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rigol-dg: Fix reading current output signal duty cycle value. 

Reading output signal duty cycle value didn't always work, since it relied
on old (cached) information about the currently active waveform. Changed to
always query channel status so this won't happen anymore.
This commit is contained in:
Timo Kokkonen 2020-10-03 16:35:10 -07:00 committed by Gerhard Sittig
parent 9ce14905cb
commit d999f2b61e
1 changed files with 2 additions and 0 deletions
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2
src/hardware/rigol-dg/api.c
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@ -490,6 +490,8 @@ static int config_get(uint32_t key, GVariant **data,
*data = g_variant_new_double(ch_status->phase); *data = g_variant_new_double(ch_status->phase);
break; break;
case SR_CONF_DUTY_CYCLE: case SR_CONF_DUTY_CYCLE:
if ((ret = rigol_dg_get_channel_state(sdi, cg)) != SR_OK)
break;
if (ch_status->wf == WF_SQUARE) { if (ch_status->wf == WF_SQUARE) {
cmd = PSG_CMD_GET_DCYCL_SQUARE; cmd = PSG_CMD_GET_DCYCL_SQUARE;
} else if (ch_status->wf == WF_PULSE) { } else if (ch_status->wf == WF_PULSE) {