saleae-logic16: Add voltage threshold conf.
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b117363ad7
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db11d7d2d0
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@ -21,6 +21,7 @@
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#include <libusb.h>
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#include <libusb.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <string.h>
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#include <math.h>
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#include "libsigrok.h"
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#include "libsigrok.h"
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#include "libsigrok-internal.h"
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#include "libsigrok-internal.h"
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#include "protocol.h"
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#include "protocol.h"
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@ -47,6 +48,7 @@ static const int32_t hwopts[] = {
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static const int32_t hwcaps[] = {
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static const int32_t hwcaps[] = {
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SR_CONF_LOGIC_ANALYZER,
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SR_CONF_LOGIC_ANALYZER,
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SR_CONF_SAMPLERATE,
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SR_CONF_SAMPLERATE,
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SR_CONF_VOLTAGE_THRESHOLD,
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/* These are really implemented in the driver, not the hardware. */
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/* These are really implemented in the driver, not the hardware. */
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SR_CONF_LIMIT_SAMPLES,
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SR_CONF_LIMIT_SAMPLES,
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@ -59,6 +61,15 @@ static const char *probe_names[NUM_PROBES + 1] = {
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NULL,
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NULL,
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};
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};
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static const struct {
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enum voltage_range range;
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gdouble low;
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gdouble high;
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} volt_thresholds[] = {
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{ VOLTAGE_RANGE_18_33_V, 0.7, 1.4 },
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{ VOLTAGE_RANGE_5_V, 1.4, 3.6 },
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};
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static const uint64_t samplerates[] = {
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static const uint64_t samplerates[] = {
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SR_KHZ(500),
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SR_KHZ(500),
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SR_MHZ(1),
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SR_MHZ(1),
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@ -192,6 +203,7 @@ static GSList *scan(GSList *options)
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if (!(devc = g_try_malloc0(sizeof(struct dev_context))))
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if (!(devc = g_try_malloc0(sizeof(struct dev_context))))
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return NULL;
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return NULL;
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devc->selected_voltage_range = VOLTAGE_RANGE_18_33_V;
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sdi->priv = devc;
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sdi->priv = devc;
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drvc->instances = g_slist_append(drvc->instances, sdi);
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drvc->instances = g_slist_append(drvc->instances, sdi);
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devices = g_slist_append(devices, sdi);
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devices = g_slist_append(devices, sdi);
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@ -430,8 +442,10 @@ static int config_get(int key, GVariant **data, const struct sr_dev_inst *sdi)
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{
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{
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struct dev_context *devc;
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struct dev_context *devc;
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struct sr_usb_dev_inst *usb;
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struct sr_usb_dev_inst *usb;
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GVariant *range[2];
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char str[128];
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char str[128];
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int ret;
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int ret;
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unsigned i;
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ret = SR_OK;
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ret = SR_OK;
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switch (key) {
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switch (key) {
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@ -452,6 +466,21 @@ static int config_get(int key, GVariant **data, const struct sr_dev_inst *sdi)
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devc = sdi->priv;
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devc = sdi->priv;
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*data = g_variant_new_uint64(devc->cur_samplerate);
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*data = g_variant_new_uint64(devc->cur_samplerate);
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break;
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break;
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case SR_CONF_VOLTAGE_THRESHOLD:
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if (!sdi)
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return SR_ERR;
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devc = sdi->priv;
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ret = SR_ERR;
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for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++)
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if (devc->selected_voltage_range ==
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volt_thresholds[i].range) {
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range[0] = g_variant_new_double(volt_thresholds[i].low);
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range[1] = g_variant_new_double(volt_thresholds[i].high);
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*data = g_variant_new_tuple(range, 2);
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ret = SR_OK;
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break;
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}
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break;
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default:
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default:
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return SR_ERR_NA;
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return SR_ERR_NA;
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}
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}
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@ -462,7 +491,9 @@ static int config_get(int key, GVariant **data, const struct sr_dev_inst *sdi)
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static int config_set(int key, GVariant *data, const struct sr_dev_inst *sdi)
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static int config_set(int key, GVariant *data, const struct sr_dev_inst *sdi)
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{
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{
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struct dev_context *devc;
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struct dev_context *devc;
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gdouble low, high;
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int ret;
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int ret;
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unsigned i;
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if (sdi->status != SR_ST_ACTIVE)
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if (sdi->status != SR_ST_ACTIVE)
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return SR_ERR_DEV_CLOSED;
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return SR_ERR_DEV_CLOSED;
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@ -477,6 +508,19 @@ static int config_set(int key, GVariant *data, const struct sr_dev_inst *sdi)
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case SR_CONF_LIMIT_SAMPLES:
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case SR_CONF_LIMIT_SAMPLES:
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devc->limit_samples = g_variant_get_uint64(data);
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devc->limit_samples = g_variant_get_uint64(data);
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break;
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break;
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case SR_CONF_VOLTAGE_THRESHOLD:
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g_variant_get(data, "(dd)", &low, &high);
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ret = SR_ERR_ARG;
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for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) {
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if (fabs(volt_thresholds[i].low - low) < 0.1 &&
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fabs(volt_thresholds[i].high - high) < 0.1) {
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devc->selected_voltage_range =
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volt_thresholds[i].range;
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ret = SR_OK;
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break;
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}
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}
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break;
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default:
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default:
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ret = SR_ERR_NA;
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ret = SR_ERR_NA;
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}
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}
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@ -486,9 +530,10 @@ static int config_set(int key, GVariant *data, const struct sr_dev_inst *sdi)
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static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi)
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static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi)
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{
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{
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GVariant *gvar;
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GVariant *gvar, *range[2];
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GVariantBuilder gvb;
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GVariantBuilder gvb;
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int ret;
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int ret;
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unsigned i;
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(void)sdi;
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(void)sdi;
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@ -509,6 +554,16 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi)
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g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
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g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
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*data = g_variant_builder_end(&gvb);
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*data = g_variant_builder_end(&gvb);
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break;
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break;
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case SR_CONF_VOLTAGE_THRESHOLD:
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g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
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for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) {
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range[0] = g_variant_new_double(volt_thresholds[i].low);
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range[1] = g_variant_new_double(volt_thresholds[i].high);
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gvar = g_variant_new_tuple(range, 2);
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g_variant_builder_add_value(&gvb, gvar);
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}
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*data = g_variant_builder_end(&gvb);
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break;
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default:
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default:
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return SR_ERR_NA;
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return SR_ERR_NA;
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}
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}
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@ -429,6 +429,9 @@ SR_PRIV int saleae_logic16_setup_acquisition(const struct sr_dev_inst *sdi,
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uint8_t clock_select, reg1, reg10;
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uint8_t clock_select, reg1, reg10;
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uint64_t div;
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uint64_t div;
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int i, ret, nchan = 0;
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int i, ret, nchan = 0;
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struct dev_context *devc;
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devc = sdi->priv;
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if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
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if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
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sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
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sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
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@ -460,6 +463,9 @@ SR_PRIV int saleae_logic16_setup_acquisition(const struct sr_dev_inst *sdi,
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return SR_ERR;
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return SR_ERR;
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}
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}
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if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
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return ret;
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if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
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if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
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return ret;
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return ret;
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@ -568,7 +574,7 @@ SR_PRIV int saleae_logic16_init_device(const struct sr_dev_inst *sdi)
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if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
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if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
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return ret;
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return ret;
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if ((ret = upload_fpga_bitstream(sdi, VOLTAGE_RANGE_18_33_V)) != SR_OK)
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if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
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return ret;
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return ret;
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return SR_OK;
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return SR_OK;
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@ -59,6 +59,9 @@ struct dev_context {
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/** The currently configured input voltage of the device */
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/** The currently configured input voltage of the device */
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enum voltage_range cur_voltage_range;
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enum voltage_range cur_voltage_range;
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/** The input voltage selected by the user */
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enum voltage_range selected_voltage_range;
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/** Channels to use */
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/** Channels to use */
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uint16_t cur_channels;
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uint16_t cur_channels;
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@ -93,6 +93,8 @@ static struct sr_config_info sr_config_info_data[] = {
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"Hold min", NULL},
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"Hold min", NULL},
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{SR_CONF_SPL_MEASUREMENT_RANGE, SR_T_UINT64_RANGE, "spl_meas_range",
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{SR_CONF_SPL_MEASUREMENT_RANGE, SR_T_UINT64_RANGE, "spl_meas_range",
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"Sound pressure level measurement range", NULL},
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"Sound pressure level measurement range", NULL},
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{SR_CONF_VOLTAGE_THRESHOLD, SR_T_DOUBLE_RANGE, "voltage_threshold",
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"Voltage threshold", NULL },
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{SR_CONF_POWER_OFF, SR_T_BOOL, "power_off",
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{SR_CONF_POWER_OFF, SR_T_BOOL, "power_off",
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"Power off", NULL},
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"Power off", NULL},
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{SR_CONF_DATA_SOURCE, SR_T_CHAR, "data_source",
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{SR_CONF_DATA_SOURCE, SR_T_CHAR, "data_source",
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@ -142,6 +142,7 @@ enum {
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SR_T_RATIONAL_VOLT,
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SR_T_RATIONAL_VOLT,
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SR_T_KEYVALUE,
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SR_T_KEYVALUE,
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SR_T_UINT64_RANGE,
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SR_T_UINT64_RANGE,
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SR_T_DOUBLE_RANGE,
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};
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};
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/** Value for sr_datafeed_packet.type. */
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/** Value for sr_datafeed_packet.type. */
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@ -681,6 +682,9 @@ enum {
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/** Min hold mode. */
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/** Min hold mode. */
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SR_CONF_HOLD_MIN,
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SR_CONF_HOLD_MIN,
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/** Logic low-high threshold range. */
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SR_CONF_VOLTAGE_THRESHOLD,
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/*--- Special stuff -------------------------------------------------*/
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/*--- Special stuff -------------------------------------------------*/
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/** Scan options supported by the driver. */
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/** Scan options supported by the driver. */
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