With trigger enabled, and with PulseView, a second (or more) acquisition
starts immediately instead of blocking. It's mandatory to try several times
to have a correct behavior.
According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf section 2.3.1
p.8, the Openbench Logic Sniffer must be reset before each arm command.
This fixes bug #809.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Openbench Logic Sniffer reset is a little more complex than a simple send.
To avoid code duplication, this patch adds a new function dedicated to
this task.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Instead of replacing the group=plugdev, simply add the TAG as well.
This allows (in most cases) the same file to be used happily on systemd
and older group based systems. Some systems may produce warnings about
non-existant groups, but it remains functional. Approach inspired by
that taken by the OpenOCD project.
This fixes parts of bug #665.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Increasing the chunk size from 512ksamples to 4Msamples leads to
slightly faster session file loading from sigrok session (*.sr) files
in frontends, while not looking too "chunky".
The performance increase is not really massive, but still noticeable.
A further increase to, say, 10 or 100Msamples shows no further
noticeable improvements.
This changes the fx2lafw code to only enable the wide_sampling (16bit)
method, if at least one of the higher eight channels is enabled. This
has the benefit, that we can use higher samplerates on 16bit LA
devices if we use only the first eight channels.
The wide sampling is also enabled if we have one or more analog
channels.
Signed-off-by: Jan Losinski <losinski@wh2.tu-dresden.de>
I've seen the following output from sigrok-cli:
CH1: 478.720 mV
CH1: -514 mV
CH1: -0 V
I added some debug, and it seems like the digits value isn't reset
to the actual value after calling sr_analog_si_prefix_friendly():
using 6 digits
value2 0.478720 digits 6
value2 -0.513536 digits 3
value2 -0.487424 digits 0
This commit fixes this by resetting the value to the actual value before.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
devc->step is not reset on acquistion start, so acquisition
starts with a different value every time. Thats annoying when
using the demo driver to debug sigrok, so lets make sure that
it's reset to 0.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
It appears that the symmetry changes of setting CC and CFLAGS correctly
for C code compilation in commit 104f02f broke things for people using
some other version of setuptools which uses those vars instead of
CXX and CXXFLAGS when compiling C++ code. In order to make this work
everywhere, set _both_ sets of variables as required for C++ compilation.
No C code is compiled by the python binding module anyway.
Soeren Apel
Gwenhael Goavec-Merou
Uwe Hermann
Marc Schink
Karl Palsson
Bert Vermeulen
Jan Losinski
Sven Schnelle
Matthieu Guillaumin
Vlad Ivanov
Marcus Comstedt