poljar (Damir Jelić)
1130e4229b
rigol-ds1xx2: Send a SR_DF_END packet before acquisition stop.
...
Without a SR_DF_END samples could be cached in the internal buffer of an output
module and never flushed, therefore they would be missing in the final output.
By sending a SR_DF_END packet we force the output to be flushed.
2013-11-15 17:00:07 +01:00
Uwe Hermann
ce4d26ddf9
Various cosmetics, whitespace, consistency fixes.
2013-07-31 13:09:48 +02:00
Uwe Hermann
decfe89d4e
Drop some lines that are no longer needed.
2013-05-10 18:30:32 +02:00
Martin Ling
9bd4c95606
rigol-ds1xx2: Use common serial code.
2013-04-24 02:10:25 +02:00
Martin Ling
6bb192bc05
rigol-ds1xx2: support digital channels.
2013-04-14 16:57:02 +02:00
Martin Ling
ee7e9bee5d
rigol-ds1xx2: fix handling of partial frames.
2013-04-14 16:57:01 +02:00
Uwe Hermann
169dbe8577
rigol-ds1xx2: Whitespace, minor fix.
...
Return SR_ERR_MALLOC for failed malloc, not SR_ERR.
2013-04-12 18:44:28 +02:00
Bert Vermeulen
254dd102e8
rigol-ds1xx2: Support for all channels, proper defaults
...
Since this driver supports devices with a control panel and display,
we take the defaults from the device -- not a set of sensible
defaults as usual.
2013-04-11 18:32:08 +02:00
Bert Vermeulen
88e429c97f
rigol-ds1xx2: fix channel numbers
...
Copyright bump, too.
2013-04-11 18:32:08 +02:00
Bert Vermeulen
a3df166f02
rigol-ds1xx2: better debugging
2013-04-11 18:32:08 +02:00
Bert Vermeulen
75d8a4e576
rigol-ds1xx2: properly send frame begin/end packets
2013-04-11 18:32:08 +02:00
Bert Vermeulen
69e19dd769
Always interleave analog data with all enabled probes.
...
The new "probes" field in sr_datafeed_analog contains a copy
of all enabled struct sr_probe.
2013-01-23 03:40:44 +01:00
Uwe Hermann
29d957ceae
rigol-ds1xx2: Cosmetics, whitespace.
2013-01-03 19:04:11 +01:00
Martin Ling
e0b7d23ce8
rigol-ds1xx2: First working version.
...
Currently hardcoded to use /dev/usbtmc1. Analog data readout works.
2013-01-03 18:41:29 +01:00
Martin Ling
f4816ac6cc
rigol-ds1xx2: Initial driver skeleton.
2013-01-03 18:41:28 +01:00