Bert Vermeulen
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34e4813f2e
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inout module infrastructure + binary input module
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2010-04-30 16:09:47 -07:00 |
Håvard Espeland
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28a35d8ab3
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This commit adds initial support for the Asix Sigma Logic Analyzer. Currently, only 200 MHz is supported, and only with software trigger. Firmware for the device will be distributed separately, with permission from the vendor.
Signed-off-by: Håvard Espeland <gus@ping.uio.no>
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2010-04-27 13:16:01 -07:00 |
Uwe Hermann
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62c8202582
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libsigrok: More coding style fixes.
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2010-04-15 20:16:53 +02:00 |
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Uwe Hermann
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1c5b9d302c
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Add raw binary output format.
Also, rename the "bin" format to "bits" for now to avoid confusion.
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2010-04-12 21:22:58 +02:00 |
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Uwe Hermann
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25e7d9b115
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Factor out common sigrok_samplerate_string().
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2010-04-07 20:13:57 +02:00 |
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Uwe Hermann
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e2ad47b5b0
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Gnuplot output format support.
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2010-04-06 16:54:37 +02:00 |
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Uwe Hermann
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4c9ffa83cf
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Initial Value Change Dump (VCD) output support.
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2010-04-04 13:19:20 +02:00 |
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Uwe Hermann
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a695d6c075
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Rename libbackend to libsigrok.
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2010-04-02 20:27:59 +02:00 |
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Uwe Hermann
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a1bb33afbd
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Start of code base layout restructuring.
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2010-04-02 20:27:54 +02:00 |