406 lines
10 KiB
C
406 lines
10 KiB
C
/*
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* This file is part of the sigrok project.
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*
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* Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "protocol.h"
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extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
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static struct sr_dev_driver *di = &link_mso19_driver_info;
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SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
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{
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struct dev_context *devc = sdi->priv;
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uint16_t ops[16];
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uint16_t dso_trigger = mso_calc_raw_from_mv(devc);
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dso_trigger &= 0x3ff;
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if ((!devc->trigger_slope && devc->trigger_chan == 1) ||
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(devc->trigger_slope &&
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(devc->trigger_chan == 0 ||
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devc->trigger_chan == 2 ||
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devc->trigger_chan == 3)))
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dso_trigger |= 0x400;
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switch (devc->trigger_chan) {
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case 1:
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dso_trigger |= 0xe000;
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case 2:
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dso_trigger |= 0x4000;
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break;
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case 3:
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dso_trigger |= 0x2000;
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break;
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case 4:
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dso_trigger |= 0xa000;
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break;
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case 5:
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dso_trigger |= 0x8000;
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break;
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default:
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case 0:
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break;
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}
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switch (devc->trigger_outsrc) {
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case 1:
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dso_trigger |= 0x800;
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break;
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case 2:
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dso_trigger |= 0x1000;
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break;
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case 3:
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dso_trigger |= 0x1800;
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break;
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}
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ops[0] = mso_trans(5, devc->la_trigger);
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ops[1] = mso_trans(6, devc->la_trigger_mask);
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ops[2] = mso_trans(3, dso_trigger & 0xff);
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ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff);
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ops[4] = mso_trans(11,
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devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));
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/* Select the SPI/I2C trigger config bank */
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ops[5] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
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/* Configure the SPI/I2C protocol trigger */
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ops[6] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
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ops[7] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
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ops[8] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
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ops[9] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
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ops[10] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
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ops[11] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
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ops[12] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
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ops[13] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
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ops[14] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
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/* Select the default config bank */
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ops[15] = mso_trans(REG_CTL2, devc->ctlbase2);
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return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
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}
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SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi)
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{
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struct dev_context *devc = sdi->priv;
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return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
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}
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SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
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{
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uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
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struct dev_context *devc = sdi->priv;
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sr_dbg("Requesting buffer dump.");
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return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
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}
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SR_PRIV int mso_arm(struct sr_dev_inst *sdi)
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{
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struct dev_context *devc = sdi->priv;
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uint16_t ops[] = {
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mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
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mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
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mso_trans(REG_CTL1, devc->ctlbase1),
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};
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sr_dbg("Requesting trigger arm.");
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return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
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}
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SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
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{
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struct dev_context *devc = sdi->priv;
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uint16_t ops[] = {
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mso_trans(REG_CTL1, devc->ctlbase1 | 8),
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mso_trans(REG_CTL1, devc->ctlbase1),
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};
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sr_dbg("Requesting forced capture.");
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return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
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}
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SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
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{
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struct dev_context *devc = sdi->priv;
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uint16_t ops[] = {
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mso_trans(REG_DAC1, (val >> 8) & 0xff),
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mso_trans(REG_DAC2, val & 0xff),
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mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
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};
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sr_dbg("Setting dac word to 0x%x.", val);
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return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
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}
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SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
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{
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return (uint16_t) (0x200 -
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((devc->dso_trigger_voltage / devc->dso_probe_attn) /
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devc->vbit));
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}
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SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
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struct dev_context *devc)
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{
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unsigned int u1, u2, u3, u4, u5, u6;
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iProduct = iProduct;
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/* FIXME: This code is in the original app, but I think its
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* used only for the GUI */
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/* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
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devc->num_sample_rates = 0x16;
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else
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devc->num_sample_rates = 0x10; */
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/* parse iSerial */
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if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
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&u1, &u2, &u3, &u4, &u5, &u6) != 6)
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return SR_ERR;
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devc->hwmodel = u4;
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devc->hwrev = u5;
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devc->serial = u6;
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devc->vbit = u1 / 10000;
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if (devc->vbit == 0)
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devc->vbit = 4.19195;
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devc->dac_offset = u2;
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if (devc->dac_offset == 0)
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devc->dac_offset = 0x1ff;
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devc->offset_range = u3;
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if (devc->offset_range == 0)
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devc->offset_range = 0x17d;
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/*
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* FIXME: There is more code on the original software to handle
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* bigger iSerial strings, but as I can't test on my device
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* I will not implement it yet
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*/
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return SR_OK;
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}
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SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
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uint16_t payload[], int n)
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{
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int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
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char *p, *buf;
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ret = SR_ERR;
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if (serial->fd < 0)
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goto ret;
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if (!(buf = g_try_malloc(s))) {
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sr_err("Failed to malloc message buffer.");
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ret = SR_ERR_MALLOC;
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goto ret;
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}
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p = buf;
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memcpy(p, mso_head, sizeof(mso_head));
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p += sizeof(mso_head);
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for (i = 0; i < n; i++) {
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*(uint16_t *) p = htons(payload[i]);
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p += 2;
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}
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memcpy(p, mso_foot, sizeof(mso_foot));
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w = 0;
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while (w < s) {
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ret = serial_write(serial, buf + w, s - w);
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if (ret < 0) {
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ret = SR_ERR;
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goto free;
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}
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w += ret;
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}
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ret = SR_OK;
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free:
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g_free(buf);
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ret:
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return ret;
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}
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SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
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{
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struct dev_context *devc = sdi->priv;
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uint16_t ops[2];
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ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
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ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
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devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;
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sr_dbg("Requesting ADC reset.");
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return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
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}
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SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
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{
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struct sr_datafeed_packet packet;
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struct dev_context *devc;
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devc = sdi->priv;
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sr_source_remove(devc->serial->fd);
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/* Terminate session */
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packet.type = SR_DF_END;
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sr_session_send(sdi, &packet);
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}
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SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
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{
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uint16_t ops[] = {
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mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
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mso_trans(REG_CLKRATE2, val & 0xff),
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};
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sr_dbg("Setting clkrate word to 0x%x.", val);
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return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
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}
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SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
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{
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struct dev_context *devc = sdi->priv;
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unsigned int i;
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int ret = SR_ERR;
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for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
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if (rate_map[i].rate == rate) {
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devc->ctlbase2 = rate_map[i].slowmode;
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ret = mso_clkrate_out(devc->serial, rate_map[i].val);
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if (ret == SR_OK)
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devc->cur_rate = rate;
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return ret;
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}
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}
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return ret;
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}
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SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
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{
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uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
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int ret;
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sr_dbg("Requesting trigger state.");
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ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
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if (info == NULL || ret != SR_OK)
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return ret;
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uint8_t buf = 0;
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if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
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ret = SR_ERR;
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*info = buf;
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sr_dbg("Trigger state is: 0x%x.", *info);
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return ret;
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}
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SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
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{
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struct sr_datafeed_packet packet;
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struct sr_datafeed_logic logic;
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struct sr_dev_inst *sdi;
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struct drv_context *drvc;
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struct dev_context *devc;
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GSList *l;
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int num_channels, offset, i, j;
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unsigned char byte;
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drvc = di->priv;
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/* Find this device's devc struct by its fd. */
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devc = NULL;
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for (l = drvc->instances; l; l = l->next) {
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sdi = l->data;
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devc = sdi->priv;
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if (devc->serial->fd == fd)
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break;
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devc = NULL;
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}
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if (!devc)
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/* Shouldn't happen. */
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return TRUE;
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(void)revents;
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uint8_t in[1024];
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size_t s = serial_read(devc->serial, in, sizeof(in));
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if (s <= 0)
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return FALSE;
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/* No samples */
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if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
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devc->trigger_state = in[0];
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if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
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mso_read_buffer(sdi);
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devc->buffer_n = 0;
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} else {
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mso_check_trigger(devc->serial, NULL);
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}
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return FALSE;
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}
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/* the hardware always dumps 1024 samples, 24bits each */
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if (devc->buffer_n < 3072) {
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memcpy(devc->buffer + devc->buffer_n, in, s);
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devc->buffer_n += s;
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}
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if (devc->buffer_n < 3072)
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return FALSE;
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/* do the conversion */
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uint8_t logic_out[1024];
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double analog_out[1024];
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for (i = 0; i < 1024; i++) {
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/* FIXME: Need to do conversion to mV */
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analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
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((devc->buffer[i * 3 + 1] & 0xf) << 6);
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logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
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((devc->buffer[i * 3 + 2] & 0x3f) << 2);
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}
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packet.type = SR_DF_LOGIC;
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packet.payload = &logic;
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logic.length = 1024;
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logic.unitsize = 1;
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logic.data = logic_out;
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sr_session_send(cb_data, &packet);
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// Dont bother fixing this yet, keep it "old style"
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/*
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packet.type = SR_DF_ANALOG;
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packet.length = 1024;
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packet.unitsize = sizeof(double);
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packet.payload = analog_out;
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sr_session_send(ctx->session_dev_id, &packet);
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*/
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packet.type = SR_DF_END;
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sr_session_send(devc->session_dev_id, &packet);
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}
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