678 lines
16 KiB
C
678 lines
16 KiB
C
/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
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* Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include "libsigrok.h"
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#include "libsigrok-internal.h"
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#include "analyzer.h"
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#include "gl_usb.h"
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#include "protocol.h"
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enum {
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HARD_DATA_CHECK_SUM = 0x00,
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PASS_WORD,
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DEV_ID0 = 0x10,
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DEV_ID1,
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START_STATUS = 0x20,
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DEV_STATUS = 0x21,
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FREQUENCY_REG0 = 0x30,
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FREQUENCY_REG1,
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FREQUENCY_REG2,
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FREQUENCY_REG3,
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FREQUENCY_REG4,
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MEMORY_LENGTH,
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CLOCK_SOURCE,
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TRIGGER_STATUS0 = 0x40,
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TRIGGER_STATUS1,
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TRIGGER_STATUS2,
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TRIGGER_STATUS3,
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TRIGGER_STATUS4,
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TRIGGER_STATUS5,
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TRIGGER_STATUS6,
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TRIGGER_STATUS7,
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TRIGGER_STATUS8,
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TRIGGER_COUNT0 = 0x50,
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TRIGGER_COUNT1,
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TRIGGER_LEVEL0 = 0x55,
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TRIGGER_LEVEL1,
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TRIGGER_LEVEL2,
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TRIGGER_LEVEL3,
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RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
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RAMSIZE_TRIGGERBAR_ADDRESS1,
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RAMSIZE_TRIGGERBAR_ADDRESS2,
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TRIGGERBAR_ADDRESS0,
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TRIGGERBAR_ADDRESS1,
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TRIGGERBAR_ADDRESS2,
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DONT_CARE_TRIGGERBAR,
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FILTER_ENABLE = 0x70,
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FILTER_STATUS,
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ENABLE_DELAY_TIME0 = 0x7a,
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ENABLE_DELAY_TIME1,
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ENABLE_INSERT_DATA0 = 0x80,
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ENABLE_INSERT_DATA1,
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ENABLE_INSERT_DATA2,
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ENABLE_INSERT_DATA3,
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COMPRESSION_TYPE0,
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COMPRESSION_TYPE1,
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TRIGGER_ADDRESS0 = 0x90,
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TRIGGER_ADDRESS1,
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TRIGGER_ADDRESS2,
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NOW_ADDRESS0 = 0x96,
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NOW_ADDRESS1,
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NOW_ADDRESS2,
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STOP_ADDRESS0 = 0x9b,
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STOP_ADDRESS1,
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STOP_ADDRESS2,
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READ_RAM_STATUS = 0xa0,
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};
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static int g_trigger_status[9] = { 0 };
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static int g_trigger_count = 1;
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static int g_filter_status[8] = { 0 };
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static int g_filter_enable = 0;
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static int g_freq_value = 1;
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static int g_freq_scale = FREQ_SCALE_MHZ;
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static int g_memory_size = MEMORY_SIZE_8K;
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static int g_ramsize_triggerbar_addr = 2 * 1024;
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static int g_triggerbar_addr = 0;
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static int g_compression = COMPRESSION_NONE;
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static int g_thresh = 0x31; /* 1.5V */
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/* Maybe unk specifies an "endpoint" or "register" of sorts. */
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static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
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unsigned char flags)
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{
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assert(unk <= 3);
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return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
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}
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#if 0
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static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
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{
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int reg0 = 0, divisor = 0, reg2 = 0;
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switch (scale) {
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case FREQ_SCALE_MHZ: /* MHz */
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if (freq >= 100 && freq <= 200) {
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reg0 = freq * 0.1;
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divisor = 1;
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reg2 = 0;
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break;
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}
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if (freq >= 50 && freq < 100) {
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reg0 = freq * 0.2;
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divisor = 2;
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reg2 = 0;
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break;
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}
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if (freq >= 10 && freq < 50) {
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if (freq == 25) {
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reg0 = 25;
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divisor = 5;
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reg2 = 1;
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break;
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} else {
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reg0 = freq * 0.5;
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divisor = 5;
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reg2 = 1;
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break;
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}
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}
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if (freq >= 2 && freq < 10) {
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divisor = 5;
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reg0 = freq * 2;
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reg2 = 2;
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break;
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}
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if (freq == 1) {
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divisor = 5;
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reg2 = 16;
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reg0 = 5;
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break;
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}
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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case FREQ_SCALE_HZ: /* Hz */
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if (freq >= 500 && freq < 1000) {
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reg0 = freq * 0.01;
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divisor = 10;
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reg2 = 64;
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break;
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}
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if (freq >= 300 && freq < 500) {
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reg0 = freq * 0.005 * 8;
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divisor = 5;
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reg2 = 67;
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break;
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}
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if (freq >= 100 && freq < 300) {
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reg0 = freq * 0.005 * 16;
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divisor = 5;
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reg2 = 68;
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break;
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}
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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case FREQ_SCALE_KHZ: /* kHz */
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if (freq >= 500 && freq < 1000) {
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reg0 = freq * 0.01;
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divisor = 5;
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reg2 = 17;
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break;
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}
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if (freq >= 100 && freq < 500) {
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reg0 = freq * 0.05;
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divisor = 5;
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reg2 = 32;
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break;
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}
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if (freq >= 50 && freq < 100) {
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reg0 = freq * 0.1;
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divisor = 5;
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reg2 = 33;
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break;
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}
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if (freq >= 10 && freq < 50) {
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if (freq == 25) {
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reg0 = 25;
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divisor = 5;
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reg2 = 49;
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break;
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}
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reg0 = freq * 0.5;
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divisor = 5;
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reg2 = 48;
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break;
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}
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if (freq >= 2 && freq < 10) {
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divisor = 5;
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reg0 = freq * 2;
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reg2 = 50;
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break;
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}
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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default:
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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}
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sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
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"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
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freq, scale, divisor, reg0, 0x02, reg2);
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if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
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return -1; /* Divisor maybe? */
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if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
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return -1; /* 10 / 0.2 */
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if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
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return -1; /* Always 2 */
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if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
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return -1;
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return 0;
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}
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#endif
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/*
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* It seems that ...
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* FREQUENCT_REG0 - division factor (?)
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* FREQUENCT_REG1 - multiplication factor (?)
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* FREQUENCT_REG4 - clock selection (?)
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*
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* clock selection
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* 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
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* 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
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* 2 2.5MHz . . 50 2.5kHz 66 250Hz
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* . . . . 67 125Hz
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* . . . . 68 62.5Hz
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*/
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static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
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{
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struct freq_factor {
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int freq;
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int scale;
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int sel;
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int div;
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int mul;
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};
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static const struct freq_factor f[] = {
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{ 200, FREQ_SCALE_MHZ, 0, 1, 20 },
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{ 150, FREQ_SCALE_MHZ, 0, 1, 15 },
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{ 100, FREQ_SCALE_MHZ, 0, 1, 10 },
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{ 80, FREQ_SCALE_MHZ, 0, 2, 16 },
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{ 50, FREQ_SCALE_MHZ, 0, 2, 10 },
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{ 25, FREQ_SCALE_MHZ, 1, 5, 25 },
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{ 10, FREQ_SCALE_MHZ, 1, 5, 10 },
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{ 1, FREQ_SCALE_MHZ, 16, 5, 5 },
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{ 800, FREQ_SCALE_KHZ, 17, 5, 8 },
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{ 400, FREQ_SCALE_KHZ, 32, 5, 20 },
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{ 200, FREQ_SCALE_KHZ, 32, 5, 10 },
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{ 100, FREQ_SCALE_KHZ, 32, 5, 5 },
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{ 50, FREQ_SCALE_KHZ, 33, 5, 5 },
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{ 25, FREQ_SCALE_KHZ, 49, 5, 25 },
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{ 5, FREQ_SCALE_KHZ, 50, 5, 10 },
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{ 1, FREQ_SCALE_KHZ, 64, 5, 5 },
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{ 500, FREQ_SCALE_HZ, 64, 10, 5 },
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{ 100, FREQ_SCALE_HZ, 68, 5, 8 },
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{ 0, 0, 0, 0, 0 }
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};
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int i;
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for (i = 0; f[i].freq; i++) {
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if (scale == f[i].scale && freq == f[i].freq)
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break;
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}
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if (!f[i].freq)
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return -1;
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sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
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"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
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freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
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if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
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return -1;
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if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
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return -1;
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if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
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return -1;
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if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
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return -1;
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return 0;
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}
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static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
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unsigned int address)
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{
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gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
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gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
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gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
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}
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static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
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unsigned int address)
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{
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gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
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gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
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gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
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}
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static void __analyzer_set_compression(libusb_device_handle *devh,
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unsigned int type)
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{
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gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
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gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
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}
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static void __analyzer_set_trigger_count(libusb_device_handle *devh,
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unsigned int count)
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{
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gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
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gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
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}
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static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
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{
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gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
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gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
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gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
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gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
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}
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static void analyzer_set_filter(libusb_device_handle *devh)
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{
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int i;
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gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
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for (i = 0; i < 8; i++)
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gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
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}
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SR_PRIV void analyzer_reset(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
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analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
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}
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SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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}
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SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
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{
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int status;
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while (1) {
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status = gl_reg_read(devh, DEV_STATUS);
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if ((!set || (status & set)) && ((status & unset) == 0))
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return;
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}
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}
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SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
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/* Prep for bulk reads */
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gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
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}
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SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
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unsigned int size)
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{
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return gl_read_bulk(devh, buffer, size);
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}
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SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 3, STATUS_FLAG_20);
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analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
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}
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SR_PRIV void analyzer_start(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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analyzer_write_status(devh, 1, STATUS_FLAG_GO);
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}
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SR_PRIV void analyzer_configure(libusb_device_handle *devh)
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{
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int i;
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/* Write_Start_Status */
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analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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/* Start_Config_Outside_Device ? */
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analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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/* SetData_To_Frequence_Reg */
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__analyzer_set_freq(devh, g_freq_value, g_freq_scale);
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/* SetMemory_Length */
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gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
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/* Sele_Inside_Outside_Clock */
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gl_reg_write(devh, CLOCK_SOURCE, 0x03);
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/* Set_Trigger_Status */
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for (i = 0; i < 9; i++)
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gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
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__analyzer_set_trigger_count(devh, g_trigger_count);
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/* Set_Trigger_Level */
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gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
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gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
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gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
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gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);
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/* Size of actual memory >> 2 */
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__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
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__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
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/* Set_Dont_Care_TriggerBar */
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gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
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/* Enable_Status */
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analyzer_set_filter(devh);
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/* Set_Enable_Delay_Time */
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gl_reg_write(devh, 0x7a, 0x00);
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gl_reg_write(devh, 0x7b, 0x00);
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analyzer_write_enable_insert_data(devh);
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__analyzer_set_compression(devh, g_compression);
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}
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SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct sr_trigger *trigger;
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struct sr_trigger_stage *stage;
|
|
struct sr_trigger_match *match;
|
|
GSList *l, *m;
|
|
int channel;
|
|
|
|
devc = sdi->priv;
|
|
|
|
if (!(trigger = sr_session_trigger_get(sdi->session)))
|
|
return SR_OK;
|
|
|
|
for (l = trigger->stages; l; l = l->next) {
|
|
stage = l->data;
|
|
for (m = stage->matches; m; m = m->next) {
|
|
match = m->data;
|
|
devc->trigger = 1;
|
|
if (!match->channel->enabled)
|
|
/* Ignore disabled channels with a trigger. */
|
|
continue;
|
|
channel = match->channel->index;
|
|
switch (match->match) {
|
|
case SR_TRIGGER_ZERO:
|
|
g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
|
|
case SR_TRIGGER_ONE:
|
|
g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
|
|
break;
|
|
default:
|
|
sr_err("Unsupported match %d", match->match);
|
|
return SR_ERR;
|
|
}
|
|
}
|
|
}
|
|
|
|
return SR_OK;
|
|
}
|
|
|
|
SR_PRIV void analyzer_add_filter(int channel, int type)
|
|
{
|
|
int i;
|
|
|
|
if (type != FILTER_HIGH && type != FILTER_LOW)
|
|
return;
|
|
if ((channel & 0xf) >= 8)
|
|
return;
|
|
|
|
if (channel & CHANNEL_A)
|
|
i = 0;
|
|
else if (channel & CHANNEL_B)
|
|
i = 2;
|
|
else if (channel & CHANNEL_C)
|
|
i = 4;
|
|
else if (channel & CHANNEL_D)
|
|
i = 6;
|
|
else
|
|
return;
|
|
|
|
if ((channel & 0xf) >= 4) {
|
|
i++;
|
|
channel -= 4;
|
|
}
|
|
|
|
g_filter_status[i] |=
|
|
1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
|
|
|
|
g_filter_enable = 1;
|
|
}
|
|
|
|
SR_PRIV void analyzer_set_trigger_count(int count)
|
|
{
|
|
g_trigger_count = count;
|
|
}
|
|
|
|
SR_PRIV void analyzer_set_freq(int freq, int scale)
|
|
{
|
|
g_freq_value = freq;
|
|
g_freq_scale = scale;
|
|
}
|
|
|
|
SR_PRIV void analyzer_set_memory_size(unsigned int size)
|
|
{
|
|
g_memory_size = size;
|
|
}
|
|
|
|
SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
|
|
{
|
|
g_ramsize_triggerbar_addr = address;
|
|
}
|
|
|
|
SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
|
|
{
|
|
return g_ramsize_triggerbar_addr;
|
|
}
|
|
|
|
SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
|
|
{
|
|
g_triggerbar_addr = address;
|
|
}
|
|
|
|
SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
|
|
{
|
|
return g_triggerbar_addr;
|
|
}
|
|
|
|
SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
|
|
{
|
|
return gl_reg_read(devh, DEV_STATUS);
|
|
}
|
|
|
|
SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
|
|
{
|
|
return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
|
|
}
|
|
|
|
SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
|
|
{
|
|
return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
|
|
STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
|
|
}
|
|
|
|
SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
|
|
{
|
|
return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
|
|
NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
|
|
}
|
|
|
|
SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
|
|
{
|
|
return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
|
|
TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
|
|
}
|
|
|
|
SR_PRIV void analyzer_set_compression(unsigned int type)
|
|
{
|
|
g_compression = type;
|
|
}
|
|
|
|
SR_PRIV void analyzer_set_voltage_threshold(int thresh)
|
|
{
|
|
g_thresh = thresh;
|
|
}
|
|
|
|
SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
|
|
{
|
|
analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
|
|
}
|
|
|
|
SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
|
|
{
|
|
analyzer_wait(devh, 0, STATUS_BUSY);
|
|
}
|
|
|
|
SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
|
|
void *output, unsigned int output_len)
|
|
{
|
|
unsigned char *in = input;
|
|
unsigned char *out = output;
|
|
unsigned int A, B, C, count;
|
|
unsigned int written = 0;
|
|
|
|
while (input_len > 0) {
|
|
A = *in++;
|
|
B = *in++;
|
|
C = *in++;
|
|
count = (*in++) + 1;
|
|
|
|
if (count > output_len)
|
|
count = output_len;
|
|
output_len -= count;
|
|
written += count;
|
|
|
|
while (count--) {
|
|
*out++ = A;
|
|
*out++ = B;
|
|
*out++ = C;
|
|
*out++ = 0; /* Channel D */
|
|
}
|
|
|
|
input_len -= 4;
|
|
if (output_len == 0)
|
|
break;
|
|
}
|
|
|
|
return written;
|
|
}
|