264 lines
7.0 KiB
C
264 lines
7.0 KiB
C
/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
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#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
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#define LOG_PREFIX "sysclk-lwla"
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#include "lwla.h"
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#include "libsigrok.h"
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#include "libsigrok-internal.h"
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#include <stdint.h>
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#include <glib.h>
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/* For now, only the LWLA1034 is supported.
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*/
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#define VENDOR_NAME "SysClk"
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#define MODEL_NAME "LWLA1034"
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#define USB_VID_PID "2961.6689"
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#define USB_INTERFACE 0
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#define USB_TIMEOUT 3000 /* ms */
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#define NUM_PROBES 34
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#define TRIGGER_TYPES "01fr"
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/* Bit mask covering all 34 channels.
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*/
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#define ALL_CHANNELS_MASK (((uint64_t)1 << NUM_PROBES) - 1)
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/** Unit and packet size for the sigrok logic datafeed.
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*/
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#define UNIT_SIZE ((NUM_PROBES + 7) / 8)
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#define PACKET_LENGTH 10000 /* units */
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/** Size of the acquisition buffer in device memory units.
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*/
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#define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */
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/** Number of device memory units (36 bit) to read at a time. Slices of 8
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* consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
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* length should be a multiple of 8 to ensure alignment to slice boundaries.
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*
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* Experimentation has shown that reading chunks larger than about 1024 bytes
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* is unreliable. The threshold seems to relate to the buffer size on the FX2
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* USB chip: The configured endpoint buffer size is 512, and with double or
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* triple buffering enabled a multiple of 512 bytes can be kept in fly.
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*
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* The vendor software limits reads to 120 words (15 slices, 540 bytes) at
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* a time. So far, it appears safe to increase this to 224 words (28 slices,
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* 1008 bytes), thus making the most of two 512 byte buffers.
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*/
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#define READ_CHUNK_LEN (28 * 8)
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/** Calculate the required buffer size in 32-bit units for reading a given
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* number of device memory words. Rounded to a multiple of 8 device words.
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*/
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#define LWLA1034_MEMBUF_LEN(count) (((count) + 7) / 8 * 9)
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/** Maximum number of 16-bit words sent at a time during acquisition.
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* Used for allocating the libusb transfer buffer.
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*/
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#define MAX_ACQ_SEND_WORDS 8 /* 5 for memory read request plus stuffing */
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/** Maximum number of 32-bit words received at a time during acquisition.
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* Round to the next multiple of the endpoint buffer size to avoid nasty
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* transfer overflow conditions on hiccups.
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*/
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#define MAX_ACQ_RECV_LEN ((READ_CHUNK_LEN / 8 * 9 + 127) / 128 * 128)
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/** Maximum length of a register write sequence.
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*/
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#define MAX_REG_WRITE_SEQ_LEN 5
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/** Default configured samplerate.
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*/
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#define DEFAULT_SAMPLERATE SR_MHZ(125)
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/** Maximum configurable sample count limit.
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*/
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#define MAX_LIMIT_SAMPLES (UINT64_C(1) << 48)
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/** Maximum configurable capture duration in milliseconds.
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*/
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#define MAX_LIMIT_MSEC (UINT64_C(1) << 32)
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/** LWLA1034 FPGA clock configurations.
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*/
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enum clock_config {
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CONF_CLOCK_NONE,
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CONF_CLOCK_INT,
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CONF_CLOCK_EXT_RISE,
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CONF_CLOCK_EXT_FALL,
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};
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/** Available clock sources.
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*/
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enum clock_source {
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CLOCK_INTERNAL,
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CLOCK_EXT_CLK,
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};
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/** Available trigger sources.
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*/
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enum trigger_source {
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TRIGGER_CHANNELS = 0,
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TRIGGER_EXT_TRG,
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};
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/** Available edge choices for the external clock and trigger inputs.
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*/
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enum signal_edge {
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EDGE_POSITIVE = 0,
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EDGE_NEGATIVE,
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};
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/** LWLA device states.
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*/
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enum device_state {
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STATE_IDLE = 0,
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STATE_START_CAPTURE,
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STATE_STATUS_WAIT,
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STATE_STATUS_REQUEST,
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STATE_STATUS_RESPONSE,
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STATE_STOP_CAPTURE,
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STATE_LENGTH_REQUEST,
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STATE_LENGTH_RESPONSE,
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STATE_READ_PREPARE,
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STATE_READ_REQUEST,
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STATE_READ_RESPONSE,
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STATE_READ_END,
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};
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/** LWLA run-length encoding states.
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*/
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enum rle_state {
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RLE_STATE_DATA,
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RLE_STATE_LEN
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};
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/** LWLA sample acquisition and decompression state.
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*/
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struct acquisition_state {
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uint64_t sample;
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uint64_t run_len;
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/** Maximum number of samples to process. */
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uint64_t samples_max;
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/** Number of samples sent to the session bus. */
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uint64_t samples_done;
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/** Maximum duration of capture, in milliseconds. */
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uint64_t duration_max;
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/** Running capture duration since trigger event. */
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uint64_t duration_now;
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/** Capture memory fill level. */
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size_t mem_addr_fill;
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size_t mem_addr_done;
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size_t mem_addr_next;
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size_t mem_addr_stop;
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size_t out_index;
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struct libusb_transfer *xfer_in;
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struct libusb_transfer *xfer_out;
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unsigned int capture_flags;
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enum rle_state rle;
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/** Whether to bypass the clock divider. */
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gboolean bypass_clockdiv;
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/* Payload data buffers for incoming and outgoing transfers. */
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uint32_t xfer_buf_in[MAX_ACQ_RECV_LEN];
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uint16_t xfer_buf_out[MAX_ACQ_SEND_WORDS];
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/* Payload buffer for sigrok logic packets. */
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uint8_t out_packet[PACKET_LENGTH * UNIT_SIZE];
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};
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/** Private, per-device-instance driver context.
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*/
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struct dev_context {
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/** The samplerate selected by the user. */
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uint64_t samplerate;
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/** The maximimum sampling duration, in milliseconds. */
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uint64_t limit_msec;
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/** The maximimum number of samples to acquire. */
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uint64_t limit_samples;
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/** Channels to use. */
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uint64_t channel_mask;
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uint64_t trigger_mask;
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uint64_t trigger_edge_mask;
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uint64_t trigger_values;
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struct acquisition_state *acquisition;
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struct regval_pair reg_write_seq[MAX_REG_WRITE_SEQ_LEN];
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int reg_write_pos;
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int reg_write_len;
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enum device_state state;
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/** The currently active clock configuration of the device. */
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enum clock_config cur_clock_config;
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/** Clock source configuration setting. */
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enum clock_source cfg_clock_source;
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/** Clock edge configuration setting. */
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enum signal_edge cfg_clock_edge;
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/** Trigger source configuration setting. */
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enum trigger_source cfg_trigger_source;
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/** Trigger slope configuration setting. */
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enum signal_edge cfg_trigger_slope;
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/* Indicates that stopping the acquisition is currently in progress. */
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gboolean stopping_in_progress;
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/* Indicates whether a transfer failed. */
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gboolean transfer_error;
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};
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SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void);
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SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq);
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SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_abort_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data);
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#endif /* !LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H */
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