178 lines
5.4 KiB
C
178 lines
5.4 KiB
C
/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
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* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
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#define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
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/* Modified protocol commands & flags used by DSLogic */
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#define DS_CMD_GET_FW_VERSION 0xb0
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#define DS_CMD_GET_REVID_VERSION 0xb1
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#define DS_CMD_START 0xb2
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#define DS_CMD_CONFIG 0xb3
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#define DS_CMD_SETTING 0xb4
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#define DS_CMD_CONTROL 0xb5
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#define DS_CMD_STATUS 0xb6
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#define DS_CMD_STATUS_INFO 0xb7
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#define DS_CMD_WR_REG 0xb8
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#define DS_CMD_WR_NVM 0xb9
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#define DS_CMD_RD_NVM 0xba
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#define DS_CMD_RD_NVM_PRE 0xbb
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#define DS_CMD_GET_HW_INFO 0xbc
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#define DS_NUM_TRIGGER_STAGES 16
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#define DS_START_FLAGS_STOP (1 << 7)
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#define DS_START_FLAGS_CLK_48MHZ (1 << 6)
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#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
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#define DS_START_FLAGS_MODE_LA (1 << 4)
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#define DS_ADDR_COMB 0x68
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#define DS_ADDR_EEWP 0x70
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#define DS_ADDR_VTH 0x78
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#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
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#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
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#define DS_MODE_TRIG_EN (1 << 0)
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#define DS_MODE_CLK_TYPE (1 << 1)
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#define DS_MODE_CLK_EDGE (1 << 2)
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#define DS_MODE_RLE_MODE (1 << 3)
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#define DS_MODE_DSO_MODE (1 << 4)
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#define DS_MODE_HALF_MODE (1 << 5)
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#define DS_MODE_QUAR_MODE (1 << 6)
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#define DS_MODE_ANALOG_MODE (1 << 7)
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#define DS_MODE_FILTER (1 << 8)
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#define DS_MODE_INSTANT (1 << 9)
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#define DS_MODE_STRIG_MODE (1 << 11)
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#define DS_MODE_STREAM_MODE (1 << 12)
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#define DS_MODE_LPB_TEST (1 << 13)
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#define DS_MODE_EXT_TEST (1 << 14)
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#define DS_MODE_INT_TEST (1 << 15)
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enum dslogic_operation_modes {
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DS_OP_NORMAL,
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DS_OP_INTERNAL_TEST,
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DS_OP_EXTERNAL_TEST,
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DS_OP_LOOPBACK_TEST,
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};
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enum {
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DS_VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
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DS_VOLTAGE_RANGE_5_V, /* 5V logic */
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};
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enum {
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DS_EDGE_RISING,
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DS_EDGE_FALLING,
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};
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struct dslogic_version {
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uint8_t major;
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uint8_t minor;
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};
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struct dslogic_mode {
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uint8_t flags;
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uint8_t sample_delay_h;
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uint8_t sample_delay_l;
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};
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struct dslogic_trigger_pos {
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uint32_t real_pos;
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uint32_t ram_saddr;
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uint32_t remain_cnt;
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uint8_t first_block[500];
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};
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/*
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* The FPGA is configured with TLV tuples. Length is specified as the
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* number of 16-bit words, and the (type, length) header is in some
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* cases padded with 0xffff.
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*/
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#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
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#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
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#define DS_CFG_START 0xf5a5f5a5
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#define DS_CFG_MODE _DS_CFG(0, 1)
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#define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2)
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#define DS_CFG_COUNT _DS_CFG_PAD(3, 2)
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#define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2)
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#define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
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#define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2)
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#define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2)
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#define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16)
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#define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16)
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#define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16)
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#define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16)
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#define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16)
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#define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16)
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#define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16)
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#define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16)
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#define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16)
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#define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16)
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#define DS_CFG_END 0xfa5afa5a
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struct dslogic_fpga_config {
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uint32_t sync;
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uint16_t mode_header;
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uint16_t mode;
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uint32_t divider_header;
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uint32_t divider;
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uint32_t count_header;
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uint32_t count;
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uint32_t trig_pos_header;
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uint32_t trig_pos;
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uint16_t trig_glb_header;
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uint16_t trig_glb;
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uint32_t trig_adp_header;
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uint32_t trig_adp;
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uint32_t trig_sda_header;
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uint32_t trig_sda;
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uint32_t trig_mask0_header;
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uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_mask1_header;
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uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_value0_header;
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uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_value1_header;
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uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_edge0_header;
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uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_edge1_header;
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uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_count0_header;
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uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_count1_header;
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uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_logic0_header;
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uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
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uint32_t trig_logic1_header;
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uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
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uint32_t end_sync;
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};
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SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
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const char *name);
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SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
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SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
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SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
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#endif
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