gonna slep
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e00b4f0b10
commit
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12
src/main.rs
12
src/main.rs
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@ -395,6 +395,8 @@ fn parse_instruction(mut bytes: &[u16]) -> (Instruction, usize) {
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consumed += 1;
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//println!("{:016b}", aw);
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// this shiftright shouldn't be needed... but it is.
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aw >>= 4;
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for i in 0..register_count {
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registers.insert(0_usize, Register::into_register(aw & 0b1111));
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@ -513,13 +515,13 @@ impl Machine {
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let arg0 = ci.args[0].as_immediate();
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self.write(ci.args[1], arg0);
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self.RSTAT.set(Flags::FZERO, arg0 == 0);
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//eprintln!("copying {} to {:?}", arg0, ci.args[1]);
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log::info!("copying {} to {:?}", arg0, ci.args[1]);
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}
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OP::CMP => {
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let a = self.read(ci.args[0]);
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let b = self.read(ci.args[1]);
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log::debug!("CMP({}, {})", a, b);
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log::info!("CMP({}, {})", a, b);
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self.RSTAT.set(Flags::FZERO, a == 0 || b == 0);
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self.RSTAT.set(Flags::FEQUL, a == b);
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@ -547,7 +549,7 @@ impl Machine {
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let mut val = self.read(ci.args[0]);
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val = val.wrapping_add(1);
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self.write(ci.args[0], val);
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log::debug!("INC({:?}) to {}", ci.args[0], val);
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log::info!("INC({:?}) to {}", ci.args[0], val);
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self.RSTAT.set(Flags::FZERO, val == 0);
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}
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OP::READ => {
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@ -647,7 +649,7 @@ impl Machine {
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self.write(ci.args[0], val);
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self.RSTAT.set(Flags::FZERO, val == 0);
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}
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_ => { eprintln!("unsupported opcode {:?}, continuing", oc); return false; }
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_ => { eprintln!("unsupported opcode {:?}", oc); return false; }
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}
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if should_inc_ip {
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@ -683,7 +685,7 @@ fn main() {
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let mut m = Machine::default();
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m.SIN[1..=sin.inner().len()].copy_from_slice(sin.inner());
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m.SCODE[1..=code.inner().len()].copy_from_slice(code.inner());
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m.input = b"\x09\x0f\xcc\xcc\xcc\xcc\x0c\x0c\x00\x00\x00\x0a".to_vec();
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m.input = b"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x0a".to_vec();
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// dump_instructions(&m.SCODE[1..=code.inner().len()]);
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