more implementations, still doesn't work.
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parent
89baa2dd3b
commit
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30
src/main.rs
30
src/main.rs
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@ -1,6 +1,7 @@
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use byteorder::{ReadBytesExt, LE};
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use std::io::Cursor;
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use std::convert::{TryInto, TryFrom};
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use std::io::Read;
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struct Machine {
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RX: u16,
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@ -522,20 +523,32 @@ impl Machine {
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}
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OP::JEQU => {
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if self.RSTAT.contains(Flags::FEQUL) {
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if self.RTRGT == 0 {
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return false;
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}
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self.IP = self.RTRGT;
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should_inc_ip = false;
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}
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}
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OP::JUMP => {
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if self.RTRGT == 0 {
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return false;
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}
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self.IP = self.RTRGT;
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should_inc_ip = false;
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}
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OP::INC => {
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let mut val = self.read(ci.args[0]);
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val += 1;
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val = val.wrapping_add(1);
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self.write(ci.args[0], val);
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self.RSTAT.set(Flags::FZERO, val == 0);
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}
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OP::READ => {
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let input = 0;
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std::io::stdin().read(&mut [input]).unwrap();
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self.write(ci.args[0], input);
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self.write(ci.args[0], input as u16);
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self.RSTAT.set(Flags::FZERO, input == 0);
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}
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OP::CPY => {
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@ -558,6 +571,19 @@ impl Machine {
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self.push_stack(self.RTRGT);
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self.RTRGT = 0;
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}
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OP::RCPT => {
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let by: i32 = if ci.def.sign() == 1 {
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self.RTRGT as i32
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} else {
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-(self.RTRGT as i32)
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};
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let from = self.read(ci.args[0]);
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let to = ci.args[1].offset(by);
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self.write(to, from);
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self.RSTAT.set(Flags::FZERO, from == 0);
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}
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OP::RCPF => {
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let by: i32 = if ci.def.sign() == 1 {
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self.RTRGT as i32
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