kicad/pcbnew/collectors.cpp

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
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*
* Copyright (C) 2007-2008 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
* Copyright (C) 2004-2018 KiCad Developers, see AUTHORS.txt for contributors.
*
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* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
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* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
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* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <collectors.h>
#include <class_board_item.h> // class BOARD_ITEM
#include <class_module.h>
#include <fp_shape.h>
#include <class_pad.h>
#include <class_track.h>
#include <class_marker_pcb.h>
#include <class_zone.h>
#include <pcb_shape.h>
#include <class_pcb_group.h>
#include <macros.h>
#include <math/util.h> // for KiROUND
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/* This module contains out of line member functions for classes given in
* collectors.h. Those classes augment the functionality of class PCB_EDIT_FRAME.
*/
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const KICAD_T GENERAL_COLLECTOR::AllBoardItems[] = {
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// there are some restrictions on the order of items in the general case.
// all items in m_Drawings for instance should be contiguous.
// *** all items in a same list (shown here) must be contiguous ****
PCB_MARKER_T, // in m_markers
PCB_TEXT_T, // in m_drawings
PCB_SHAPE_T, // in m_drawings
PCB_DIM_ALIGNED_T, // in m_drawings
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PCB_DIM_CENTER_T, // in m_drawings
PCB_DIM_ORTHOGONAL_T, // in m_drawings
PCB_DIM_LEADER_T, // in m_drawings
PCB_TARGET_T, // in m_drawings
PCB_VIA_T, // in m_tracks
PCB_TRACE_T, // in m_tracks
PCB_ARC_T, // in m_tracks
PCB_PAD_T, // in modules
PCB_FP_TEXT_T, // in modules
PCB_MODULE_T, // in m_modules
PCB_GROUP_T, // in m_groups
PCB_ZONE_AREA_T, // in m_zones
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EOT
};
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const KICAD_T GENERAL_COLLECTOR::BoardLevelItems[] = {
PCB_MARKER_T,
PCB_TEXT_T,
PCB_SHAPE_T,
PCB_DIM_ALIGNED_T,
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PCB_DIM_ORTHOGONAL_T,
PCB_DIM_CENTER_T,
PCB_DIM_LEADER_T,
PCB_TARGET_T,
PCB_VIA_T,
PCB_ARC_T,
PCB_TRACE_T,
PCB_MODULE_T,
PCB_GROUP_T,
PCB_ZONE_AREA_T,
EOT
};
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const KICAD_T GENERAL_COLLECTOR::AllButZones[] = {
PCB_MARKER_T,
PCB_TEXT_T,
PCB_SHAPE_T,
PCB_DIM_ALIGNED_T,
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PCB_DIM_ORTHOGONAL_T,
PCB_DIM_CENTER_T,
PCB_DIM_LEADER_T,
PCB_TARGET_T,
PCB_VIA_T,
PCB_TRACE_T,
PCB_ARC_T,
PCB_PAD_T,
PCB_FP_TEXT_T,
PCB_MODULE_T,
PCB_GROUP_T,
PCB_ZONE_AREA_T, // if it is visible on screen, it should be selectable
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EOT
};
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const KICAD_T GENERAL_COLLECTOR::Modules[] = {
PCB_MODULE_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::PadsOrModules[] = {
PCB_PAD_T,
PCB_MODULE_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::PadsOrTracks[] = {
PCB_PAD_T,
PCB_VIA_T,
PCB_TRACE_T,
PCB_ARC_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::ModulesAndTheirItems[] = {
PCB_MODULE_T,
PCB_FP_TEXT_T,
PCB_FP_SHAPE_T,
PCB_PAD_T,
PCB_FP_ZONE_AREA_T,
PCB_GROUP_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::ModuleItems[] = {
PCB_FP_TEXT_T,
PCB_FP_SHAPE_T,
PCB_PAD_T,
PCB_FP_ZONE_AREA_T,
PCB_GROUP_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::Tracks[] = {
PCB_TRACE_T,
PCB_ARC_T,
PCB_VIA_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::LockableItems[] = {
PCB_MODULE_T,
PCB_GROUP_T, // Can a group be locked?
PCB_TRACE_T,
PCB_ARC_T,
PCB_VIA_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::Zones[] = {
PCB_ZONE_AREA_T,
PCB_FP_ZONE_AREA_T,
EOT
};
const KICAD_T GENERAL_COLLECTOR::Dimensions[] = {
PCB_DIM_ALIGNED_T,
PCB_DIM_LEADER_T,
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PCB_DIM_ORTHOGONAL_T,
PCB_DIM_CENTER_T,
EOT
};
SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData )
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{
BOARD_ITEM* item = (BOARD_ITEM*) testItem;
MODULE* module = nullptr;
PCB_GROUP* group = nullptr;
D_PAD* pad = nullptr;
bool pad_through = false;
VIA* via = nullptr;
MARKER_PCB* marker = nullptr;
ZONE_CONTAINER* zone = nullptr;
PCB_SHAPE* shape = nullptr;
#if 0 // debugging
static int breakhere = 0;
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switch( item->Type() )
{
case PCB_PAD_T:
{
MODULE* m = (MODULE*) item->GetParent();
if( m->GetReference() == wxT( "Y2" ) )
{
breakhere++;
}
}
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break;
case PCB_VIA_T:
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breakhere++;
break;
case PCB_TRACE_T:
case PCB_ARC_T:
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breakhere++;
break;
case PCB_TEXT_T:
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breakhere++;
break;
case PCB_SHAPE_T:
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breakhere++;
break;
case PCB_DIM_ALIGNED_T:
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breakhere++;
break;
case PCB_FP_TEXT_T:
{
FP_TEXT* tm = (FP_TEXT*) item;
if( tm->GetText() == wxT( "10uH" ) )
{
breakhere++;
}
}
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break;
case PCB_MODULE_T:
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{
MODULE* m = (MODULE*) item;
if( m->GetReference() == wxT( "C98" ) )
{
breakhere++;
}
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}
break;
case PCB_MARKER_T:
breakhere++;
break;
default:
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breakhere++;
break;
}
#endif
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switch( item->Type() )
{
case PCB_PAD_T:
// there are pad specific visibility controls.
// Criterias to select a pad is:
// for smd pads: the module parent must be seen, and pads on the corresponding
// board side must be seen
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// if pad is a thru hole, then it can be visible when its parent module is not.
// for through pads: pads on Front or Back board sides must be seen
pad = (D_PAD*) item;
if( (pad->GetAttribute() != PAD_ATTRIB_SMD) &&
(pad->GetAttribute() != PAD_ATTRIB_CONN) ) // a hole is present, so multiple layers
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{
// proceed to the common tests below, but without the parent module test,
// by leaving module==NULL, but having pad != null
pad_through = true;
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}
else // smd, so use pads test after module test
{
module = static_cast<MODULE*>( item->GetParent() );
}
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break;
case PCB_VIA_T: // vias are on many layers, so layer test is specific
via = static_cast<VIA*>( item );
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break;
case PCB_TRACE_T:
case PCB_ARC_T:
if( m_Guide->IgnoreTracks() )
goto exit;
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break;
case PCB_FP_ZONE_AREA_T:
module = static_cast<MODULE*>( item->GetParent() );
// Fallthrough to get the zone as well
KI_FALLTHROUGH;
case PCB_ZONE_AREA_T:
zone = static_cast<ZONE_CONTAINER*>( item );
break;
case PCB_TEXT_T:
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break;
case PCB_SHAPE_T:
shape = static_cast<PCB_SHAPE*>( item );
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break;
case PCB_DIM_ALIGNED_T:
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case PCB_DIM_CENTER_T:
case PCB_DIM_ORTHOGONAL_T:
case PCB_DIM_LEADER_T:
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break;
case PCB_TARGET_T:
break;
case PCB_FP_TEXT_T:
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{
FP_TEXT *text = static_cast<FP_TEXT*>( item );
if( m_Guide->IgnoreMTextsMarkedNoShow() && !text->IsVisible() )
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goto exit;
if( m_Guide->IgnoreMTextsOnBack() && IsBackLayer( text->GetLayer() ) )
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goto exit;
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if( m_Guide->IgnoreMTextsOnFront() && IsFrontLayer( text->GetLayer() ) )
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goto exit;
/* The three text types have different criteria: reference
* and value have their own ignore flags; user text instead
* follows their layer visibility. Checking this here is
* simpler than later (when layer visibility is checked for
* other entities) */
switch( text->GetType() )
{
case FP_TEXT::TEXT_is_REFERENCE:
if( m_Guide->IgnoreModulesRefs() )
goto exit;
break;
case FP_TEXT::TEXT_is_VALUE:
if( m_Guide->IgnoreModulesVals() )
goto exit;
break;
case FP_TEXT::TEXT_is_DIVERS:
if( !m_Guide->IsLayerVisible( text->GetLayer() )
&& m_Guide->IgnoreNonVisibleLayers() )
goto exit;
break;
}
// Extract the module since it could be hidden
module = static_cast<MODULE*>( item->GetParent() );
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}
break;
case PCB_FP_SHAPE_T:
shape = static_cast<FP_SHAPE*>( item );
break;
case PCB_MODULE_T:
module = static_cast<MODULE*>( item );
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break;
case PCB_GROUP_T:
group = static_cast<PCB_GROUP*>( item );
break;
case PCB_MARKER_T:
marker = static_cast<MARKER_PCB*>( item );
break;
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default:
break;
}
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// common tests:
if( module ) // true from case PCB_PAD_T, PCB_FP_TEXT_T, or PCB_MODULE_T
{
if( m_Guide->IgnoreModulesOnBack() && (module->GetLayer() == B_Cu) )
goto exit;
if( m_Guide->IgnoreModulesOnFront() && (module->GetLayer() == F_Cu) )
goto exit;
}
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// Pads are not sensitive to the layer visibility controls.
// They all have their own separate visibility controls
// skip them if not visible
if( pad )
{
if( m_Guide->IgnorePads() )
goto exit;
if( ! pad_through )
{
if( m_Guide->IgnorePadsOnFront() && pad->IsOnLayer(F_Cu ) )
goto exit;
if( m_Guide->IgnorePadsOnBack() && pad->IsOnLayer(B_Cu ) )
goto exit;
}
}
if( marker )
{
// Markers are not sensitive to the layer
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if( marker->HitTest( m_refPos ) )
Append( item );
goto exit;
}
if( group )
{
// Groups are not sensitive to the layer ... ?
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if( group->HitTest( m_refPos ) )
Append( item );
goto exit;
}
if( via )
{
auto type = via->GetViaType();
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if( ( m_Guide->IgnoreThroughVias() && type == VIATYPE::THROUGH )
|| ( m_Guide->IgnoreBlindBuriedVias() && type == VIATYPE::BLIND_BURIED )
|| ( m_Guide->IgnoreMicroVias() && type == VIATYPE::MICROVIA ) )
{
goto exit;
}
}
if( item->IsOnLayer( m_Guide->GetPreferredLayer() ) || m_Guide->IgnorePreferredLayer() )
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{
PCB_LAYER_ID layer = item->GetLayer();
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// Modules and their subcomponents: reference, value and pads are not sensitive
// to the layer visibility controls. They all have their own separate visibility
// controls for vias, GetLayer() has no meaning, but IsOnLayer() works fine. User
// text in module *is* sensitive to layer visibility but that was already handled.
if( via || module || pad || m_Guide->IsLayerVisible( layer )
|| !m_Guide->IgnoreNonVisibleLayers() )
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{
if( !m_Guide->IsLayerLocked( layer ) || !m_Guide->IgnoreLockedLayers() )
{
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if( !item->IsLocked() || !m_Guide->IgnoreLockedItems() )
{
int accuracy = KiROUND( 5 * m_Guide->OnePixelInIU() );
if( zone )
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{
bool testFill = !m_Guide->IgnoreZoneFills();
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if( zone->HitTestForCorner( m_refPos, accuracy * 2 )
|| zone->HitTestForEdge( m_refPos, accuracy )
|| ( testFill && zone->HitTestFilledArea( layer, m_refPos ) ) )
{
Append( item );
goto exit;
}
}
else if( item->Type() == PCB_MODULE_T )
{
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if( module->HitTest( m_refPos, accuracy )
&& module->HitTestAccurate( m_refPos, accuracy ) )
{
Append( item );
goto exit;
}
}
else if( shape )
{
if( shape->HitTest( m_refPos, accuracy ) )
{
Append( item );
goto exit;
}
}
else
{
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if( item->HitTest( m_refPos, 0 ) )
{
Append( item );
goto exit;
}
}
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}
}
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}
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}
if( m_Guide->IncludeSecondary() )
{
// for now, "secondary" means "tolerate any layer". It has
// no effect on other criteria, since there is a separate "ignore" control for
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// those in the COLLECTORS_GUIDE
PCB_LAYER_ID layer = item->GetLayer();
// Modules and their subcomponents: reference, value and pads are not sensitive
// to the layer visibility controls. They all have their own separate visibility
// controls for vias, GetLayer() has no meaning, but IsOnLayer() works fine. User
// text in module *is* sensitive to layer visibility but that was already handled.
if( via || module || pad || zone || m_Guide->IsLayerVisible( layer )
|| !m_Guide->IgnoreNonVisibleLayers() )
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{
if( !m_Guide->IsLayerLocked( layer ) || !m_Guide->IgnoreLockedLayers() )
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{
if( !item->IsLocked() || !m_Guide->IgnoreLockedItems() )
{
int accuracy = KiROUND( 5 * m_Guide->OnePixelInIU() );
if( zone )
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{
bool testFill = !m_Guide->IgnoreZoneFills();
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if( zone->HitTestForCorner( m_refPos, accuracy * 2 )
|| zone->HitTestForEdge( m_refPos, accuracy )
|| ( testFill && zone->HitTestFilledArea( layer, m_refPos ) ) )
{
Append2nd( item );
goto exit;
}
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}
else if( item->Type() == PCB_MODULE_T )
{
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if( module->HitTest( m_refPos, accuracy )
&& module->HitTestAccurate( m_refPos, accuracy ) )
{
Append( item );
goto exit;
}
}
else if( shape )
{
if( shape->HitTest( m_refPos, accuracy ) )
{
Append( item );
goto exit;
}
}
else
{
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if( item->HitTest( m_refPos, 0 ) )
{
Append( item );
goto exit;
}
}
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}
}
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}
}
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exit:
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return SEARCH_RESULT::CONTINUE; // always when collecting
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}
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void GENERAL_COLLECTOR::Collect( BOARD_ITEM* aItem, const KICAD_T aScanList[],
const wxPoint& aRefPos, const COLLECTORS_GUIDE& aGuide )
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{
Empty(); // empty the collection, primary criteria list
Empty2nd(); // empty the collection, secondary criteria list
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// remember guide, pass it to Inspect()
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SetGuide( &aGuide );
SetScanTypes( aScanList );
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// remember where the snapshot was taken from and pass refPos to
// the Inspect() function.
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SetRefPos( aRefPos );
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aItem->Visit( m_inspector, NULL, m_scanTypes );
// record the length of the primary list before concatenating on to it.
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m_PrimaryLength = m_list.size();
// append 2nd list onto end of the first list
for( unsigned i = 0; i<m_List2nd.size(); ++i )
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Append( m_List2nd[i] );
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Empty2nd();
}
SEARCH_RESULT PCB_TYPE_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData )
{
// The Visit() function only visits the testItem if its type was in the
// the scanList, so therefore we can collect anything given to us here.
Append( testItem );
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return SEARCH_RESULT::CONTINUE; // always when collecting
}
void PCB_TYPE_COLLECTOR::Collect( BOARD_ITEM* aBoard, const KICAD_T aScanList[] )
{
Empty(); // empty any existing collection
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aBoard->Visit( m_inspector, NULL, aScanList );
}
SEARCH_RESULT PCB_LAYER_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData )
{
BOARD_ITEM* item = (BOARD_ITEM*) testItem;
if( item->IsOnLayer( m_layer_id ) )
Append( testItem );
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return SEARCH_RESULT::CONTINUE;
}
void PCB_LAYER_COLLECTOR::Collect( BOARD_ITEM* aBoard, const KICAD_T aScanList[] )
{
Empty();
aBoard->Visit( m_inspector, NULL, aScanList );
}