20 lines
601 B
Plaintext
20 lines
601 B
Plaintext
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* PWM model analog in and out
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* Input: 0 - 1 V
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* Output: Vlo, Vhi
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* Frequency: freq
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.subckt pwm out+ out- in+ in- params: freq = 100k vlo=0.7 vhi=3.5
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* the pwm (analog in, digital out)
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a5 %vd (in+ in-) dout pwm_osc
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.model pwm_osc d_pwm(cntl_array = [0 0.01 0.99 1]
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+ dc_array = [0.01 0.01 0.99 0.99]
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+ frequency = {freq} init_phase = 90.0
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+ rise_delay = 2e-9 fall_delay=2e-9)
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* the D to A converter
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abridge1 [dout] %vd[out+ out-] dac1
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.model dac1 dac_bridge(out_low = {vlo} out_high = {vhi} out_undef = {oundef}
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+ input_load = 5.0e-12 t_rise = 2e-9
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+ t_fall = 2e-9)
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.param oundef={(vhi-vlo)/2}
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.ends
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