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kicad/demos/pic_programmer/pic_programmer.kicad_pcb

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Update demo
2018-01-10 15:41:40 +00:00
(kicad_pcb (version 20171130) (host pcbnew "(2018-01-10 revision 87045ea)-master")
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(general
(thickness 1.6)
(drawings 24)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(tracks 372)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(zones 0)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(modules 63)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(nets 118)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(page A4)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(title_block
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(title "SERIAL PIC PROGRAMMER")
)
(layers
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(0 Composant signal)
(31 Cuivre signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(setup
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(last_trace_width 0.5)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(user_trace_width 0.4)
(user_trace_width 0.5)
(trace_clearance 0.25)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.254)
(segment_width 0.381)
(edge_width 0.381)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(via_size 1.6)
(via_drill 0.6)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(via_min_size 0.889)
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
(uvia_min_drill 0.127)
(pcb_text_width 0.3048)
(pcb_text_size 1.524 2.032)
(mod_edge_width 0.381)
(mod_text_size 1.524 1.524)
(mod_text_width 0.3048)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad_size 1.6 1.6)
(pad_drill 0.8)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(pad_to_mask_clearance 0.1)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(aux_axis_origin 62.23 153.67)
(visible_elements 7FFFFFFF)
(pcbplotparams
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(layerselection 0x00030_80000001)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(usegerberextensions true)
Update demos
2017-11-21 20:26:06 +00:00
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(excludeedgelayer true)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(linewidth 0.150000)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(net 1 /CTS)
(net 2 /DTR)
(net 3 /PC-CLOCK-OUT)
(net 4 /TXD)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(net 5 GND)
(net 6 "Net-(C2-Pad1)")
(net 7 "Net-(C4-Pad1)")
(net 8 "Net-(C5-Pad1)")
(net 9 "Net-(C9-Pad2)")
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(net 10 "Net-(D11-Pad1)")
(net 11 "Net-(D11-Pad2)")
(net 12 "Net-(Q1-Pad2)")
(net 13 "Net-(Q2-Pad3)")
(net 14 "Net-(Q3-Pad2)")
(net 15 "Net-(R12-Pad1)")
(net 16 "Net-(R13-Pad1)")
(net 17 "Net-(R15-Pad1)")
(net 18 "Net-(R16-Pad1)")
(net 19 "Net-(R8-Pad1)")
(net 20 "Net-(RV1-Pad2)")
(net 21 VCC)
(net 22 VPP)
(net 23 /pic_sockets/VCC_PIC)
(net 24 "Net-(D1-Pad2)")
(net 25 "Net-(D4-Pad2)")
(net 26 "Net-(D8-Pad2)")
(net 27 "Net-(D9-Pad2)")
(net 28 "Net-(D12-Pad2)")
Update demos
2017-11-21 20:26:06 +00:00
(net 29 /VPP/MCLR)
(net 30 /CLOCK-RB6)
(net 31 /DATA-RB7)
(net 32 "Net-(D2-Pad2)")
(net 33 "Net-(D6-Pad2)")
(net 34 "Net-(D10-Pad2)")
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 35 "Net-(P3-Pad2)")
(net 36 "Net-(P3-Pad3)")
(net 37 "Net-(P3-Pad4)")
(net 38 "Net-(P3-Pad5)")
(net 39 "Net-(P3-Pad6)")
(net 40 "Net-(P3-Pad7)")
(net 41 "Net-(P3-Pad9)")
(net 42 "Net-(P3-Pad10)")
(net 43 "Net-(P3-Pad13)")
(net 44 "Net-(P3-Pad14)")
(net 45 "Net-(P3-Pad15)")
(net 46 "Net-(P3-Pad16)")
(net 47 "Net-(P3-Pad17)")
(net 48 "Net-(P3-Pad18)")
(net 49 "Net-(P3-Pad19)")
(net 50 "Net-(P3-Pad20)")
(net 51 "Net-(P3-Pad21)")
(net 52 "Net-(P3-Pad22)")
(net 53 "Net-(P3-Pad23)")
(net 54 "Net-(P3-Pad24)")
(net 55 "Net-(P3-Pad25)")
(net 56 "Net-(P3-Pad26)")
(net 57 "Net-(P3-Pad27)")
(net 58 "Net-(P3-Pad28)")
(net 59 "Net-(P3-Pad29)")
(net 60 "Net-(P3-Pad30)")
(net 61 "Net-(P3-Pad33)")
(net 62 "Net-(P3-Pad34)")
(net 63 "Net-(P3-Pad35)")
(net 64 "Net-(P3-Pad36)")
(net 65 "Net-(P3-Pad37)")
(net 66 "Net-(P3-Pad38)")
(net 67 "Net-(P104-Pad1)")
(net 68 "Net-(P103-Pad1)")
(net 69 "Net-(P102-Pad1)")
(net 70 "Net-(P101-Pad1)")
(net 71 "Net-(P106-Pad1)")
(net 72 "Net-(P105-Pad1)")
(net 73 "Net-(J1-Pad1)")
(net 74 "Net-(J1-Pad2)")
(net 75 "Net-(J1-Pad6)")
(net 76 "Net-(J1-Pad9)")
(net 77 "Net-(U6-Pad5)")
(net 78 "Net-(U6-Pad2)")
(net 79 "Net-(U6-Pad3)")
(net 80 "Net-(U1-Pad7)")
(net 81 "Net-(U4-Pad3)")
(net 82 "Net-(U4-Pad4)")
(net 83 "Net-(P2-Pad15)")
(net 84 "Net-(P2-Pad2)")
(net 85 "Net-(P2-Pad16)")
(net 86 "Net-(P2-Pad3)")
(net 87 "Net-(P2-Pad17)")
(net 88 "Net-(P2-Pad4)")
(net 89 "Net-(P2-Pad18)")
(net 90 "Net-(P2-Pad5)")
(net 91 "Net-(P2-Pad6)")
(net 92 "Net-(P2-Pad7)")
(net 93 "Net-(P2-Pad21)")
(net 94 "Net-(P2-Pad22)")
(net 95 "Net-(P2-Pad9)")
(net 96 "Net-(P2-Pad23)")
(net 97 "Net-(P2-Pad10)")
(net 98 "Net-(P2-Pad24)")
(net 99 "Net-(P2-Pad11)")
(net 100 "Net-(P2-Pad25)")
(net 101 "Net-(P2-Pad12)")
(net 102 "Net-(P2-Pad26)")
(net 103 "Net-(P2-Pad13)")
(net 104 "Net-(P2-Pad14)")
(net 105 "Net-(U5-Pad1)")
(net 106 "Net-(U5-Pad10)")
(net 107 "Net-(U5-Pad2)")
(net 108 "Net-(U5-Pad11)")
(net 109 "Net-(U5-Pad3)")
(net 110 "Net-(U5-Pad6)")
(net 111 "Net-(U5-Pad15)")
(net 112 "Net-(U5-Pad7)")
(net 113 "Net-(U5-Pad16)")
(net 114 "Net-(U5-Pad8)")
(net 115 "Net-(U5-Pad17)")
(net 116 "Net-(U5-Pad9)")
(net 117 "Net-(U5-Pad18)")
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(net_class Default "Ceci est la Netclass par défaut"
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(clearance 0.25)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(trace_width 0.5)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(via_dia 1.6)
(via_drill 0.6)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(uvia_dia 0.508)
(uvia_drill 0.127)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(add_net /CLOCK-RB6)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(add_net /CTS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(add_net /DATA-RB7)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(add_net /DTR)
(add_net /PC-CLOCK-OUT)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(add_net /TXD)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(add_net /VPP/MCLR)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(add_net /pic_sockets/VCC_PIC)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(add_net "Net-(C2-Pad1)")
(add_net "Net-(C4-Pad1)")
(add_net "Net-(C5-Pad1)")
(add_net "Net-(C9-Pad2)")
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(add_net "Net-(D1-Pad2)")
(add_net "Net-(D10-Pad2)")
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(add_net "Net-(D11-Pad1)")
(add_net "Net-(D11-Pad2)")
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(add_net "Net-(D12-Pad2)")
(add_net "Net-(D2-Pad2)")
(add_net "Net-(D4-Pad2)")
(add_net "Net-(D6-Pad2)")
(add_net "Net-(D8-Pad2)")
(add_net "Net-(D9-Pad2)")
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(add_net "Net-(J1-Pad1)")
(add_net "Net-(J1-Pad2)")
(add_net "Net-(J1-Pad6)")
(add_net "Net-(J1-Pad9)")
(add_net "Net-(P101-Pad1)")
(add_net "Net-(P102-Pad1)")
(add_net "Net-(P103-Pad1)")
(add_net "Net-(P104-Pad1)")
(add_net "Net-(P105-Pad1)")
(add_net "Net-(P106-Pad1)")
(add_net "Net-(P2-Pad10)")
(add_net "Net-(P2-Pad11)")
(add_net "Net-(P2-Pad12)")
(add_net "Net-(P2-Pad13)")
(add_net "Net-(P2-Pad14)")
(add_net "Net-(P2-Pad15)")
(add_net "Net-(P2-Pad16)")
(add_net "Net-(P2-Pad17)")
(add_net "Net-(P2-Pad18)")
(add_net "Net-(P2-Pad2)")
(add_net "Net-(P2-Pad21)")
(add_net "Net-(P2-Pad22)")
(add_net "Net-(P2-Pad23)")
(add_net "Net-(P2-Pad24)")
(add_net "Net-(P2-Pad25)")
(add_net "Net-(P2-Pad26)")
(add_net "Net-(P2-Pad3)")
(add_net "Net-(P2-Pad4)")
(add_net "Net-(P2-Pad5)")
(add_net "Net-(P2-Pad6)")
(add_net "Net-(P2-Pad7)")
(add_net "Net-(P2-Pad9)")
(add_net "Net-(P3-Pad10)")
(add_net "Net-(P3-Pad13)")
(add_net "Net-(P3-Pad14)")
(add_net "Net-(P3-Pad15)")
(add_net "Net-(P3-Pad16)")
(add_net "Net-(P3-Pad17)")
(add_net "Net-(P3-Pad18)")
(add_net "Net-(P3-Pad19)")
(add_net "Net-(P3-Pad2)")
(add_net "Net-(P3-Pad20)")
(add_net "Net-(P3-Pad21)")
(add_net "Net-(P3-Pad22)")
(add_net "Net-(P3-Pad23)")
(add_net "Net-(P3-Pad24)")
(add_net "Net-(P3-Pad25)")
(add_net "Net-(P3-Pad26)")
(add_net "Net-(P3-Pad27)")
(add_net "Net-(P3-Pad28)")
(add_net "Net-(P3-Pad29)")
(add_net "Net-(P3-Pad3)")
(add_net "Net-(P3-Pad30)")
(add_net "Net-(P3-Pad33)")
(add_net "Net-(P3-Pad34)")
(add_net "Net-(P3-Pad35)")
(add_net "Net-(P3-Pad36)")
(add_net "Net-(P3-Pad37)")
(add_net "Net-(P3-Pad38)")
(add_net "Net-(P3-Pad4)")
(add_net "Net-(P3-Pad5)")
(add_net "Net-(P3-Pad6)")
(add_net "Net-(P3-Pad7)")
(add_net "Net-(P3-Pad9)")
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(add_net "Net-(Q1-Pad2)")
(add_net "Net-(Q2-Pad3)")
(add_net "Net-(Q3-Pad2)")
(add_net "Net-(R12-Pad1)")
(add_net "Net-(R13-Pad1)")
(add_net "Net-(R15-Pad1)")
(add_net "Net-(R16-Pad1)")
(add_net "Net-(R8-Pad1)")
(add_net "Net-(RV1-Pad2)")
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(add_net "Net-(U1-Pad7)")
(add_net "Net-(U4-Pad3)")
(add_net "Net-(U4-Pad4)")
(add_net "Net-(U5-Pad1)")
(add_net "Net-(U5-Pad10)")
(add_net "Net-(U5-Pad11)")
(add_net "Net-(U5-Pad15)")
(add_net "Net-(U5-Pad16)")
(add_net "Net-(U5-Pad17)")
(add_net "Net-(U5-Pad18)")
(add_net "Net-(U5-Pad2)")
(add_net "Net-(U5-Pad3)")
(add_net "Net-(U5-Pad6)")
(add_net "Net-(U5-Pad7)")
(add_net "Net-(U5-Pad8)")
(add_net "Net-(U5-Pad9)")
(add_net "Net-(U6-Pad2)")
(add_net "Net-(U6-Pad3)")
(add_net "Net-(U6-Pad5)")
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(add_net VPP)
)
(net_class POWER ""
(clearance 0.28)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(trace_width 0.8)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(via_dia 1.6)
(via_drill 0.6)
(uvia_dia 0.508)
(uvia_drill 0.127)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(add_net GND)
(add_net VCC)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AD83)
(at 135.255 121.92 90)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4D85)
(fp_text reference R12 (at 5.08 -2.31 90) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 470 (at 5.08 2.31 90) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 /DATA-RB7))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(R12-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AD6D)
(at 139.065 91.059)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4D92)
(fp_text reference R8 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 1K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 "Net-(Q1-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(R8-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AD57)
(at 140.335 111.76 270)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4D8D)
(fp_text reference R13 (at 5.08 -2.31 270) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 470 (at 5.08 2.31 270) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 270) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 /CLOCK-RB6))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(R13-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
update demo
2017-11-30 15:42:00 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AD41)
(at 139.065 87.63)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A5083)
(fp_text reference R14 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 470 (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(D9-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 VCC))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AD2B)
(at 118.11 78.74)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A58D7)
(fp_text reference R15 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 6.2K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(R15-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AD15)
(at 118.11 75.184)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A58DC)
(fp_text reference R16 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 62K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 22 VPP))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(R16-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22ACFF)
(at 156.21 68.58 90)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A50BF)
(fp_text reference R17 (at 5.08 -2.31 90) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 22K (at 5.08 2.31 90) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(Q2-Pad3)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(scale (xyz 1 1 1))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22ACE9)
(at 149.225 83.82 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4639B9B0)
(fp_text reference R19 (at 5.08 -2.31 180) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 2.2K (at 5.08 2.31 180) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(Q3-Pad2)"))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(D11-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22ACD3)
(at 144.78 102.235 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4639B9B3)
(fp_text reference R20 (at 5.08 -2.31 180) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 2.2K (at 5.08 2.31 180) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(Q3-Pad2)"))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 VCC))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22ACBD)
(at 158.115 102.235 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4639B9E9)
(fp_text reference R21 (at 5.08 -2.31 180) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 470 (at 5.08 2.31 180) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 28 "Net-(D12-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22ACA7)
(at 87.757 121.92)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4D63)
(fp_text reference R6 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 /PC-CLOCK-OUT))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AC91)
(at 139.7 54.61)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4F2A)
(fp_text reference R7 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(C9-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 VPP))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AC7B)
(at 87.757 125.476)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4D62)
(fp_text reference R5 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 "Net-(D6-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 /PC-CLOCK-OUT))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AC65)
(at 87.63 107.823)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4D5B)
(fp_text reference R4 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 /DTR))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AC4F)
(at 87.63 111.125)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4D5A)
(fp_text reference R3 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(D4-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 /DTR))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Update demo
2018-01-10 15:41:40 +00:00
(rotate (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AC39)
(at 87.63 114.554)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4CFB)
(fp_text reference R2 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 /TXD))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(scale (xyz 1 1 1))
Update demo
2018-01-10 15:41:40 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AC23)
(at 87.63 118.11)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4CF4)
(fp_text reference R1 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(D2-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 /TXD))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(scale (xyz 1 1 1))
Update demo
2018-01-10 15:41:40 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22AC0D)
(at 139.065 77.47)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A4F52)
(fp_text reference R9 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 2.2K (at 5.08 2.31) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(D8-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(Q2-Pad3)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22ABF7)
(at 114.3 48.26)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /442A5F83)
(fp_text reference R10 (at 5.08 -2.31) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 5,1K (at 5.08 2.31) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(C5-Pad1)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(C4-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A22ABE1)
(at 152.4 68.58 90)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
Update demo
2018-01-10 15:41:40 +00:00
(path /44369638)
(fp_text reference R18 (at 5.08 -2.31 90) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 220 (at 5.08 2.31 90) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo
2018-01-10 15:41:40 +00:00
(net 29 /VPP/MCLR))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(Q2-Pad3)"))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Composant) (tedit 5A14249F) (tstamp 5A2A0231)
(at 140.081 70.993 90)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
Update demo
2018-01-10 15:41:40 +00:00
(path /442A4F23)
(fp_text reference R11 (at 5.08 -2.31 90) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 22K (at 5.08 2.31 90) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 5.08 0 90) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 10.16 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(C9-Pad2)"))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(D11-Pad1)"))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:40tex-Ell600 (layer Composant) (tedit 5A29799A) (tstamp 541E1940)
(at 182.88 74.93 270)
(descr "Support TEXTOOL Dil 40 pins, pads elliptiques, e=600 mils")
(tags DEV)
(path /4804A5E2/442A88ED)
(fp_text reference P3 (at -3.81 -3.175 270) (layer F.SilkS)
(effects (font (size 2.032 1.27) (thickness 0.3048)))
)
(fp_text value SUPP40 (at -5.715 1.905 270) (layer F.SilkS)
(effects (font (size 2.032 1.27) (thickness 0.3048)))
)
(fp_line (start -50 8) (end -35 8) (layer F.CrtYd) (width 0.15))
(fp_line (start -50 13.5) (end -50 8) (layer F.CrtYd) (width 0.15))
(fp_line (start -35 13.5) (end -50 13.5) (layer F.CrtYd) (width 0.15))
(fp_line (start -35 12) (end -35 13.5) (layer F.CrtYd) (width 0.15))
(fp_line (start 18.5 12) (end -35 12) (layer F.CrtYd) (width 0.15))
(fp_line (start 18.5 17) (end 18.5 12) (layer F.CrtYd) (width 0.15))
(fp_line (start 24.5 17) (end 18.5 17) (layer F.CrtYd) (width 0.15))
(fp_line (start 24.5 12) (end 24.5 17) (layer F.CrtYd) (width 0.15))
(fp_line (start 32.5 12) (end 24.5 12) (layer F.CrtYd) (width 0.15))
(fp_line (start 32.5 -12) (end 32.5 12) (layer F.CrtYd) (width 0.15))
(fp_line (start -23.5 -12) (end 32.5 -12) (layer F.CrtYd) (width 0.15))
(fp_line (start -23.5 -17) (end -23.5 -12) (layer F.CrtYd) (width 0.15))
(fp_line (start -30 -17) (end -23.5 -17) (layer F.CrtYd) (width 0.15))
(fp_line (start -30 -12) (end -30 -17) (layer F.CrtYd) (width 0.15))
(fp_line (start -35 -12) (end -30 -12) (layer F.CrtYd) (width 0.15))
(fp_line (start -35 8) (end -35 -12) (layer F.CrtYd) (width 0.15))
(fp_line (start -34.29 -10.16) (end -33.02 -11.43) (layer F.SilkS) (width 0.381))
(fp_line (start -34.29 10.16) (end -34.29 -10.16) (layer F.SilkS) (width 0.381))
(fp_line (start -33.02 11.43) (end -34.29 10.16) (layer F.SilkS) (width 0.381))
(fp_line (start 30.48 11.43) (end -33.02 11.43) (layer F.SilkS) (width 0.381))
(fp_line (start 31.75 10.16) (end 30.48 11.43) (layer F.SilkS) (width 0.381))
(fp_line (start 31.75 -10.16) (end 31.75 10.16) (layer F.SilkS) (width 0.381))
(fp_line (start 30.48 -11.43) (end 31.75 -10.16) (layer F.SilkS) (width 0.381))
(fp_line (start -33.02 -11.43) (end 30.48 -11.43) (layer F.SilkS) (width 0.381))
(fp_line (start -46.99 8.89) (end -48.26 10.16) (layer F.SilkS) (width 0.381))
(fp_line (start -40.64 8.89) (end -46.99 8.89) (layer F.SilkS) (width 0.381))
(fp_line (start -39.37 10.16) (end -40.64 8.89) (layer F.SilkS) (width 0.381))
(fp_line (start -39.37 11.43) (end -33.02 11.43) (layer F.SilkS) (width 0.381))
(fp_line (start -39.37 10.16) (end -29.21 10.16) (layer F.SilkS) (width 0.381))
(fp_line (start -39.37 11.43) (end -39.37 10.16) (layer F.SilkS) (width 0.381))
(fp_line (start -40.64 12.7) (end -39.37 11.43) (layer F.SilkS) (width 0.381))
(fp_line (start -46.99 12.7) (end -40.64 12.7) (layer F.SilkS) (width 0.381))
(fp_line (start -48.26 11.43) (end -46.99 12.7) (layer F.SilkS) (width 0.381))
(fp_line (start -48.26 10.16) (end -48.26 11.43) (layer F.SilkS) (width 0.381))
(fp_line (start -29.21 10.16) (end -29.21 11.43) (layer F.SilkS) (width 0.381))
(fp_line (start 19.05 15.24) (end 19.05 11.43) (layer F.SilkS) (width 0.381))
(fp_line (start 20.32 16.51) (end 19.05 15.24) (layer F.SilkS) (width 0.381))
(fp_line (start 22.86 16.51) (end 20.32 16.51) (layer F.SilkS) (width 0.381))
(fp_line (start 24.13 15.24) (end 22.86 16.51) (layer F.SilkS) (width 0.381))
(fp_line (start 24.13 11.43) (end 24.13 15.24) (layer F.SilkS) (width 0.381))
(fp_line (start -29.21 -15.24) (end -29.21 -11.43) (layer F.SilkS) (width 0.381))
(fp_line (start -27.94 -16.51) (end -29.21 -15.24) (layer F.SilkS) (width 0.381))
(fp_line (start -25.4 -16.51) (end -27.94 -16.51) (layer F.SilkS) (width 0.381))
(fp_line (start -24.13 -15.24) (end -25.4 -16.51) (layer F.SilkS) (width 0.381))
(fp_line (start -24.13 -11.43) (end -24.13 -15.24) (layer F.SilkS) (width 0.381))
(fp_line (start -29.21 5.08) (end -29.21 -5.08) (layer F.SilkS) (width 0.381))
(fp_line (start 26.67 5.08) (end -29.21 5.08) (layer F.SilkS) (width 0.381))
(fp_line (start 26.67 -5.08) (end 26.67 5.08) (layer F.SilkS) (width 0.381))
(fp_line (start -29.21 -5.08) (end 26.67 -5.08) (layer F.SilkS) (width 0.381))
(pad HOLE thru_hole circle (at 21.59 13.97 270) (size 2.8 2.8) (drill 2) (layers *.Cu *.Mask))
(pad HOLE thru_hole circle (at -26.67 -13.97 270) (size 2.8 2.8) (drill 2) (layers *.Cu *.Mask))
(pad 40 thru_hole rect (at -24.13 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 31 /DATA-RB7))
(pad 39 thru_hole oval (at -21.59 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 30 /CLOCK-RB6))
(pad 38 thru_hole oval (at -19.05 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 66 "Net-(P3-Pad38)"))
(pad 37 thru_hole oval (at -16.51 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 65 "Net-(P3-Pad37)"))
(pad 36 thru_hole oval (at -13.97 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 64 "Net-(P3-Pad36)"))
(pad 35 thru_hole oval (at -11.43 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 63 "Net-(P3-Pad35)"))
(pad 34 thru_hole oval (at -8.89 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 62 "Net-(P3-Pad34)"))
(pad 33 thru_hole oval (at -6.35 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 61 "Net-(P3-Pad33)"))
(pad 32 thru_hole oval (at -3.81 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(pad 31 thru_hole oval (at -1.27 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 5 GND))
(pad 30 thru_hole oval (at 1.27 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 60 "Net-(P3-Pad30)"))
(pad 29 thru_hole oval (at 3.81 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 59 "Net-(P3-Pad29)"))
(pad 28 thru_hole oval (at 6.35 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 58 "Net-(P3-Pad28)"))
(pad 27 thru_hole oval (at 8.89 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 57 "Net-(P3-Pad27)"))
(pad 26 thru_hole oval (at 11.43 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 56 "Net-(P3-Pad26)"))
(pad 25 thru_hole oval (at 13.97 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 55 "Net-(P3-Pad25)"))
(pad 24 thru_hole oval (at 16.51 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 54 "Net-(P3-Pad24)"))
(pad 23 thru_hole oval (at 19.05 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 53 "Net-(P3-Pad23)"))
(pad 22 thru_hole oval (at 21.59 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 52 "Net-(P3-Pad22)"))
(pad 21 thru_hole oval (at 24.13 -7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 51 "Net-(P3-Pad21)"))
(pad 20 thru_hole oval (at 24.13 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 50 "Net-(P3-Pad20)"))
(pad 19 thru_hole oval (at 21.59 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 49 "Net-(P3-Pad19)"))
(pad 18 thru_hole oval (at 19.05 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 48 "Net-(P3-Pad18)"))
(pad 17 thru_hole oval (at 16.51 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 47 "Net-(P3-Pad17)"))
(pad 16 thru_hole oval (at 13.97 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 46 "Net-(P3-Pad16)"))
(pad 15 thru_hole oval (at 11.43 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 45 "Net-(P3-Pad15)"))
(pad 14 thru_hole oval (at 8.89 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 44 "Net-(P3-Pad14)"))
(pad 13 thru_hole oval (at 6.35 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 43 "Net-(P3-Pad13)"))
(pad 12 thru_hole oval (at 3.81 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 5 GND))
(pad 11 thru_hole oval (at 1.27 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(pad 10 thru_hole oval (at -1.27 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 42 "Net-(P3-Pad10)"))
(pad 9 thru_hole oval (at -3.81 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 41 "Net-(P3-Pad9)"))
(pad 8 thru_hole oval (at -6.35 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 5 GND))
(pad 7 thru_hole oval (at -8.89 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 40 "Net-(P3-Pad7)"))
(pad 6 thru_hole oval (at -11.43 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 39 "Net-(P3-Pad6)"))
(pad 5 thru_hole oval (at -13.97 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 38 "Net-(P3-Pad5)"))
(pad 4 thru_hole oval (at -16.51 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 37 "Net-(P3-Pad4)"))
(pad 3 thru_hole oval (at -19.05 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 36 "Net-(P3-Pad3)"))
(pad 2 thru_hole oval (at -21.59 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 35 "Net-(P3-Pad2)"))
(pad 1 thru_hole oval (at -24.13 7.62 270) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask)
(net 29 /VPP/MCLR))
(model Sockets.3dshapes/40tex600.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module footprints:RV2X4 (layer Composant) (tedit 5A295CAE) (tstamp 5A29ABCA)
(at 122.555 88.265 180)
(descr "Resistance variable / Potentiometre")
(tags R)
(path /443D0101)
(fp_text reference RV1 (at -2.54 -5.08 180) (layer F.SilkS)
(effects (font (size 1.397 1.27) (thickness 0.2032)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 1K (at -1.651 5.461 180) (layer F.Fab)
(effects (font (size 1.397 1.27) (thickness 0.2032)))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start -8 4.25) (end -8 -4.25) (layer F.CrtYd) (width 0.15))
(fp_line (start 4.25 4.25) (end -8 4.25) (layer F.CrtYd) (width 0.15))
(fp_line (start 7 1.5) (end 4.25 4.25) (layer F.CrtYd) (width 0.15))
(fp_line (start 7 -1.5) (end 7 1.5) (layer F.CrtYd) (width 0.15))
(fp_line (start 4.25 -4.25) (end 7 -1.5) (layer F.CrtYd) (width 0.15))
(fp_line (start -8 -4.25) (end 4.25 -4.25) (layer F.CrtYd) (width 0.15))
(fp_circle (center 1.27 0) (end -2.54 -0.635) (layer F.SilkS) (width 0.3048))
(fp_line (start -2.54 0.508) (end 4.953 0.508) (layer F.SilkS) (width 0.3048))
(fp_line (start -2.54 -0.508) (end 4.953 -0.508) (layer F.SilkS) (width 0.3048))
(fp_line (start 1.651 3.81) (end 0.762 3.81) (layer F.SilkS) (width 0.3048))
(fp_line (start 0.762 -3.81) (end 1.905 -3.81) (layer F.SilkS) (width 0.3048))
(fp_line (start -7.62 3.81) (end -7.62 -3.81) (layer F.SilkS) (width 0.3048))
(fp_line (start 3.81 3.81) (end -7.62 3.81) (layer F.SilkS) (width 0.3048))
(fp_line (start 6.35 1.27) (end 3.81 3.81) (layer F.SilkS) (width 0.3048))
(fp_line (start 6.35 -1.27) (end 6.35 1.27) (layer F.SilkS) (width 0.3048))
(fp_line (start 3.81 -3.81) (end 6.35 -1.27) (layer F.SilkS) (width 0.3048))
(fp_line (start -7.62 -3.81) (end 3.81 -3.81) (layer F.SilkS) (width 0.3048))
(pad 3 thru_hole circle (at -5.08 2.54 180) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask)
(net 18 "Net-(R16-Pad1)"))
(pad 2 thru_hole circle (at 5.08 0 180) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask)
(net 20 "Net-(RV1-Pad2)"))
(pad 1 thru_hole circle (at -5.08 -2.54 180) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask)
(net 17 "Net-(R15-Pad1)"))
(model Discret.3dshapes/RV2X4.wrl
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:INDUCTOR_V (layer Composant) (tedit 5A2977B9) (tstamp 54032CAE)
(at 125.73 64.77 270)
(descr "Inductor (vertical)")
(tags INDUCTOR)
(path /442A57BE)
(fp_text reference L1 (at 0 1.99898 270) (layer F.Fab)
(effects (font (size 1.00076 1.00076) (thickness 0.2032)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 22uH (at 0.09906 -1.99898 270) (layer F.SilkS)
(effects (font (size 1.00076 1.00076) (thickness 0.2032)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 0 0) (end 4 0.25) (layer F.CrtYd) (width 0.15))
(fp_circle (center 0 0) (end 3.81 0) (layer F.SilkS) (width 0.20066))
(pad 2 thru_hole circle (at 2.54 0 270) (size 1.905 1.905) (drill 0.8128) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 21 VCC))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole rect (at -2.54 0 270) (size 1.905 1.905) (drill 0.8128) (layers *.Cu *.Mask)
(net 34 "Net-(D10-Pad2)"))
(model Inductors.3dshapes/INDUCTOR_V.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 2 2 2))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:1pin-4 (layer Composant) (tedit 5A295BB7) (tstamp 54033021)
(at 229.87 44.45)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /54020DE3)
(fp_text reference P104 (at 0 -3.048) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 0 0) (end 3.5 0) (layer F.CrtYd) (width 0.15))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 67 "Net-(P104-Pad1)") (clearance 2))
)
(module footprints:1pin-4 (layer Composant) (tedit 5A295BB7) (tstamp 54033012)
(at 77.47 135.89)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /54020BEA)
(fp_text reference P101 (at 0 -3.048) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
)
(fp_circle (center 0 0) (end 3.5 0) (layer F.CrtYd) (width 0.15))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 70 "Net-(P101-Pad1)") (clearance 2))
)
(module footprints:1pin-4 (layer Composant) (tedit 5A295BB7) (tstamp 54033017)
(at 158.75 135.89)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /54020DA9)
(fp_text reference P102 (at 0 -3.048) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
)
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 0 0) (end 3.5 0) (layer F.CrtYd) (width 0.15))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 69 "Net-(P102-Pad1)") (clearance 2))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:1pin-4 (layer Composant) (tedit 5A295BB7) (tstamp 5403301C)
(at 229.87 135.89)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /54020DC2)
(fp_text reference P103 (at 0 -3.048) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 0 0) (end 3.5 0) (layer F.CrtYd) (width 0.15))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 68 "Net-(P103-Pad1)") (clearance 2))
)
(module footprints:1pin-4 (layer Composant) (tedit 5A295BB7) (tstamp 54033026)
(at 158.75 44.45)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /54020E5D)
(fp_text reference P105 (at 0 -3.048) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 0 0) (end 3.5 0) (layer F.CrtYd) (width 0.15))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 72 "Net-(P105-Pad1)") (clearance 2))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:1pin-4 (layer Composant) (tedit 5A295BB7) (tstamp 5403302B)
(at 77.47 44.45)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /54020E76)
(fp_text reference P106 (at 0 -3.048) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.254)))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
)
(fp_circle (center 0 0) (end 3.5 0) (layer F.CrtYd) (width 0.15))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 71 "Net-(P106-Pad1)") (clearance 2))
)
(module TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal (layer Composant) (tedit 5A082035) (tstamp 5A29E47A)
(at 78.7 62.3 270)
(descr "Terminal Block Phoenix MKDS-1,5-2, 2 pins, pitch 05mm, size 10.0x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
(tags "THT Terminal Block Phoenix MKDS-1.5-2 pitch 05mm size 10.0x9.8mm^2 drill 1.3mm pad 2.6mm")
(path /442A4FE7)
(fp_text reference P1 (at 2.5 -6.26 270) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value CONN_2 (at 2.5 5.66 270) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 2.5 3.2 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8 -5.75) (end -3 -5.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 8 5.1) (end 8 -5.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3 5.1) (end 8 5.1) (layer F.CrtYd) (width 0.05))
(fp_line (start -3 -5.75) (end -3 5.1) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.8 4.9) (end -2.3 4.9) (layer F.SilkS) (width 0.12))
(fp_line (start -2.8 4.16) (end -2.8 4.9) (layer F.SilkS) (width 0.12))
(fp_line (start 3.773 1.023) (end 3.726 1.069) (layer F.SilkS) (width 0.12))
(fp_line (start 6.07 -1.275) (end 6.035 -1.239) (layer F.SilkS) (width 0.12))
(fp_line (start 3.966 1.239) (end 3.931 1.274) (layer F.SilkS) (width 0.12))
(fp_line (start 6.275 -1.069) (end 6.228 -1.023) (layer F.SilkS) (width 0.12))
(fp_line (start 5.955 -1.138) (end 3.863 0.955) (layer F.Fab) (width 0.1))
(fp_line (start 6.138 -0.955) (end 4.046 1.138) (layer F.Fab) (width 0.1))
(fp_line (start 0.955 -1.138) (end -1.138 0.955) (layer F.Fab) (width 0.1))
(fp_line (start 1.138 -0.955) (end -0.955 1.138) (layer F.Fab) (width 0.1))
(fp_line (start 7.56 -5.261) (end 7.56 4.66) (layer F.SilkS) (width 0.12))
(fp_line (start -2.56 -5.261) (end -2.56 4.66) (layer F.SilkS) (width 0.12))
(fp_line (start -2.56 4.66) (end 7.56 4.66) (layer F.SilkS) (width 0.12))
(fp_line (start -2.56 -5.261) (end 7.56 -5.261) (layer F.SilkS) (width 0.12))
(fp_line (start -2.56 -2.301) (end 7.56 -2.301) (layer F.SilkS) (width 0.12))
(fp_line (start -2.5 -2.3) (end 7.5 -2.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.56 2.6) (end 7.56 2.6) (layer F.SilkS) (width 0.12))
(fp_line (start -2.5 2.6) (end 7.5 2.6) (layer F.Fab) (width 0.1))
(fp_line (start -2.56 4.1) (end 7.56 4.1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.5 4.1) (end 7.5 4.1) (layer F.Fab) (width 0.1))
(fp_line (start -2.5 4.1) (end -2.5 -5.2) (layer F.Fab) (width 0.1))
(fp_line (start -2 4.6) (end -2.5 4.1) (layer F.Fab) (width 0.1))
(fp_line (start 7.5 4.6) (end -2 4.6) (layer F.Fab) (width 0.1))
(fp_line (start 7.5 -5.2) (end 7.5 4.6) (layer F.Fab) (width 0.1))
(fp_line (start -2.5 -5.2) (end 7.5 -5.2) (layer F.Fab) (width 0.1))
(fp_circle (center 5 0) (end 6.68 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 5 0) (end 6.5 0) (layer F.Fab) (width 0.1))
(fp_circle (center 0 0) (end 1.5 0) (layer F.Fab) (width 0.1))
(fp_arc (start 0 0) (end -0.684 1.535) (angle -25) (layer F.SilkS) (width 0.12))
(fp_arc (start 0 0) (end -1.535 -0.684) (angle -48) (layer F.SilkS) (width 0.12))
(fp_arc (start 0 0) (end 0.684 -1.535) (angle -48) (layer F.SilkS) (width 0.12))
(fp_arc (start 0 0) (end 1.535 0.684) (angle -48) (layer F.SilkS) (width 0.12))
(fp_arc (start 0 0) (end 0 1.68) (angle -24) (layer F.SilkS) (width 0.12))
(pad 2 thru_hole circle (at 5 0 270) (size 2.6 2.6) (drill 1.3) (layers *.Cu *.Mask)
(net 24 "Net-(D1-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 2.6 2.6) (drill 1.3) (layers *.Cu *.Mask)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Diode_THT:D_DO-35_SOD27_P12.70mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A286264)
(at 137.16 57.15 180)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 12.7mm length 4mm diameter 2mm")
(path /442A6026)
(fp_text reference D10 (at 6.35 -2.12 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value SCHOTTKY (at 6.35 2.12 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 6.65 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 13.75 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 13.75 1.4) (end 13.75 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 13.75 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.83 -1.12) (end 4.83 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.07 -1.12) (end 5.07 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.95 -1.12) (end 4.95 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 11.66 0) (end 8.47 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 4.23 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.47 -1.12) (end 4.23 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 8.47 1.12) (end 8.47 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.23 1.12) (end 8.47 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.23 -1.12) (end 4.23 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.85 -1) (end 4.85 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 -1) (end 5.05 1) (layer F.Fab) (width 0.1))
(fp_line (start 4.95 -1) (end 4.95 1) (layer F.Fab) (width 0.1))
(fp_line (start 12.7 0) (end 8.35 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 4.35 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.35 -1) (end 4.35 -1) (layer F.Fab) (width 0.1))
(fp_line (start 8.35 1) (end 8.35 -1) (layer F.Fab) (width 0.1))
(fp_line (start 4.35 1) (end 8.35 1) (layer F.Fab) (width 0.1))
(fp_line (start 4.35 -1) (end 4.35 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 12.7 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(D10-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 VPP))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P12.70mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Diode_THT:D_DO-35_SOD27_P12.70mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A23D878)
(at 87.757 71.12 90)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 12.7mm length 4mm diameter 2mm")
(path /442A500B)
(fp_text reference D1 (at 6.35 -2.12 90) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 1N4004 (at 6.35 2.12 90) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 6.65 0 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 13.75 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 13.75 1.4) (end 13.75 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 13.75 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.83 -1.12) (end 4.83 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.07 -1.12) (end 5.07 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.95 -1.12) (end 4.95 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 11.66 0) (end 8.47 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 4.23 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.47 -1.12) (end 4.23 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 8.47 1.12) (end 8.47 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.23 1.12) (end 8.47 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.23 -1.12) (end 4.23 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.85 -1) (end 4.85 1) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 -1) (end 5.05 1) (layer F.Fab) (width 0.1))
(fp_line (start 4.95 -1) (end 4.95 1) (layer F.Fab) (width 0.1))
(fp_line (start 12.7 0) (end 8.35 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 4.35 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.35 -1) (end 4.35 -1) (layer F.Fab) (width 0.1))
(fp_line (start 8.35 1) (end 8.35 -1) (layer F.Fab) (width 0.1))
(fp_line (start 4.35 1) (end 8.35 1) (layer F.Fab) (width 0.1))
(fp_line (start 4.35 -1) (end 4.35 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 12.7 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 "Net-(D1-Pad2)"))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(C2-Pad1)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P12.70mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Composant) (tedit 5A142A3B) (tstamp 5A250C34)
(at 143.002 49.784)
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /464AD280)
(fp_text reference C9 (at 2.5 -2.91) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 220nF (at 2.5 2.91) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 2.5 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(C9-Pad2)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 VPP))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Composant) (tedit 5A142A3B) (tstamp 5A250C20)
(at 198.755 71.12 270)
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /4804A5E2/442AA145)
(fp_text reference C7 (at 2.5 -2.91 270) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 100nF (at 2.5 2.91 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.5 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 23 /pic_sockets/VCC_PIC))
Update demo
2018-01-10 15:41:40 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Composant) (tedit 5A142A3B) (tstamp 5A250CC6)
(at 196.85 112.395 270)
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /4804A5E2/442AA12B)
(fp_text reference C6 (at 2.5 -2.91 270) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 100nF (at 2.5 2.91 270) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 2.5 0 270) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Composant) (tedit 5A142A3B) (tstamp 5A250BF8)
(at 129.54 49.53)
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /442A58B1)
(fp_text reference C5 (at 2.5 -2.91) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 10nF (at 2.5 2.91) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 2.5 0) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo
2018-01-10 15:41:40 +00:00
(net 8 "Net-(C5-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Composant) (tedit 5A142A3B) (tstamp 5A250BE4)
(at 114.3 52.07)
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /442A5F61)
(fp_text reference C4 (at 2.5 -2.91) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 0 (at 2.5 2.91) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 2.5 0) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo
2018-01-10 15:41:40 +00:00
(net 7 "Net-(C4-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:LED_D5.0mm (layer Composant) (tedit 5A22AE99) (tstamp 5A22F4BB)
(at 156.21 97.155 180)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /4639B9EA)
(fp_text reference D12 (at 1.27 -3.96 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value YELLOW-LED (at 1.27 3.96 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 1.25 0) (end 4.5 0) (layer F.CrtYd) (width 0.15))
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 28 "Net-(D12-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:LED_D5.0mm (layer Composant) (tedit 5A22AE99) (tstamp 5A22F4AD)
(at 156.21 87.63 180)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /442A5084)
(fp_text reference D9 (at 1.27 -3.96 180) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value GREEN-LED (at 1.27 3.96 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 1.25 0) (end 4.5 0) (layer F.CrtYd) (width 0.15))
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 27 "Net-(D9-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 5 GND))
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:LED_D5.0mm (layer Composant) (tedit 5A22AE99) (tstamp 5A22F49F)
(at 156.21 77.47 180)
(descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
(tags "LED diameter 5.0mm 2 pins")
(path /442A4F5D)
(fp_text reference D8 (at 1.27 -3.96 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value RED-LED (at 1.27 3.96 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_circle (center 1.25 0) (end 4.5 0) (layer F.CrtYd) (width 0.15))
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.2)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
(fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
(fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 26 "Net-(D8-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(model ${KISYS3DMOD}/LED_THT.3dshapes/LED_D5.0mm.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:TO-220_LM78xx (layer Composant) (tedit 5A228B68) (tstamp 5A2A01D8)
(at 99.06 71.247)
(descr "TO-220 for LM87xx")
(tags "TO-220 LM78xx")
(path /5A238DF8)
(fp_text reference U3 (at 0.24892 -22.84984) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value 7805 (at -0.20066 4.24942) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start -5.75 2) (end -5.75 -21) (layer F.CrtYd) (width 0.15))
(fp_line (start 5.75 2) (end -5.75 2) (layer F.CrtYd) (width 0.15))
(fp_line (start 5.75 -21) (end 5.75 2) (layer F.CrtYd) (width 0.15))
(fp_line (start -5.75 -21) (end 5.75 -21) (layer F.CrtYd) (width 0.15))
(fp_line (start -2.54 -3.683) (end -2.54 -2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -3.683) (end 0 -2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 2.54 -3.683) (end 2.54 -2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 -12.192) (end 5.334 -20.193) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 -20.193) (end -5.334 -20.193) (layer F.SilkS) (width 0.15))
(fp_line (start -5.334 -20.193) (end -5.334 -12.192) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 -3.683) (end 5.334 -12.192) (layer F.SilkS) (width 0.15))
(fp_line (start 5.334 -12.192) (end -5.334 -12.192) (layer F.SilkS) (width 0.15))
(fp_line (start -5.334 -12.192) (end -5.334 -3.683) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -3.683) (end -5.334 -3.683) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -3.683) (end 5.334 -3.683) (layer F.SilkS) (width 0.15))
(pad GND thru_hole oval (at 0 0 90) (size 3.50012 1.69926) (drill 1.00076) (layers *.Cu *.Mask)
(net 5 GND))
(pad VI thru_hole oval (at -2.54 0 90) (size 3.50012 1.69926) (drill 1.00076) (layers *.Cu *.Mask)
(net 6 "Net-(C2-Pad1)"))
(pad VO thru_hole oval (at 2.54 0 270) (size 3.50012 1.69926) (drill 1.00076) (layers *.Cu *.Mask)
(net 21 VCC))
(pad "" thru_hole rect (at 0 -16.764) (size 10 8) (drill 3.2) (layers *.Cu *.Mask))
(model TO_SOT_Packages_THT.3dshapes/TO-220_Neutral123_Horizontal_LargePads.wrl
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 0.3937 0.3937 0.3937))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:TO-92_BC237_307 (layer Composant) (tedit 5A227438) (tstamp 5A228A38)
(at 148.082 60.706 180)
(descr "TO-92 leads molded, narrow, drill 0.6mm")
(tags "to-92 transistor")
(path /442A4F30)
(fp_text reference Q2 (at 1.27 -3.56 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value BC307 (at 1.27 2.79 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 1.27 -3.56 180) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 3 thru_hole circle (at 0 0 270) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 13 "Net-(Q2-Pad3)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole rect (at 2.54 0 270) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 22 VPP))
(pad 2 thru_hole circle (at 1.27 -1.27 270) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 9 "Net-(C9-Pad2)"))
(model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl
(offset (xyz 1.269999980926514 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Update demo
2018-01-10 15:41:40 +00:00
(rotate (xyz 0 0 -90))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:TO-92_BC237_307 (layer Composant) (tedit 5A227438) (tstamp 5A228A49)
(at 146.05 69.85)
(descr "TO-92 leads molded, narrow, drill 0.6mm")
(tags "to-92 transistor")
(path /442A4EB9)
(fp_text reference Q1 (at 1.27 -3.56) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value BC237 (at 1.27 2.79) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 1.27 -3.56) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 3 thru_hole circle (at 0 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 10 "Net-(D11-Pad1)"))
(pad 1 thru_hole rect (at 2.54 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 5 GND))
(pad 2 thru_hole circle (at 1.27 -1.27 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 12 "Net-(Q1-Pad2)"))
(model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl
(offset (xyz 1.269999980926514 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Update demo
2018-01-10 15:41:40 +00:00
(rotate (xyz 0 0 -90))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(module footprints:TO-92_BC237_307 (layer Composant) (tedit 5A227438) (tstamp 5A228A27)
(at 142.24 97.79)
(descr "TO-92 leads molded, narrow, drill 0.6mm")
(tags "to-92 transistor")
(path /4639B996)
(fp_text reference Q3 (at 1.27 -3.56) (layer F.SilkS)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value BC307 (at 1.27 2.79) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 1.27 -3.56) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(pad 3 thru_hole circle (at 0 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(pad 1 thru_hole rect (at 2.54 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 21 VCC))
(pad 2 thru_hole circle (at 1.27 -1.27 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask)
(net 14 "Net-(Q3-Pad2)"))
(model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl
(offset (xyz 1.269999980926514 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Update demo
2018-01-10 15:41:40 +00:00
(rotate (xyz 0 0 -90))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Connector_Dsub:DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm (layer Composant) (tedit 59FEDEE2) (tstamp 5A222DBD)
(at 82.55 121.031 270)
(descr "9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf")
(tags "9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 25mm mounting-hole-offset 25mm")
(path /442A4C93)
(fp_text reference J1 (at -5.54 -2.8 270) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text value DB9-FEMAL (at -5.54 18.61 270) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at -5.54 14.025 270) (layer F.Fab)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 10.4 -2.35) (end -21.5 -2.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.4 17.65) (end 10.4 -2.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -21.5 17.65) (end 10.4 17.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -21.5 -2.35) (end -21.5 17.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -2.321325) (end -0.25 -2.754338) (layer F.SilkS) (width 0.12))
(fp_line (start 0.25 -2.754338) (end 0 -2.321325) (layer F.SilkS) (width 0.12))
(fp_line (start -0.25 -2.754338) (end 0.25 -2.754338) (layer F.SilkS) (width 0.12))
(fp_line (start 9.945 -1.86) (end 9.945 10.48) (layer F.SilkS) (width 0.12))
(fp_line (start -21.025 -1.86) (end 9.945 -1.86) (layer F.SilkS) (width 0.12))
(fp_line (start -21.025 10.48) (end -21.025 -1.86) (layer F.SilkS) (width 0.12))
(fp_line (start 8.56 10.54) (end 8.56 1.42) (layer F.Fab) (width 0.1))
(fp_line (start 5.36 10.54) (end 5.36 1.42) (layer F.Fab) (width 0.1))
(fp_line (start -16.44 10.54) (end -16.44 1.42) (layer F.Fab) (width 0.1))
(fp_line (start -19.64 10.54) (end -19.64 1.42) (layer F.Fab) (width 0.1))
(fp_line (start 9.46 10.94) (end 4.46 10.94) (layer F.Fab) (width 0.1))
(fp_line (start 9.46 15.94) (end 9.46 10.94) (layer F.Fab) (width 0.1))
(fp_line (start 4.46 15.94) (end 9.46 15.94) (layer F.Fab) (width 0.1))
(fp_line (start 4.46 10.94) (end 4.46 15.94) (layer F.Fab) (width 0.1))
(fp_line (start -15.54 10.94) (end -20.54 10.94) (layer F.Fab) (width 0.1))
(fp_line (start -15.54 15.94) (end -15.54 10.94) (layer F.Fab) (width 0.1))
(fp_line (start -20.54 15.94) (end -15.54 15.94) (layer F.Fab) (width 0.1))
(fp_line (start -20.54 10.94) (end -20.54 15.94) (layer F.Fab) (width 0.1))
(fp_line (start 2.61 10.94) (end -13.69 10.94) (layer F.Fab) (width 0.1))
(fp_line (start 2.61 17.11) (end 2.61 10.94) (layer F.Fab) (width 0.1))
(fp_line (start -13.69 17.11) (end 2.61 17.11) (layer F.Fab) (width 0.1))
(fp_line (start -13.69 10.94) (end -13.69 17.11) (layer F.Fab) (width 0.1))
(fp_line (start 9.885 10.54) (end -20.965 10.54) (layer F.Fab) (width 0.1))
(fp_line (start 9.885 10.94) (end 9.885 10.54) (layer F.Fab) (width 0.1))
(fp_line (start -20.965 10.94) (end 9.885 10.94) (layer F.Fab) (width 0.1))
(fp_line (start -20.965 10.54) (end -20.965 10.94) (layer F.Fab) (width 0.1))
(fp_line (start 9.885 -1.8) (end -20.965 -1.8) (layer F.Fab) (width 0.1))
(fp_line (start 9.885 10.54) (end 9.885 -1.8) (layer F.Fab) (width 0.1))
(fp_line (start -20.965 10.54) (end 9.885 10.54) (layer F.Fab) (width 0.1))
(fp_line (start -20.965 -1.8) (end -20.965 10.54) (layer F.Fab) (width 0.1))
(fp_arc (start 6.96 1.42) (end 5.36 1.42) (angle 180) (layer F.Fab) (width 0.1))
(fp_arc (start -18.04 1.42) (end -19.64 1.42) (angle 180) (layer F.Fab) (width 0.1))
(pad 0 thru_hole circle (at 6.96 1.42 270) (size 4 4) (drill 3.2) (layers *.Cu *.Mask))
(pad 0 thru_hole circle (at -18.04 1.42 270) (size 4 4) (drill 3.2) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at -9.695 2.84 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 76 "Net-(J1-Pad9)"))
(pad 8 thru_hole circle (at -6.925 2.84 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 1 /CTS))
(pad 7 thru_hole circle (at -4.155 2.84 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 3 /PC-CLOCK-OUT))
(pad 6 thru_hole circle (at -1.385 2.84 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 75 "Net-(J1-Pad6)"))
(pad 5 thru_hole circle (at -11.08 0 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 5 GND))
(pad 4 thru_hole circle (at -8.31 0 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 2 /DTR))
(pad 3 thru_hole circle (at -5.54 0 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 4 /TXD))
(pad 2 thru_hole circle (at -2.77 0 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 74 "Net-(J1-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 1) (layers *.Cu *.Mask)
(net 73 "Net-(J1-Pad1)"))
(model ${KISYS3DMOD}/Connector_Dsub.3dshapes/DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A217AE2)
(at 107.95 125.095 180)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /442A4D64)
(fp_text reference D6 (at 3.81 -2.12 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value BAT43 (at 3.81 2.12 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
(fp_text user K (at 0 -1.8 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 4.11 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 8.7 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 1.4) (end 8.7 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 8.7 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 "Net-(D6-Pad2)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 VCC))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A217AC4)
(at 107.95 115.316 180)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /442A4D65)
(fp_text reference D7 (at 3.81 -2.12 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value BAT43 (at 3.81 2.12 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.7 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 1.4) (end 8.7 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 8.7 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 "Net-(D6-Pad2)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A217AA6)
(at 139.065 80.645)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /4639BA28)
(fp_text reference D11 (at 3.81 -2.12) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value BAT43 (at 3.81 2.12) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
(fp_text user K (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 4.11 0) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 8.7 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 1.4) (end 8.7 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 8.7 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 2 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(D11-Pad2)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(D11-Pad1)"))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A217A88)
(at 107.95 108.585 180)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /442A4D5D)
(fp_text reference D5 (at 3.81 -2.12 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value BAT43 (at 3.81 2.12 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.7 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 1.4) (end 8.7 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 8.7 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(D4-Pad2)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A217A6A)
(at 107.95 111.887 180)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /442A4D5C)
(fp_text reference D4 (at 3.81 -2.12 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value BAT43 (at 3.81 2.12 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
(fp_text user K (at 0 -1.8 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 4.11 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 8.7 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 1.4) (end 8.7 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 8.7 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(D4-Pad2)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 VCC))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A217A4C)
(at 107.95 121.92 180)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /442A4D25)
(fp_text reference D3 (at 3.81 -2.12 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value BAT43 (at 3.81 2.12 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.8 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.11 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
(fp_line (start 8.7 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 1.4) (end 8.7 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 8.7 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(D2-Pad2)"))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal (layer Composant) (tedit 5A195B5A) (tstamp 5A217A2E)
(at 107.95 118.237 180)
(descr "D, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf")
(tags "D DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm")
(path /442A4D1B)
(fp_text reference D2 (at 3.81 -2.12 180) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value BAT43 (at 3.81 2.12 180) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user K (at 0 -1.8 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
(fp_text user K (at 0 -1.8 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text user %R (at 4.11 0 180) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 8.7 -1.4) (end -1.05 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 1.4) (end 8.7 -1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.4) (end 8.7 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.4) (end -1.05 1.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.29 -1.12) (end 2.29 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.53 -1.12) (end 2.53 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.41 -1.12) (end 2.41 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.58 0) (end 5.93 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 0) (end 1.69 0) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 -1.12) (end 1.69 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 5.93 1.12) (end 5.93 -1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 1.12) (end 5.93 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.69 -1.12) (end 1.69 1.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.31 -1) (end 2.31 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.51 -1) (end 2.51 1) (layer F.Fab) (width 0.1))
(fp_line (start 2.41 -1) (end 2.41 1) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 5.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.81 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 -1) (end 1.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 5.81 1) (end 5.81 -1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 1) (end 5.81 1) (layer F.Fab) (width 0.1))
(fp_line (start 1.81 -1) (end 1.81 1) (layer F.Fab) (width 0.1))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(D2-Pad2)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 VCC))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_DO-35_SOD27_P7.62mm_Horizontal.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Package_DIP:DIP-14_W7.62mm_LongPads (layer Composant) (tedit 5A02E8C5) (tstamp 5A212AD4)
(at 115.57 119.38 90)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads")
(path /442A4D6B)
(fp_text reference U2 (at 3.81 -2.33 90) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value 74HC125 (at 3.81 17.57 90) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user %R (at 3.81 7.62 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 9.1 -1.55) (end -1.45 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 16.8) (end 9.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 16.8) (end 9.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 -1.55) (end -1.45 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 16.57) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 16.57) (end 6.06 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 VCC))
(pad 7 thru_hole oval (at 0 15.24 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 13 thru_hole oval (at 7.62 2.54 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
(pad 6 thru_hole oval (at 0 12.7 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(R12-Pad1)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 12 thru_hole oval (at 7.62 5.08 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 /DATA-RB7))
(pad 5 thru_hole oval (at 0 10.16 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(D4-Pad2)"))
(pad 11 thru_hole oval (at 7.62 7.62 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 /CTS))
(pad 4 thru_hole oval (at 0 7.62 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 10 thru_hole oval (at 7.62 10.16 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 3 thru_hole oval (at 0 5.08 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(R8-Pad1)"))
(pad 9 thru_hole oval (at 7.62 12.7 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 "Net-(D6-Pad2)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(D2-Pad2)"))
(pad 8 thru_hole oval (at 7.62 15.24 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(R13-Pad1)"))
(pad 1 thru_hole rect (at 0 0 90) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Package_DIP:DIP-18_W7.62mm_Socket_LongPads (layer Composant) (tedit 5A02E8C5) (tstamp 5A212AA7)
(at 207.899 107.95)
(descr "18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /4804A5E2/442A81A7)
(fp_text reference U5 (at 3.81 -2.33) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value PIC_18_PINS (at 3.81 22.65) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user %R (at 3.81 10.16) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 21.9) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 21.9) (end 9.15 21.9) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 21.9) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.06 -1.39) (end -1.44 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 9.06 21.71) (end 9.06 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 21.71) (end 9.06 21.71) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.39) (end -1.44 21.71) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 21.65) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 21.65) (end 6.06 21.65) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 21.65) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 21.65) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 21.65) (end 8.89 21.65) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 21.65) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 21.59) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 21.59) (end 0.635 21.59) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 21.59) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 18 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 117 "Net-(U5-Pad18)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 9 thru_hole oval (at 0 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 116 "Net-(U5-Pad9)"))
(pad 17 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 115 "Net-(U5-Pad17)"))
(pad 8 thru_hole oval (at 0 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 114 "Net-(U5-Pad8)"))
(pad 16 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 113 "Net-(U5-Pad16)"))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 112 "Net-(U5-Pad7)"))
(pad 15 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 111 "Net-(U5-Pad15)"))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 110 "Net-(U5-Pad6)"))
(pad 14 thru_hole oval (at 7.62 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 13 thru_hole oval (at 7.62 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 /DATA-RB7))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /VPP/MCLR))
(pad 12 thru_hole oval (at 7.62 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 /CLOCK-RB6))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 109 "Net-(U5-Pad3)"))
(pad 11 thru_hole oval (at 7.62 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 108 "Net-(U5-Pad11)"))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 107 "Net-(U5-Pad2)"))
(pad 10 thru_hole oval (at 7.62 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 106 "Net-(U5-Pad10)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 105 "Net-(U5-Pad1)"))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-18_W7.62mm_Socket.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
)
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Package_DIP:DIP-28_W7.62mm_Socket_LongPads (layer Composant) (tedit 5A02E8C5) (tstamp 5A212A70)
(at 207.645 50.8)
(descr "28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /4804A5E2/4436967E)
(fp_text reference P2 (at 3.81 -2.33) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value SUPP28 (at 3.81 35.35) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user %R (at 3.81 16.51) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 34.65) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 34.65) (end 9.15 34.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 34.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.06 -1.39) (end -1.44 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 9.06 34.41) (end 9.06 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 34.41) (end 9.06 34.41) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.39) (end -1.44 34.41) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 34.35) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 34.35) (end 6.06 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 34.35) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 34.35) (end 8.89 34.35) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 34.35) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 34.29) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 34.29) (end 0.635 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 28 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 /DATA-RB7))
(pad 14 thru_hole oval (at 0 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 104 "Net-(P2-Pad14)"))
(pad 27 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 /CLOCK-RB6))
(pad 13 thru_hole oval (at 0 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 103 "Net-(P2-Pad13)"))
(pad 26 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 102 "Net-(P2-Pad26)"))
(pad 12 thru_hole oval (at 0 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 101 "Net-(P2-Pad12)"))
(pad 25 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 100 "Net-(P2-Pad25)"))
(pad 11 thru_hole oval (at 0 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 99 "Net-(P2-Pad11)"))
(pad 24 thru_hole oval (at 7.62 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 98 "Net-(P2-Pad24)"))
(pad 10 thru_hole oval (at 0 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 97 "Net-(P2-Pad10)"))
(pad 23 thru_hole oval (at 7.62 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 96 "Net-(P2-Pad23)"))
(pad 9 thru_hole oval (at 0 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 95 "Net-(P2-Pad9)"))
(pad 22 thru_hole oval (at 7.62 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 94 "Net-(P2-Pad22)"))
(pad 8 thru_hole oval (at 0 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
(pad 21 thru_hole oval (at 7.62 17.78) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(P2-Pad21)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(P2-Pad7)"))
(pad 20 thru_hole oval (at 7.62 20.32) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(P2-Pad6)"))
(pad 19 thru_hole oval (at 7.62 22.86) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(P2-Pad5)"))
(pad 18 thru_hole oval (at 7.62 25.4) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(P2-Pad18)"))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(P2-Pad4)"))
(pad 17 thru_hole oval (at 7.62 27.94) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(P2-Pad17)"))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(P2-Pad3)"))
(pad 16 thru_hole oval (at 7.62 30.48) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(P2-Pad16)"))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(P2-Pad2)"))
(pad 15 thru_hole oval (at 7.62 33.02) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 83 "Net-(P2-Pad15)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /VPP/MCLR))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-28_W7.62mm_Socket.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Package_DIP:DIP-8_W7.62mm_LongPads (layer Composant) (tedit 5A02E8C5) (tstamp 5A212A55)
(at 110.49 57.15)
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads")
(path /442A5E20)
(fp_text reference U4 (at 3.81 -2.33) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value LT1373 (at 3.81 9.95) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user %R (at 3.81 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 9.1 -1.55) (end -1.45 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 9.15) (end 9.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 9.15) (end 9.1 9.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 -1.55) (end -1.45 9.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 8.95) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 8.95) (end 6.06 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 8.89) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 8.89) (end 0.635 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 8 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(D10-Pad2)"))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 82 "Net-(U4-Pad4)"))
(pad 7 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(net 5 GND))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(U4-Pad3)"))
Update demo
2018-01-10 15:41:40 +00:00
(pad 6 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(RV1-Pad2)"))
(pad 5 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 VCC))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(C4-Pad1)"))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm.wrl
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Package_DIP:DIP-8_W7.62mm_Socket_LongPads (layer Composant) (tedit 5A02E8C5) (tstamp 5A212A32)
(at 179.07 109.22)
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /4804A5E2/442A87F7)
(fp_text reference U1 (at 3.81 -2.33) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value 24Cxx (at 3.81 9.95) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user %R (at 3.81 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 9.2) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 9.2) (end 9.15 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.06 -1.39) (end -1.44 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 9.06 9.01) (end 9.06 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 9.01) (end 9.06 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.39) (end -1.44 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 8.95) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 8.95) (end 6.06 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 8.95) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.95) (end 8.89 8.95) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 8.95) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 8.89) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 8.89) (end 0.635 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 8 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 7 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 80 "Net-(U1-Pad7)"))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(pad 6 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 /CLOCK-RB6))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
(net 5 GND))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 5 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 /DATA-RB7))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(module Package_DIP:DIP-8_W7.62mm_Socket_LongPads (layer Composant) (tedit 5A02E8C5) (tstamp 5A212A0F)
(at 179.07 120.65)
(descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads")
(path /4804A5E2/442A81A5)
(fp_text reference U6 (at 3.81 -2.33) (layer F.SilkS)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text value PIC_8_PINS (at 3.81 9.95) (layer F.Fab)
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(fp_text user %R (at 3.81 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update demo
2018-01-10 15:41:40 +00:00
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 9.2) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 9.2) (end 9.15 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 -1.6) (end -1.55 9.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.06 -1.39) (end -1.44 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 9.06 9.01) (end 9.06 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 9.01) (end 9.06 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start -1.44 -1.39) (end -1.44 9.01) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 8.95) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 8.95) (end 6.06 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 8.95) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.95) (end 8.89 8.95) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 8.95) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 8.89) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 8.89) (end 0.635 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(pad 8 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 /VPP/MCLR))
(pad 7 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 /DATA-RB7))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 79 "Net-(U6-Pad3)"))
(pad 6 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 /CLOCK-RB6))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 78 "Net-(U6-Pad2)"))
(pad 5 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 "Net-(U6-Pad5)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 /pic_sockets/VCC_PIC))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
(at (xyz 0 0 0))
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
(scale (xyz 1 1 1))
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module connect:GS2 (layer Cuivre) (tedit 5A295E0E) (tstamp 5A295FB8)
(at 148.082 97.79 270)
(descr "Pontet Goute de soudure")
(path /4639BAF8)
(attr virtual)
(fp_text reference JP1 (at 1.778 0 180) (layer B.SilkS)
(effects (font (size 1.016 0.762) (thickness 0.127)) (justify mirror))
)
(fp_text value JUMPER (at 1.524 0 180) (layer B.SilkS) hide
(effects (font (size 0.762 0.762) (thickness 0.127)) (justify mirror))
)
(fp_line (start -0.889 1.27) (end -0.889 -1.27) (layer B.SilkS) (width 0.127))
(fp_line (start 0.889 -1.27) (end 0.889 1.27) (layer B.SilkS) (width 0.127))
(fp_line (start 0.889 -1.27) (end -0.889 -1.27) (layer B.SilkS) (width 0.127))
(fp_line (start -0.889 1.27) (end 0.889 1.27) (layer B.SilkS) (width 0.127))
(fp_line (start -1 1.5) (end 1 1.5) (layer B.CrtYd) (width 0.15))
(fp_line (start 1 1.5) (end 1 -1.5) (layer B.CrtYd) (width 0.15))
(fp_line (start 1 -1.5) (end -1 -1.5) (layer B.CrtYd) (width 0.15))
(fp_line (start -1 -1.5) (end -1 1.5) (layer B.CrtYd) (width 0.15))
(pad 1 smd rect (at 0 0.635 270) (size 1.27 0.9652) (layers Cuivre B.Paste B.Mask)
(net 21 VCC))
(pad 2 smd rect (at 0 -0.635 270) (size 1.27 0.9652) (layers Cuivre B.Paste B.Mask)
(net 23 /pic_sockets/VCC_PIC))
)
(module Capacitors_THT:CP_Axial_L18.0mm_D6.5mm_P25.00mm_Horizontal (layer Composant) (tedit 5A142A3B) (tstamp 54032B95)
(at 84.582 90.17)
(descr "CP, Axial series, Axial, Horizontal, pin pitch=25mm, Electrolytic Capacitor, http://www.vishay.com/docs/28325/021asm.pdf")
(tags "CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 6.5mm Electrolytic Capacitor")
(path /442A501D)
(fp_text reference C2 (at 12.5 -4.31) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 220uF (at 12.5 4.31) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 12.5 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 26.45 -3.6) (end -1.45 -3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 26.45 3.6) (end 26.45 -3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 3.6) (end 26.45 3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 -3.6) (end -1.45 3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 23.62 0) (end 21.56 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.38 0) (end 3.44 0) (layer F.SilkS) (width 0.12))
(fp_line (start 7.04 3.31) (end 21.56 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 6.14 2.41) (end 7.04 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 5.24 3.31) (end 6.14 2.41) (layer F.SilkS) (width 0.12))
(fp_line (start 3.44 3.31) (end 5.24 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 7.04 -3.31) (end 21.56 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 6.14 -2.41) (end 7.04 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 5.24 -3.31) (end 6.14 -2.41) (layer F.SilkS) (width 0.12))
(fp_line (start 3.44 -3.31) (end 5.24 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 21.56 -3.31) (end 21.56 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 3.44 -3.31) (end 3.44 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 6.15 -0.9) (end 6.15 0.9) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 0) (end 7.05 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.15 -0.9) (end 6.15 0.9) (layer F.Fab) (width 0.1))
(fp_line (start 5.25 0) (end 7.05 0) (layer F.Fab) (width 0.1))
(fp_line (start 25 0) (end 21.5 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.5 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.04 3.25) (end 21.5 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.14 2.35) (end 7.04 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 5.24 3.25) (end 6.14 2.35) (layer F.Fab) (width 0.1))
(fp_line (start 3.5 3.25) (end 5.24 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 7.04 -3.25) (end 21.5 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.14 -2.35) (end 7.04 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 5.24 -3.25) (end 6.14 -2.35) (layer F.Fab) (width 0.1))
(fp_line (start 3.5 -3.25) (end 5.24 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.5 -3.25) (end 21.5 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 3.5 -3.25) (end 3.5 3.25) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 25 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 5 GND))
(pad 1 thru_hole rect (at 0 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 6 "Net-(C2-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Axial_L18.0mm_D6.5mm_P25.00mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:CP_Axial_L18.0mm_D6.5mm_P25.00mm_Horizontal (layer Composant) (tedit 5A142A3B) (tstamp 54032B86)
(at 110.49 78.867 180)
(descr "CP, Axial series, Axial, Horizontal, pin pitch=25mm, Electrolytic Capacitor, http://www.vishay.com/docs/28325/021asm.pdf")
(tags "CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 6.5mm Electrolytic Capacitor")
(path /442A5056)
(fp_text reference C1 (at 12.5 -4.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100µF (at 12.5 4.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.5 -3.25) (end 3.5 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 21.5 -3.25) (end 21.5 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 3.5 -3.25) (end 5.24 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 5.24 -3.25) (end 6.14 -2.35) (layer F.Fab) (width 0.1))
(fp_line (start 6.14 -2.35) (end 7.04 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 7.04 -3.25) (end 21.5 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 3.5 3.25) (end 5.24 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 5.24 3.25) (end 6.14 2.35) (layer F.Fab) (width 0.1))
(fp_line (start 6.14 2.35) (end 7.04 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 7.04 3.25) (end 21.5 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.5 0) (layer F.Fab) (width 0.1))
(fp_line (start 25 0) (end 21.5 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.25 0) (end 7.05 0) (layer F.Fab) (width 0.1))
(fp_line (start 6.15 -0.9) (end 6.15 0.9) (layer F.Fab) (width 0.1))
(fp_line (start 5.25 0) (end 7.05 0) (layer F.SilkS) (width 0.12))
(fp_line (start 6.15 -0.9) (end 6.15 0.9) (layer F.SilkS) (width 0.12))
(fp_line (start 3.44 -3.31) (end 3.44 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 21.56 -3.31) (end 21.56 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 3.44 -3.31) (end 5.24 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 5.24 -3.31) (end 6.14 -2.41) (layer F.SilkS) (width 0.12))
(fp_line (start 6.14 -2.41) (end 7.04 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 7.04 -3.31) (end 21.56 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 3.44 3.31) (end 5.24 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 5.24 3.31) (end 6.14 2.41) (layer F.SilkS) (width 0.12))
(fp_line (start 6.14 2.41) (end 7.04 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 7.04 3.31) (end 21.56 3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.38 0) (end 3.44 0) (layer F.SilkS) (width 0.12))
(fp_line (start 23.62 0) (end 21.56 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.45 -3.6) (end -1.45 3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 3.6) (end 26.45 3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 26.45 3.6) (end 26.45 -3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 26.45 -3.6) (end -1.45 -3.6) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 12.5 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 21 VCC))
(pad 2 thru_hole oval (at 25 0 180) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 5 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Axial_L18.0mm_D6.5mm_P25.00mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Axial_L12.0mm_D6.5mm_P20.00mm_Horizontal (layer Composant) (tedit 5A285655) (tstamp 5A2A02A0)
(at 134.112 62.23 270)
(descr "C, Axial series, Axial, Horizontal, pin pitch=20mm, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf")
(tags "C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 6.5mm")
(path /442A584C)
(fp_text reference C3 (at 10 -4.31 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22uF/25V (at 10 4.31 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 10 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 21.05 -3.6) (end -1.05 -3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 21.05 3.6) (end 21.05 -3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 3.6) (end 21.05 3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -3.6) (end -1.05 3.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 19.02 0) (end 16.06 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 3.94 0) (layer F.SilkS) (width 0.12))
(fp_line (start 16.06 -3.31) (end 3.94 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 16.06 3.31) (end 16.06 -3.31) (layer F.SilkS) (width 0.12))
(fp_line (start 3.94 3.31) (end 16.06 3.31) (layer F.SilkS) (width 0.12))
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Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
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2017-12-07 17:28:11 +00:00
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2014-08-31 16:19:07 +00:00
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2017-12-07 17:28:11 +00:00
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Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
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2017-12-07 17:28:11 +00:00
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Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
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2017-12-07 17:28:11 +00:00
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2014-08-31 16:19:07 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
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2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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2017-12-07 17:28:11 +00:00
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2016-06-26 14:43:18 +00:00
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2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 14:43:18 +00:00
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Update demos
2017-11-21 20:26:06 +00:00
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Update demo to use latest libraries.
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Update demos
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Update demo to use latest libraries.
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Update demos
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Update demo to use latest libraries.
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Update demos
2017-11-21 20:26:06 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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2017-11-21 20:26:06 +00:00
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2017-12-07 17:28:11 +00:00
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Update demos
2017-11-21 20:26:06 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 16:19:07 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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2017-12-07 17:28:11 +00:00
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Update demos
2017-11-21 20:26:06 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Update demos
2017-11-21 20:26:06 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Update demos
2017-11-21 20:26:06 +00:00
(xy 127.518496 73.786195) (xy 127.515466 73.789884) (xy 127.475831 73.863802) (xy 127.435425 73.937301) (xy 127.433981 73.941852)
Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Update demos
2017-11-21 20:26:06 +00:00
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Update demo to use latest libraries.
2017-12-07 17:28:11 +00:00
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Update demo
2018-01-10 15:41:40 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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