kicad/demos/simulation/sallen_key/sallen_key.sch

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EESchema Schematic File Version 4
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LIBS:sallen_key-cache
EELAYER 26 0
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EELAYER END
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L sallen_key_schlib:VSOURCE V1
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.ac dec 10 1 1Meg\n
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L sallen_key_schlib:Generic_Opamp U1
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F 1 "AD8051" H 7900 4250 50 0000 L CNN
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F 2 "" H 7750 4300 50 0000 C CNN
F 3 "" H 7850 4400 50 0000 C CNN
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F 4 "X" H 7850 4400 60 0001 C CNN "Spice_Primitive"
F 5 "AD8051" H 7850 4400 60 0001 C CNN "Spice_Model"
F 6 "ad8051.lib" H 7850 4400 60 0001 C CNN "Spice_Lib_File"
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F 7 "Y" H 7850 4400 60 0001 C CNN "Spice_Netlist_Enabled"
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L sallen_key_schlib:VSOURCE V2
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2016-08-11 12:42:22 +00:00
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$EndComp
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L sallen_key_schlib:VSOURCE V3
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2016-08-11 12:42:22 +00:00
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L sallen_key_schlib:GND #PWR5
2016-08-11 12:42:06 +00:00
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L sallen_key_schlib:VDD #PWR6
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2016-08-11 12:42:22 +00:00
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L sallen_key_schlib:VSS #PWR7
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2016-08-11 12:42:22 +00:00
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F 2 "" H 9650 2600 50 0000 C CNN
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L sallen_key_schlib:VDD #PWR3
2016-08-11 12:42:06 +00:00
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L sallen_key_schlib:VSS #PWR4
2016-08-11 12:42:06 +00:00
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L sallen_key_schlib:R R2
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F 4 "Value" H 6950 4300 60 0001 C CNN "Fieldname"
F 5 "1 2" H 6950 4300 60 0001 C CNN "SpiceMapping"
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$EndComp
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L sallen_key_schlib:R R1
2016-08-11 12:42:06 +00:00
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L sallen_key_schlib:C C1
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L sallen_key_schlib:C C2
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F 5 "C" H 7350 4000 60 0001 C CNN "Spice_Primitive"
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$EndComp
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L sallen_key_schlib:GND #PWR2
2016-08-11 12:42:06 +00:00
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$EndComp
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
L sallen_key_schlib:GND #PWR?
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$EndComp
2016-08-11 12:42:06 +00:00
$EndSCHEMATC