demos: some simulation examples [wip]
This commit is contained in:
Tomasz Wlostowski
Maciej Suminski
parent
e691565fe3
commit
cf9abef23a
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# C
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#
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DEF C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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C?
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C_????_*
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C_????
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SMD*_c
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Capacitor*
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Capacitors_ThroughHole:C_Radial_D10_L13_P5
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Capacitors_SMD:C_0805
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Capacitors_SMD:C_1206
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$ENDFPLIST
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 40 40 1 1 P
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X ~ 2 0 -150 110 U 40 40 1 1 P
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ENDDRAW
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ENDDEF
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#
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# D
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#
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DEF D D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "D" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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Diode_*
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D-Pak_TO252AA
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*SingleDiode
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*_Diode_*
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*SingleDiode*
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$ENDFPLIST
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DRAW
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P 2 0 1 6 -50 50 -50 -50 N
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P 3 0 1 0 50 50 -50 0 50 -50 F
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GND
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#
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DEF GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -250 50 H I C CNN
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F1 "GND" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# R
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#
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DEF R R 0 0 N Y 1 F N
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F0 "R" 80 0 50 V V C CNN
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F1 "R" 0 0 50 V V C CNN
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F2 "" -70 0 50 V V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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R_*
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Resistor_*
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$ENDFPLIST
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DRAW
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S -40 -100 40 100 0 1 10 N
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# VSOURCE
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#
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DEF ~VSOURCE V 0 40 Y Y 1 F N
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F0 "V" 200 200 50 H V C CNN
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F1 "VSOURCE" 250 100 50 H I C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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F4 "Value" 0 0 60 H I C CNN "Fieldname"
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F5 "V" 0 0 60 H I C CNN "Spice_Primitive"
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F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence"
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DRAW
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C 0 0 100 0 1 0 N
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P 2 0 1 0 0 -75 0 75 N
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P 4 0 1 0 0 75 -25 25 25 25 0 75 F
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X ~ 1 0 200 100 D 50 50 1 1 I
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X ~ 2 0 -200 100 U 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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#End Library
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@ -0,0 +1,63 @@
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update=śro, 11 maj 2016, 18:59:29
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version=1
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last_client=eeschema
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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||||
version=1
|
||||
LastNetListRead=
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UseCmpFile=1
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||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
|
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[cvpcb]
|
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version=1
|
||||
NetIExt=net
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[eeschema]
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version=1
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LibDir=/home/twl/Kicad-dev/kicad-library/library
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[eeschema/libraries]
|
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LibName1=power
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LibName2=device
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LibName3=transistors
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LibName4=conn
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LibName5=linear
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||||
LibName6=regul
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LibName7=74xx
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LibName8=cmos4000
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LibName9=adc-dac
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LibName10=memory
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||||
LibName11=xilinx
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||||
LibName12=microcontrollers
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||||
LibName13=dsp
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||||
LibName14=microchip
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||||
LibName15=analog_switches
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||||
LibName16=motorola
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||||
LibName17=texas
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||||
LibName18=intel
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LibName19=audio
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LibName20=interface
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||||
LibName21=digital-audio
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LibName22=philips
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LibName23=display
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LibName24=cypress
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||||
LibName25=siliconi
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LibName26=opto
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LibName27=atmel
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LibName28=contrib
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LibName29=valves
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LibName30=pspice
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@ -0,0 +1,159 @@
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EESchema Schematic File Version 2
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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||||
LIBS:74xx
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||||
LIBS:cmos4000
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||||
LIBS:adc-dac
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LIBS:memory
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||||
LIBS:xilinx
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||||
LIBS:microcontrollers
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||||
LIBS:dsp
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||||
LIBS:microchip
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||||
LIBS:analog_switches
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||||
LIBS:motorola
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||||
LIBS:texas
|
||||
LIBS:intel
|
||||
LIBS:audio
|
||||
LIBS:interface
|
||||
LIBS:digital-audio
|
||||
LIBS:philips
|
||||
LIBS:display
|
||||
LIBS:cypress
|
||||
LIBS:siliconi
|
||||
LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:pspice
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EELAYER 25 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 1
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L VSOURCE V1
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U 1 1 57336052
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P 4400 4050
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F 0 "V1" H 4528 4096 50 0000 L CNN
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F 1 "SINE(0 1.5 1k 0 0 0 0)" H 4528 4005 50 0000 L CNN
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F 2 "" H 4400 4050 50 0000 C CNN
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F 3 "" H 4400 4050 50 0000 C CNN
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F 4 "Value" H 4400 4050 60 0001 C CNN "Fieldname"
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F 5 "V" H 4400 4050 60 0001 C CNN "Spice_Primitive"
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F 6 "1 2" H 4100 4250 60 0001 C CNN "Spice_Node_Sequence"
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1 4400 4050
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-1 0 0 1
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$EndComp
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$Comp
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L GND #PWR1
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U 1 1 573360D3
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P 4400 4350
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F 0 "#PWR1" H 4400 4100 50 0001 C CNN
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F 1 "GND" H 4405 4177 50 0000 C CNN
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F 2 "" H 4400 4350 50 0000 C CNN
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||||
F 3 "" H 4400 4350 50 0000 C CNN
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||||
1 4400 4350
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1 0 0 -1
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||||
$EndComp
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||||
$Comp
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||||
L R R1
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U 1 1 573360F5
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P 4650 3700
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F 0 "R1" V 4443 3700 50 0000 C CNN
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||||
F 1 "1k" V 4534 3700 50 0000 C CNN
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||||
F 2 "" V 4580 3700 50 0000 C CNN
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F 3 "" H 4650 3700 50 0000 C CNN
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F 4 "Value" H 4650 3700 60 0001 C CNN "Fieldname"
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F 5 "1 2" H 4650 3700 60 0001 C CNN "SpiceMapping"
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F 6 "R" V 4650 3700 60 0001 C CNN "Spice_Primitive"
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1 4650 3700
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0 1 1 0
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$EndComp
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||||
$Comp
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||||
L D D1
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U 1 1 573361B8
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P 5100 3700
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F 0 "D1" H 5100 3485 50 0000 C CNN
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F 1 "1N4148" H 5100 3576 50 0000 C CNN
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F 2 "" H 5100 3700 50 0000 C CNN
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F 3 "" H 5100 3700 50 0000 C CNN
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F 4 "Value" H 5100 3700 60 0001 C CNN "Fieldname"
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F 5 "D" H 5100 3700 60 0001 C CNN "Spice_Primitive"
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F 6 "2 1" H 5100 3700 60 0001 C CNN "Spice_Node_Sequence"
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1 5100 3700
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-1 0 0 1
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$EndComp
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||||
$Comp
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||||
L C C1
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U 1 1 5733628F
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P 5400 4000
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F 0 "C1" H 5515 4046 50 0000 L CNN
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F 1 "100n" H 5515 3955 50 0000 L CNN
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F 2 "" H 5438 3850 50 0000 C CNN
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F 3 "" H 5400 4000 50 0000 C CNN
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F 4 "Value" H 5400 4000 60 0001 C CNN "Fieldname"
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F 5 "C" H 5400 4000 60 0001 C CNN "Spice_Primitive"
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F 6 "1 2" H 5400 4000 60 0001 C CNN "SpiceMapping"
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||||
1 5400 4000
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||||
1 0 0 -1
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||||
$EndComp
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||||
$Comp
|
||||
L R R2
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||||
U 1 1 573362F7
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||||
P 5750 4000
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||||
F 0 "R2" H 5680 3954 50 0000 R CNN
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||||
F 1 "100k" H 5680 4045 50 0000 R CNN
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||||
F 2 "" V 5680 4000 50 0000 C CNN
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F 3 "" H 5750 4000 50 0000 C CNN
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F 4 "Value" H 5750 4000 60 0001 C CNN "Fieldname"
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F 5 "1 2" H 5750 4000 60 0001 C CNN "SpiceMapping"
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F 6 "R" V 5750 4000 60 0001 C CNN "Spice_Primitive"
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1 5750 4000
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||||
-1 0 0 1
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||||
$EndComp
|
||||
Text Notes 4300 4900 0 60 ~ 0
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.tran 1u 10m\n
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Wire Wire Line
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4400 4350 4400 4250
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Wire Wire Line
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4400 4300 5750 4300
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||||
Connection ~ 4400 4300
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||||
Wire Wire Line
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||||
5250 3700 5750 3700
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Wire Wire Line
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5750 3700 5750 3850
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||||
Wire Wire Line
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5400 3850 5400 3700
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Connection ~ 5400 3700
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Wire Wire Line
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5400 4300 5400 4150
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Wire Wire Line
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5750 4300 5750 4150
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Connection ~ 5400 4300
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Wire Wire Line
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4800 3700 4950 3700
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Connection ~ 4900 3700
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||||
Wire Wire Line
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||||
4400 3850 4400 3700
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||||
Wire Wire Line
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||||
4400 3700 4500 3700
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||||
Text Label 4400 3800 0 60 ~ 0
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||||
in
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||||
Text Label 5550 3700 0 60 ~ 0
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rect
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||||
Text Notes 4300 5000 0 60 ~ 0
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||||
*.ac dec 10 1 1Meg\n
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||||
$EndSCHEMATC
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||||
|
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@ -0,0 +1,112 @@
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* AD8051 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: Single 110 MHz rail-to-rail op amp - 3V
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* Developed by: JCH / ADI
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* Revision History: 08/10/2012 - Updated to new header style
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* 0.0 (09/1998)
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* Copyright 1998, 2012 by Analog Devices, Inc.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Not Modeled:
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* CMRR IS NOT MODELED
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*
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* Parameters modeled include:
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* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V)
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*
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* END Notes
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*
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* Node assignments
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* noninverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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* | | | | |
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.SUBCKT AD8051 1 2 99 50 45
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*
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* INPUT STAGE
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*
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Q1 4 3 5 QPI
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Q2 6 2 7 QPI
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RC1 50 4 20.5k
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RC2 50 6 20.5k
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RE1 5 8 5k
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RE2 7 8 5k
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EOS 3 1 POLY(1) 53 98 1.7E-3 1
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IOS 1 2 0.1u
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FNOI1 1 0 VMEAS2 1E-4
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FNOI2 2 0 VMEAS2 1E-4
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CPAR1 3 50 1.7p
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CPAR2 2 50 1.7p
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VCMH1 99 9 1
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VCMH2 99 10 1
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D1 5 9 DX
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D2 7 10 DX
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IBIAS 99 8 73u
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*
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* INTERNAL VOLTAGE REFERENCE
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*
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EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5
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EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5
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GREF2 97 0 97 0 1E-6
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*
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*VOLTAGE NOISE STAGE
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*
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DN1 51 52 DNOI1
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VN1 51 98 0.61
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VMEAS 52 98 0
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RNOI1 52 98 6.5E-3
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H1 53 98 VMEAS 1
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RNOI2 53 98 1
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*
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*CURRENT NOISE STAGE
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*
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DN2 61 62 DNOI2
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VN2 61 98 0.545
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VMEAS2 62 98 0
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RNOI3 62 98 2E-4
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*
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* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz
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*
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G1 98 20 4 6 1E-3
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RP1 98 20 550
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CP1 98 20 3p
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*
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* GAIN STAGE WITH DOMINANT POLE
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*
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G4 98 30 20 98 2.6E-3
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RG1 30 98 155k
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CF1 30 45 13.5p
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D5 31 99 DX
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D6 50 32 DX
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V1 31 30 0.6
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V2 30 32 0.6
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*
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* OUTPUT STAGE
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*
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Q3 45 42 99 QPOX
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Q4 45 44 50 QNOX
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EO3 99 42 POLY(1) 98 30 0.7175 0.5
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EO4 44 50 POLY(1) 30 98 0.7355 0.5
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*
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* MODELS
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*
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.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6)
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.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3)
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.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6)
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.MODEL DX D(IS=1E-16)
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.MODEL DZ D(IS=1E-14,BV=6.6)
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.MODEL DNOI1 D(KF=9E-10)
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.MODEL DNOI2 D(KF=1E-8)
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.ENDS AD8051
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@ -0,0 +1,124 @@
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# C
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#
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DEF C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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C?
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C_????_*
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C_????
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SMD*_c
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Capacitor*
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Capacitors_ThroughHole:C_Radial_D10_L13_P5
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Capacitors_SMD:C_0805
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Capacitors_SMD:C_1206
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$ENDFPLIST
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 40 40 1 1 P
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X ~ 2 0 -150 110 U 40 40 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GND
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#
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DEF GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -250 50 H I C CNN
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||||
F1 "GND" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# Generic_Opamp
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#
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DEF Generic_Opamp U 0 20 Y Y 1 F N
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F0 "U" 0 250 50 H V L CNN
|
||||
F1 "Generic_Opamp" 0 150 50 H V L CNN
|
||||
F2 "" -100 -100 50 H V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
DRAW
|
||||
P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f
|
||||
X + 1 -300 100 100 R 50 50 1 1 I
|
||||
X - 2 -300 -100 100 R 50 50 1 1 I
|
||||
X V+ 3 -100 300 150 D 50 50 1 1 W
|
||||
X V- 4 -100 -300 150 U 50 50 1 1 W
|
||||
X ~ 5 300 0 100 L 50 50 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# R
|
||||
#
|
||||
DEF R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
Resistor_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# VDD
|
||||
#
|
||||
DEF VDD #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "VDD" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
DRAW
|
||||
C 0 75 25 0 1 0 N
|
||||
P 2 0 1 0 0 0 0 50 N
|
||||
X VDD 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# VSOURCE
|
||||
#
|
||||
DEF ~VSOURCE V 0 40 Y Y 1 F N
|
||||
F0 "V" 200 200 50 H V C CNN
|
||||
F1 "VSOURCE" 250 100 50 H I C CNN
|
||||
F2 "" 0 0 50 H V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
F4 "Value" 0 0 60 H I C CNN "Fieldname"
|
||||
F5 "V" 0 0 60 H I C CNN "Spice_Primitive"
|
||||
F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence"
|
||||
DRAW
|
||||
C 0 0 100 0 1 0 N
|
||||
P 2 0 1 0 0 -75 0 75 N
|
||||
P 4 0 1 0 0 75 -25 25 25 25 0 75 F
|
||||
X ~ 1 0 200 100 D 50 50 1 1 I
|
||||
X ~ 2 0 -200 100 U 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# VSS
|
||||
#
|
||||
DEF VSS #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "VSS" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
DRAW
|
||||
C 0 75 25 0 1 0 N
|
||||
P 2 0 1 0 0 0 0 50 N
|
||||
X VSS 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
update=pią, 15 lip 2016, 17:18:36
|
||||
version=1
|
||||
last_client=eeschema
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
|
||||
BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=../../kicad-library/library
|
||||
[eeschema/libraries]
|
||||
LibName1=power
|
||||
LibName2=device
|
||||
LibName3=transistors
|
||||
LibName4=conn
|
||||
LibName5=linear
|
||||
LibName6=regul
|
||||
LibName7=74xx
|
||||
LibName8=cmos4000
|
||||
LibName9=adc-dac
|
||||
LibName10=memory
|
||||
LibName11=xilinx
|
||||
LibName12=microcontrollers
|
||||
LibName13=dsp
|
||||
LibName14=microchip
|
||||
LibName15=analog_switches
|
||||
LibName16=motorola
|
||||
LibName17=texas
|
||||
LibName18=intel
|
||||
LibName19=audio
|
||||
LibName20=interface
|
||||
LibName21=digital-audio
|
||||
LibName22=philips
|
||||
LibName23=display
|
||||
LibName24=cypress
|
||||
LibName25=siliconi
|
||||
LibName26=opto
|
||||
LibName27=atmel
|
||||
LibName28=contrib
|
||||
LibName29=valves
|
||||
LibName30=pspice
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=
|
||||
SpiceForceRefPrefix=0
|
||||
SpiceUseNetNumbers=0
|
||||
LabSize=60
|
||||
ERC_TestSimilarLabels=1
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
EESchema Schematic File Version 2
|
||||
LIBS:power
|
||||
LIBS:device
|
||||
LIBS:transistors
|
||||
LIBS:conn
|
||||
LIBS:linear
|
||||
LIBS:regul
|
||||
LIBS:74xx
|
||||
LIBS:cmos4000
|
||||
LIBS:adc-dac
|
||||
LIBS:memory
|
||||
LIBS:xilinx
|
||||
LIBS:microcontrollers
|
||||
LIBS:dsp
|
||||
LIBS:microchip
|
||||
LIBS:analog_switches
|
||||
LIBS:motorola
|
||||
LIBS:texas
|
||||
LIBS:intel
|
||||
LIBS:audio
|
||||
LIBS:interface
|
||||
LIBS:digital-audio
|
||||
LIBS:philips
|
||||
LIBS:display
|
||||
LIBS:cypress
|
||||
LIBS:siliconi
|
||||
LIBS:opto
|
||||
LIBS:atmel
|
||||
LIBS:contrib
|
||||
LIBS:valves
|
||||
LIBS:pspice
|
||||
LIBS:sallen_key-cache
|
||||
EELAYER 25 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L VSOURCE V1
|
||||
U 1 1 57336052
|
||||
P 6000 4700
|
||||
F 0 "V1" H 6128 4746 50 0000 L CNN
|
||||
F 1 "AC 1" H 6128 4655 50 0000 L CNN
|
||||
F 2 "" H 6000 4700 50 0000 C CNN
|
||||
F 3 "" H 6000 4700 50 0000 C CNN
|
||||
F 4 "Value" H 6000 4700 60 0001 C CNN "Fieldname"
|
||||
F 5 "V" H 6000 4700 60 0001 C CNN "Spice_Primitive"
|
||||
F 6 "1 2" H 5700 4900 60 0001 C CNN "Spice_Node_Sequence"
|
||||
1 6000 4700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Notes 4300 4900 0 60 ~ 0
|
||||
*.tran 1u 10m\n
|
||||
Text Notes 4300 4800 0 60 ~ 0
|
||||
.include diodes.lib\n
|
||||
Text Label 8550 4400 0 60 ~ 0
|
||||
lowpass
|
||||
Text Notes 4300 5000 0 60 ~ 0
|
||||
.ac dec 10 1 1Meg\n
|
||||
$Comp
|
||||
L Generic_Opamp U1
|
||||
U 1 1 5788FF9F
|
||||
P 7850 4400
|
||||
F 0 "U1" H 8191 4446 50 0000 L CNN
|
||||
F 1 "AD8051" H 8191 4355 50 0000 L CNN
|
||||
F 2 "" H 7750 4300 50 0000 C CNN
|
||||
F 3 "" H 7850 4400 50 0000 C CNN
|
||||
F 4 "Value" H 7850 4400 60 0001 C CNN "Fieldname"
|
||||
F 5 "X" H 7850 4400 60 0001 C CNN "Spice_Primitive"
|
||||
F 6 "AD8051" H 7850 4400 60 0001 C CNN "Spice_Model"
|
||||
F 7 "Y" H 7850 4400 60 0001 C CNN "Spice_Netlist_Enabled"
|
||||
F 8 "/home/twl/Kicad-dev/kicad-git/eeschema/AD8051.lib" H 7850 4400 60 0001 C CNN "Spice_Lib_File"
|
||||
1 7850 4400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L VSOURCE V2
|
||||
U 1 1 578900BA
|
||||
P 9650 1900
|
||||
F 0 "V2" H 9778 1946 50 0000 L CNN
|
||||
F 1 "DC 10" H 9778 1855 50 0000 L CNN
|
||||
F 2 "" H 9650 1900 50 0000 C CNN
|
||||
F 3 "" H 9650 1900 50 0000 C CNN
|
||||
F 4 "Value" H 9650 1900 60 0001 C CNN "Fieldname"
|
||||
F 5 "V" H 9650 1900 60 0001 C CNN "Spice_Primitive"
|
||||
F 6 "1 2" H 9350 2100 60 0001 C CNN "Spice_Node_Sequence"
|
||||
1 9650 1900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L VSOURCE V3
|
||||
U 1 1 57890232
|
||||
P 9650 2300
|
||||
F 0 "V3" H 9778 2346 50 0000 L CNN
|
||||
F 1 "DC 10" H 9778 2255 50 0000 L CNN
|
||||
F 2 "" H 9650 2300 50 0000 C CNN
|
||||
F 3 "" H 9650 2300 50 0000 C CNN
|
||||
F 4 "Value" H 9650 2300 60 0001 C CNN "Fieldname"
|
||||
F 5 "V" H 9650 2300 60 0001 C CNN "Spice_Primitive"
|
||||
F 6 "1 2" H 9350 2500 60 0001 C CNN "Spice_Node_Sequence"
|
||||
1 9650 2300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L GND #PWR5
|
||||
U 1 1 578902D2
|
||||
P 9400 2100
|
||||
F 0 "#PWR5" H 9400 1850 50 0001 C CNN
|
||||
F 1 "GND" H 9405 1927 50 0000 C CNN
|
||||
F 2 "" H 9400 2100 50 0000 C CNN
|
||||
F 3 "" H 9400 2100 50 0000 C CNN
|
||||
1 9400 2100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L VDD #PWR6
|
||||
U 1 1 578903C0
|
||||
P 9650 1700
|
||||
F 0 "#PWR6" H 9650 1550 50 0001 C CNN
|
||||
F 1 "VDD" H 9667 1873 50 0000 C CNN
|
||||
F 2 "" H 9650 1700 50 0000 C CNN
|
||||
F 3 "" H 9650 1700 50 0000 C CNN
|
||||
1 9650 1700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L VSS #PWR7
|
||||
U 1 1 578903E2
|
||||
P 9650 2500
|
||||
F 0 "#PWR7" H 9650 2350 50 0001 C CNN
|
||||
F 1 "VSS" H 9668 2673 50 0000 C CNN
|
||||
F 2 "" H 9650 2500 50 0000 C CNN
|
||||
F 3 "" H 9650 2500 50 0000 C CNN
|
||||
1 9650 2500
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L VDD #PWR3
|
||||
U 1 1 57890425
|
||||
P 7750 4100
|
||||
F 0 "#PWR3" H 7750 3950 50 0001 C CNN
|
||||
F 1 "VDD" H 7767 4273 50 0000 C CNN
|
||||
F 2 "" H 7750 4100 50 0000 C CNN
|
||||
F 3 "" H 7750 4100 50 0000 C CNN
|
||||
1 7750 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L VSS #PWR4
|
||||
U 1 1 57890453
|
||||
P 7750 4700
|
||||
F 0 "#PWR4" H 7750 4550 50 0001 C CNN
|
||||
F 1 "VSS" H 7768 4873 50 0000 C CNN
|
||||
F 2 "" H 7750 4700 50 0000 C CNN
|
||||
F 3 "" H 7750 4700 50 0000 C CNN
|
||||
1 7750 4700
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R2
|
||||
U 1 1 57890691
|
||||
P 6950 4300
|
||||
F 0 "R2" V 6743 4300 50 0000 C CNN
|
||||
F 1 "1k" V 6834 4300 50 0000 C CNN
|
||||
F 2 "" V 6880 4300 50 0000 C CNN
|
||||
F 3 "" H 6950 4300 50 0000 C CNN
|
||||
F 4 "Value" H 6950 4300 60 0001 C CNN "Fieldname"
|
||||
F 5 "1 2" H 6950 4300 60 0001 C CNN "SpiceMapping"
|
||||
F 6 "R" V 6950 4300 60 0001 C CNN "Spice_Primitive"
|
||||
1 6950 4300
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R1
|
||||
U 1 1 578906FF
|
||||
P 6400 4300
|
||||
F 0 "R1" V 6193 4300 50 0000 C CNN
|
||||
F 1 "1k" V 6284 4300 50 0000 C CNN
|
||||
F 2 "" V 6330 4300 50 0000 C CNN
|
||||
F 3 "" H 6400 4300 50 0000 C CNN
|
||||
F 4 "Value" H 6400 4300 60 0001 C CNN "Fieldname"
|
||||
F 5 "1 2" H 6400 4300 60 0001 C CNN "SpiceMapping"
|
||||
F 6 "R" V 6400 4300 60 0001 C CNN "Spice_Primitive"
|
||||
1 6400 4300
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L C C1
|
||||
U 1 1 5789077D
|
||||
P 7000 4950
|
||||
F 0 "C1" H 7115 4996 50 0000 L CNN
|
||||
F 1 "100n" H 7115 4905 50 0000 L CNN
|
||||
F 2 "" H 7038 4800 50 0000 C CNN
|
||||
F 3 "" H 7000 4950 50 0000 C CNN
|
||||
F 4 "Value" H 7000 4950 60 0001 C CNN "Fieldname"
|
||||
F 5 "C" H 7000 4950 60 0001 C CNN "Spice_Primitive"
|
||||
F 6 "1 2" H 7000 4950 60 0001 C CNN "SpiceMapping"
|
||||
1 7000 4950
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L C C2
|
||||
U 1 1 5789085B
|
||||
P 7350 4000
|
||||
F 0 "C2" H 7465 4046 50 0000 L CNN
|
||||
F 1 "100n" H 7465 3955 50 0000 L CNN
|
||||
F 2 "" H 7388 3850 50 0000 C CNN
|
||||
F 3 "" H 7350 4000 50 0000 C CNN
|
||||
F 4 "Value" H 7350 4000 60 0001 C CNN "Fieldname"
|
||||
F 5 "C" H 7350 4000 60 0001 C CNN "Spice_Primitive"
|
||||
F 6 "1 2" H 7350 4000 60 0001 C CNN "SpiceMapping"
|
||||
1 7350 4000
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L GND #PWR2
|
||||
U 1 1 57890B95
|
||||
P 7350 3800
|
||||
F 0 "#PWR2" H 7350 3550 50 0001 C CNN
|
||||
F 1 "GND" H 7355 3627 50 0000 C CNN
|
||||
F 2 "" H 7350 3800 50 0000 C CNN
|
||||
F 3 "" H 7350 3800 50 0000 C CNN
|
||||
1 7350 3800
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
9650 2100 9400 2100
|
||||
Wire Wire Line
|
||||
8150 4400 8900 4400
|
||||
Wire Wire Line
|
||||
8350 4400 8350 4950
|
||||
Wire Wire Line
|
||||
8350 4950 7400 4950
|
||||
Wire Wire Line
|
||||
7400 4950 7400 4500
|
||||
Wire Wire Line
|
||||
7400 4500 7550 4500
|
||||
Wire Wire Line
|
||||
7550 4300 7100 4300
|
||||
Wire Wire Line
|
||||
6550 4300 6850 4300
|
||||
Wire Wire Line
|
||||
6850 4950 6650 4950
|
||||
Wire Wire Line
|
||||
6650 4950 6650 4300
|
||||
Connection ~ 6800 4300
|
||||
Connection ~ 6650 4300
|
||||
Wire Wire Line
|
||||
7150 4950 7450 4950
|
||||
Connection ~ 7400 4950
|
||||
Wire Wire Line
|
||||
7350 4150 7350 4300
|
||||
Connection ~ 7350 4300
|
||||
Wire Wire Line
|
||||
7350 3800 7350 3850
|
||||
Wire Wire Line
|
||||
6250 4300 6000 4300
|
||||
Wire Wire Line
|
||||
6000 4300 6000 4500
|
||||
Wire Wire Line
|
||||
6000 4900 6000 5000
|
||||
$Comp
|
||||
L GND #PWR1
|
||||
U 1 1 57890E7F
|
||||
P 6000 5000
|
||||
F 0 "#PWR1" H 6000 4750 50 0001 C CNN
|
||||
F 1 "GND" H 6005 4827 50 0000 C CNN
|
||||
F 2 "" H 6000 5000 50 0000 C CNN
|
||||
F 3 "" H 6000 5000 50 0000 C CNN
|
||||
1 6000 5000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
8900 4400 8900 4450
|
||||
Connection ~ 8350 4400
|
||||
$EndSCHEMATC
|
||||
Loading…
Reference in New Issue