kicad/pcbnew/drc/drc_test_provider_lvs.cpp

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2004-2020 KiCad Developers.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <class_board.h>
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#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
#include <drc/drc_test_provider.h>
#include <kiway.h>
#include <netlist_reader/pcb_netlist.h>
/*
Layout-versus-schematic (LVS) test.
Errors generated:
- DRCE_MISSING_FOOTPRINT
- DRCE_DUPLICATE_FOOTPRINT
- DRCE_EXTRA_FOOTPRINT
TODO:
- cross-check PCB netlist against SCH netlist
- cross-check PCB fields against SCH fields
*/
class DRC_TEST_PROVIDER_LVS : public DRC_TEST_PROVIDER
{
public:
DRC_TEST_PROVIDER_LVS()
{
m_isRuleDriven = false;
}
virtual ~DRC_TEST_PROVIDER_LVS()
{
}
virtual bool Run() override;
virtual const wxString GetName() const override
{
return "LVS";
};
virtual const wxString GetDescription() const override
{
return "Performs layout-vs-schematics integity check";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
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int GetNumPhases() const override;
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private:
void testFootprints( NETLIST& aNetlist );
};
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void DRC_TEST_PROVIDER_LVS::testFootprints( NETLIST& aNetlist )
{
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BOARD* board = m_drcEngine->GetBoard();
auto compare = []( const MODULE* x, const MODULE* y )
{
return x->GetReference().CmpNoCase( y->GetReference() ) < 0;
};
auto mods = std::set<MODULE*, decltype( compare )>( compare );
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// Search for duplicate footprints on the board
for( MODULE* mod : board->Modules() )
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_DUPLICATE_FOOTPRINT ) )
break;
auto ins = mods.insert( mod );
if( !ins.second )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_DUPLICATE_FOOTPRINT );
drcItem->SetItems( mod, *ins.first );
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reportViolation( drcItem, mod->GetPosition());
}
}
// Search for component footprints in the netlist but not on the board.
for( unsigned ii = 0; ii < aNetlist.GetCount(); ii++ )
{
COMPONENT* component = aNetlist.GetComponent( ii );
MODULE* module = board->FindModuleByReference( component->GetReference() );
if( module == nullptr )
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_MISSING_FOOTPRINT ) )
break;
m_msg.Printf( _( "Missing footprint %s (%s)" ),
component->GetReference(),
component->GetValue() );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_MISSING_FOOTPRINT );
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drcItem->SetErrorMessage( m_msg );
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reportViolation( drcItem, wxPoint());
}
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else
{
for( D_PAD* pad : module->Pads() )
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_NET_CONFLICT ) )
break;
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const COMPONENT_NET& sch_net = component->GetNet( pad->GetName() );
const wxString& pcb_netname = pad->GetNetname();
if( !pcb_netname.IsEmpty() && sch_net.GetPinName().IsEmpty() )
{
m_msg.Printf( _( "No corresponding pin found in schematic." ) );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
drcItem->SetErrorMessage( m_msg );
drcItem->SetItems( pad );
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reportViolation( drcItem, module->GetPosition());
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}
else if( pcb_netname.IsEmpty() && !sch_net.GetNetName().IsEmpty() )
{
m_msg.Printf( _( "Pad missing net given by schematic (%s)." ),
sch_net.GetNetName() );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
drcItem->SetErrorMessage( m_msg );
drcItem->SetItems( pad );
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reportViolation( drcItem, module->GetPosition());
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}
else if( pcb_netname != sch_net.GetNetName() )
{
m_msg.Printf( _( "Pad net (%s) doesn't match net given by schematic (%s)." ),
pcb_netname,
sch_net.GetNetName() );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
drcItem->SetErrorMessage( m_msg );
drcItem->SetItems( pad );
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reportViolation( drcItem, module->GetPosition());
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}
}
for( unsigned jj = 0; jj < component->GetNetCount(); ++jj )
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_NET_CONFLICT ) )
break;
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const COMPONENT_NET& sch_net = component->GetNet( jj );
if( !module->FindPadByName( sch_net.GetPinName() ) )
{
m_msg.Printf( _( "No pad found for pin %s in schematic." ),
sch_net.GetPinName() );
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_NET_CONFLICT );
drcItem->SetErrorMessage( m_msg );
drcItem->SetItems( module );
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reportViolation( drcItem, module->GetPosition());
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}
}
}
}
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// Search for component footprints found on board but not in netlist.
for( MODULE* module : board->Modules() )
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_EXTRA_FOOTPRINT ) )
break;
if( !aNetlist.GetComponentByReference( module->GetReference() ) )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_EXTRA_FOOTPRINT );
drcItem->SetItems( module );
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reportViolation( drcItem, module->GetPosition());
}
}
}
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bool DRC_TEST_PROVIDER_LVS::Run()
{
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if( m_drcEngine->GetTestFootprints() )
{
if( !reportPhase( _( "Checking PCB to schematic parity..." ) ) )
return false;
auto netlist = m_drcEngine->GetSchematicNetlist();
if( !netlist )
{
reportAux( _("No netlist provided, skipping LVS.") );
return false;
}
testFootprints( *netlist );
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reportRuleStatistics();
}
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return true;
}
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int DRC_TEST_PROVIDER_LVS::GetNumPhases() const
{
return m_drcEngine->GetTestFootprints() ? 1 : 0;
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_LVS::GetConstraintTypes() const
{
return {};
}
namespace detail
{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_LVS> dummy;
}