2013-04-25 16:29:35 +00:00
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2009 Jean-Pierre Charras, jaen-pierre.charras@gipsa-lab.inpg.com
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* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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2011-09-23 20:00:30 +00:00
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/**
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* @file class_netinfo.h
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*/
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/*
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* Classes to handle info on nets
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*/
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#ifndef __CLASSES_NETINFO__
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#define __CLASSES_NETINFO__
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2011-09-24 18:33:28 +00:00
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2012-09-01 13:38:27 +00:00
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#include <gr_basic.h>
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2012-01-23 04:33:36 +00:00
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#include <class_netclass.h>
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2014-01-10 17:04:07 +00:00
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#include <boost/unordered_map.hpp>
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#include <hashtables.h>
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2011-09-23 20:00:30 +00:00
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2011-09-24 18:33:28 +00:00
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class wxDC;
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class wxPoint;
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2011-09-23 20:00:30 +00:00
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class LINE_READER;
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class EDA_DRAW_PANEL;
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class EDA_DRAW_FRAME;
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class NETINFO_ITEM;
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class D_PAD;
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class BOARD;
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class BOARD_ITEM;
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2013-01-12 17:32:24 +00:00
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class MSG_PANEL_ITEM;
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2011-09-23 20:00:30 +00:00
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/*****************************/
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/* flags for a RATSNEST_ITEM */
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/*****************************/
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#define CH_VISIBLE 1 /* Visible */
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#define CH_UNROUTABLE 2 /* Don't use autorouter. */
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#define CH_ROUTE_REQ 4 /* Must be routed by the autorouter. */
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#define CH_ACTIF 8 /* Not routed. */
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#define LOCAL_RATSNEST_ITEM 0x8000 /* Line between two pads of a single module. */
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2011-12-10 05:33:24 +00:00
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/**
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* Class RATSNEST_ITEM
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* describes a ratsnest line: a straight line connecting 2 pads
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*/
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2011-09-23 20:00:30 +00:00
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class RATSNEST_ITEM
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{
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private:
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int m_NetCode; // netcode ( = 1.. n , 0 is the value used for not connected items)
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public:
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int m_Status; // State: see previous defines (CH_ ...)
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D_PAD* m_PadStart; // pointer to the starting pad
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D_PAD* m_PadEnd; // pointer to ending pad
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int m_Lenght; // length of the line (used in some calculations)
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RATSNEST_ITEM();
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/**
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* Function GetNet
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* @return int - the net code.
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*/
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int GetNet() const
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{
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return m_NetCode;
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}
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void SetNet( int aNetCode )
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{
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m_NetCode = aNetCode;
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}
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2011-11-11 07:00:51 +00:00
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bool IsVisible()
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{
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return (m_Status & CH_VISIBLE) != 0;
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}
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bool IsActive()
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{
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return (m_Status & CH_ACTIF) != 0;
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}
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bool IsLocal()
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{
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return (m_Status & LOCAL_RATSNEST_ITEM) != 0;
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}
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2011-09-23 20:00:30 +00:00
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/**
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* Function Draw
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*/
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2012-09-01 13:38:27 +00:00
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void Draw( EDA_DRAW_PANEL* panel, wxDC* DC, GR_DRAWMODE aDrawMode,
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const wxPoint& offset );
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2011-09-23 20:00:30 +00:00
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};
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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class NETINFO_MAPPING
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{
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public:
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/**
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* Function SetBoard
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* Sets a BOARD object that is used to prepare the net code map.
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*/
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void SetBoard( const BOARD* aBoard )
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{
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m_board = aBoard;
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Update();
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}
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/**
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* Function Update
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* Prepares a mapping for net codes so they can be saved as consecutive numbers.
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* To retrieve a mapped net code, use translateNet() function after calling this.
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*/
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void Update();
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/**
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* Function Translate
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* Translates net number according to the map prepared by Update() function. It
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* allows to have items stored with consecutive net codes.
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* @param aNetCode is an old net code.
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* @return Net code that follows the mapping.
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*/
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int Translate( int aNetCode ) const;
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2014-03-11 13:50:53 +00:00
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#ifndef SWIG
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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///> Wrapper class, so you can iterate through NETINFO_ITEM*s, not
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///> std::pair<int/wxString, NETINFO_ITEM*>
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class iterator
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{
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public:
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iterator( std::map<int, int>::const_iterator aIter, const NETINFO_MAPPING* aMapping ) :
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m_iterator( aIter ), m_mapping( aMapping )
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{
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}
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/// pre-increment operator
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const iterator& operator++()
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{
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++m_iterator;
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return *this;
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}
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/// post-increment operator
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iterator operator++( int )
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{
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iterator ret = *this;
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++m_iterator;
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return ret;
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}
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NETINFO_ITEM* operator*() const;
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NETINFO_ITEM* operator->() const;
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bool operator!=( const iterator& aOther ) const
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{
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return m_iterator != aOther.m_iterator;
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}
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bool operator==( const iterator& aOther ) const
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{
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return m_iterator == aOther.m_iterator;
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}
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private:
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std::map<int, int>::const_iterator m_iterator;
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const NETINFO_MAPPING* m_mapping;
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};
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/**
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* Function begin()
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* Returns iterator to the first entry in the mapping.
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* NOTE: The entry is a pointer to the original NETINFO_ITEM object, this it contains
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* not mapped net code.
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*/
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iterator begin() const
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{
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return iterator( m_netMapping.begin(), this );
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}
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/**
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* Function end()
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* Returns iterator to the last entry in the mapping.
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* NOTE: The entry is a pointer to the original NETINFO_ITEM object, this it contains
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* not mapped net code.
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*/
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iterator end() const
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{
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return iterator( m_netMapping.end(), this );
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}
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2014-03-11 13:50:53 +00:00
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#endif
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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/**
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* Function GetSize
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* @return Number of mapped nets (i.e. not empty nets for a given BOARD object).
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*/
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int GetSize() const
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{
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return m_netMapping.size();
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}
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private:
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///> Board for which mapping is prepared
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const BOARD* m_board;
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///> Map that allows saving net codes with consecutive numbers (for compatibility reasons)
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std::map<int, int> m_netMapping;
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};
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2011-12-10 05:33:24 +00:00
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/**
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* Class NETINFO
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* is a container class for NETINFO_ITEM elements, which are the nets. That makes
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* this class a container for the nets.
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*/
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2011-09-23 20:00:30 +00:00
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class NETINFO_LIST
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{
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2011-12-10 05:33:24 +00:00
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friend class BOARD;
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2011-09-23 20:00:30 +00:00
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public:
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2011-12-10 05:33:24 +00:00
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NETINFO_LIST( BOARD* aParent );
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2011-09-23 20:00:30 +00:00
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~NETINFO_LIST();
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/**
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* Function GetItem
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2014-01-16 13:20:51 +00:00
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* @param aNetCode = netcode to identify a given NETINFO_ITEM
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* @return NETINFO_ITEM* - by \a aNetCode, or NULL if not found
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2011-09-23 20:00:30 +00:00
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*/
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2014-01-16 13:20:51 +00:00
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NETINFO_ITEM* GetNetItem( int aNetCode ) const
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2011-12-10 05:33:24 +00:00
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{
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2014-01-16 13:20:51 +00:00
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NETCODES_MAP::const_iterator result = m_netCodes.find( aNetCode );
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if( result != m_netCodes.end() )
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return (*result).second;
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return NULL;
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2011-12-10 05:33:24 +00:00
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}
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2011-09-23 20:00:30 +00:00
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2014-01-10 17:04:07 +00:00
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/**
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* Function GetItem
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* @param aNetName = net name to identify a given NETINFO_ITEM
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* @return NETINFO_ITEM* - by \a aNetName, or NULL if not found
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*/
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NETINFO_ITEM* GetNetItem( const wxString& aNetName ) const
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{
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NETNAMES_MAP::const_iterator result = m_netNames.find( aNetName );
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if( result != m_netNames.end() )
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return (*result).second;
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return NULL;
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}
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2011-09-23 20:00:30 +00:00
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/**
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2011-12-10 05:33:24 +00:00
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* Function GetNetCount
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2011-09-23 20:00:30 +00:00
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* @return the number of nets ( always >= 1 )
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2011-12-10 05:33:24 +00:00
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* because the first net is the "not connected" net and always exists
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2011-09-23 20:00:30 +00:00
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*/
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2014-01-16 13:20:51 +00:00
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unsigned GetNetCount() const { return m_netNames.size(); }
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2011-09-23 20:00:30 +00:00
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/**
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* Function Append
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* adds \a aNewElement to the end of the list.
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*/
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void AppendNet( NETINFO_ITEM* aNewElement );
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/**
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2011-12-10 05:33:24 +00:00
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* Function GetPadCount
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* @return the number of pads in board
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2011-09-23 20:00:30 +00:00
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*/
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2011-12-10 05:33:24 +00:00
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unsigned GetPadCount() const { return m_PadsFullList.size(); }
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2011-09-23 20:00:30 +00:00
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/**
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2011-12-10 05:33:24 +00:00
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* Function GetPads
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* returns a list of all the pads. The returned list is not
|
|
|
|
* sorted and contains pointers to PADS, but those pointers do not convey
|
|
|
|
* ownership of the respective PADs.
|
|
|
|
* @return std::vector<D_PAD*>& - a full list of pads
|
|
|
|
std::vector<D_PAD*>& GetPads()
|
2011-09-23 20:00:30 +00:00
|
|
|
{
|
2011-12-10 05:33:24 +00:00
|
|
|
return m_PadsFullList;
|
2011-09-23 20:00:30 +00:00
|
|
|
}
|
2011-12-10 05:33:24 +00:00
|
|
|
*/
|
2011-09-23 20:00:30 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetPad
|
|
|
|
* @return the pad idx from m_PadsFullList
|
|
|
|
*/
|
2011-12-10 05:33:24 +00:00
|
|
|
D_PAD* GetPad( unsigned aIdx ) const
|
2011-09-23 20:00:30 +00:00
|
|
|
{
|
|
|
|
if( aIdx < m_PadsFullList.size() )
|
|
|
|
return m_PadsFullList[aIdx];
|
|
|
|
else
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-01-15 08:34:16 +00:00
|
|
|
///> Constant that holds the unconnected net number
|
|
|
|
static const int UNCONNECTED;
|
|
|
|
|
BOARD_CONNECTED_ITEMs do not store net code anymore (m_NetCode field), instead net info is stored using a pointer to NETINFO_ITEM.
GetNet() refers to the net code stored in the NETINFO_ITEM. SetNet() finds an appropriate NETINFO_ITEM and uses it.
Removing GetNet() & SetNet() (and the whole net code idea) requires too many changes in the code (~250 references to the mentioned functions).
BOARD_CONNECTED_ITEMs by default get a pointer to NETINFO_ITEM that stores unconnected items. This requires for all BOARD_CONNECTED_ITEMs to have a parent (so BOARD* is accessible). The only orphaned item is BOARD_DESIGN_SETTINGS::m_Pad_Master, but it does not cause any issues so far.
Items that do not have access to a BOARD (do not have set parents) and therefore cannot get net assigned, by default get const static NETINFO_LIST::ORPHANED.
Performed tests:
- loaded .kicad_pcb, KiCad legacy board, Eagle 6.0 board, P-CAD board - all ok
- load a simple project, reload netlist after changing connections in eeschema - ok
- save & reload a board - ok, but still contain empty nets
- remove everything, restore with undo - ok
- remove everything, reload netlist - ok
- changing net names (all possibilites: empty->existing, empty->not existing, existing->empty, existing->not existing) - all ok
- zones: when net is changed to a net that does not have any nodes besides the zone itself, it does not get filled
2014-01-15 17:03:06 +00:00
|
|
|
///> NETINFO_ITEM meaning that there was no net assigned for an item, as there was no
|
|
|
|
///> board storing net list available.
|
2014-02-25 10:47:27 +00:00
|
|
|
static NETINFO_ITEM ORPHANED;
|
BOARD_CONNECTED_ITEMs do not store net code anymore (m_NetCode field), instead net info is stored using a pointer to NETINFO_ITEM.
GetNet() refers to the net code stored in the NETINFO_ITEM. SetNet() finds an appropriate NETINFO_ITEM and uses it.
Removing GetNet() & SetNet() (and the whole net code idea) requires too many changes in the code (~250 references to the mentioned functions).
BOARD_CONNECTED_ITEMs by default get a pointer to NETINFO_ITEM that stores unconnected items. This requires for all BOARD_CONNECTED_ITEMs to have a parent (so BOARD* is accessible). The only orphaned item is BOARD_DESIGN_SETTINGS::m_Pad_Master, but it does not cause any issues so far.
Items that do not have access to a BOARD (do not have set parents) and therefore cannot get net assigned, by default get const static NETINFO_LIST::ORPHANED.
Performed tests:
- loaded .kicad_pcb, KiCad legacy board, Eagle 6.0 board, P-CAD board - all ok
- load a simple project, reload netlist after changing connections in eeschema - ok
- save & reload a board - ok, but still contain empty nets
- remove everything, restore with undo - ok
- remove everything, reload netlist - ok
- changing net names (all possibilites: empty->existing, empty->not existing, existing->empty, existing->not existing) - all ok
- zones: when net is changed to a net that does not have any nodes besides the zone itself, it does not get filled
2014-01-15 17:03:06 +00:00
|
|
|
|
2013-03-14 22:54:47 +00:00
|
|
|
#if defined(DEBUG)
|
|
|
|
void Show() const;
|
|
|
|
#endif
|
|
|
|
|
2014-01-10 17:04:07 +00:00
|
|
|
typedef boost::unordered_map<const wxString, NETINFO_ITEM*, WXSTRING_HASH> NETNAMES_MAP;
|
2014-01-16 13:20:51 +00:00
|
|
|
typedef boost::unordered_map<const int, NETINFO_ITEM*> NETCODES_MAP;
|
2014-01-10 17:04:07 +00:00
|
|
|
|
2014-03-11 13:50:53 +00:00
|
|
|
#ifndef SWIG
|
2014-01-16 15:47:31 +00:00
|
|
|
///> Wrapper class, so you can iterate through NETINFO_ITEM*s, not
|
|
|
|
///> std::pair<int/wxString, NETINFO_ITEM*>
|
|
|
|
class iterator
|
|
|
|
{
|
|
|
|
public:
|
|
|
|
iterator( NETNAMES_MAP::const_iterator aIter ) : m_iterator( aIter )
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
/// pre-increment operator
|
|
|
|
const iterator& operator++()
|
|
|
|
{
|
|
|
|
++m_iterator;
|
|
|
|
|
|
|
|
return *this;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// post-increment operator
|
|
|
|
iterator operator++( int )
|
|
|
|
{
|
|
|
|
iterator ret = *this;
|
|
|
|
++m_iterator;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
NETINFO_ITEM* operator*() const
|
|
|
|
{
|
|
|
|
return m_iterator->second;
|
|
|
|
}
|
|
|
|
|
|
|
|
NETINFO_ITEM* operator->() const
|
|
|
|
{
|
|
|
|
return m_iterator->second;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool operator!=( const iterator& aOther ) const
|
|
|
|
{
|
|
|
|
return m_iterator != aOther.m_iterator;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool operator==( const iterator& aOther ) const
|
|
|
|
{
|
|
|
|
return m_iterator == aOther.m_iterator;
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
NETNAMES_MAP::const_iterator m_iterator;
|
|
|
|
};
|
|
|
|
|
|
|
|
iterator begin() const
|
|
|
|
{
|
|
|
|
return iterator( m_netNames.begin() );
|
|
|
|
}
|
|
|
|
|
|
|
|
iterator end() const
|
|
|
|
{
|
|
|
|
return iterator( m_netNames.end() );
|
|
|
|
}
|
2014-03-11 13:50:53 +00:00
|
|
|
#endif
|
2014-01-16 15:47:31 +00:00
|
|
|
|
2011-09-23 20:00:30 +00:00
|
|
|
private:
|
|
|
|
/**
|
2011-12-10 05:33:24 +00:00
|
|
|
* Function DeleteData
|
|
|
|
* deletes the list of nets (and free memory)
|
|
|
|
*/
|
|
|
|
void clear();
|
|
|
|
|
|
|
|
/**
|
2013-08-24 08:08:55 +00:00
|
|
|
* Function buildListOfNets
|
2011-12-10 05:33:24 +00:00
|
|
|
* builds or rebuilds the list of NETINFO_ITEMs
|
|
|
|
* The list is sorted by names.
|
|
|
|
*/
|
|
|
|
void buildListOfNets();
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function buildPadsFullList
|
|
|
|
* creates the pad list, and initializes:
|
2011-09-23 20:00:30 +00:00
|
|
|
* m_Pads (list of pads)
|
|
|
|
* set m_Status_Pcb = LISTE_PAD_OK;
|
|
|
|
* and clear for all pads in list the m_SubRatsnest member;
|
|
|
|
* clear m_Pcb->m_FullRatsnest
|
|
|
|
*/
|
2011-12-10 05:33:24 +00:00
|
|
|
void buildPadsFullList();
|
|
|
|
|
2014-01-16 13:20:51 +00:00
|
|
|
/**
|
|
|
|
* Function getFreeNetCode
|
|
|
|
* returns the first available net code that is not used by any other net.
|
|
|
|
*/
|
|
|
|
int getFreeNetCode() const;
|
|
|
|
|
Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
|
|
|
BOARD* m_Parent;
|
2014-01-16 13:20:51 +00:00
|
|
|
|
2014-01-10 17:04:07 +00:00
|
|
|
NETNAMES_MAP m_netNames; ///< map for a fast look up by net names
|
2014-01-16 13:20:51 +00:00
|
|
|
NETCODES_MAP m_netCodes; ///< map for a fast look up by net codes
|
|
|
|
|
Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
|
|
|
std::vector<D_PAD*> m_PadsFullList; ///< contains all pads, sorted by pad's netname.
|
2011-12-10 05:33:24 +00:00
|
|
|
///< can be used in ratsnest calculations.
|
2011-09-23 20:00:30 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Class NETINFO_ITEM
|
|
|
|
* handles the data for a net
|
|
|
|
*/
|
|
|
|
class NETINFO_ITEM
|
|
|
|
{
|
2014-01-16 13:20:51 +00:00
|
|
|
friend class NETINFO_LIST;
|
|
|
|
|
2011-09-23 20:00:30 +00:00
|
|
|
private:
|
2014-03-11 13:50:53 +00:00
|
|
|
int m_NetCode; ///< A number equivalent to the net name.
|
2011-12-10 05:33:24 +00:00
|
|
|
///< Used for fast comparisons in ratsnest and DRC computations.
|
2011-09-23 20:00:30 +00:00
|
|
|
|
2014-03-11 13:50:53 +00:00
|
|
|
wxString m_Netname; ///< Full net name like /mysheet/mysubsheet/vout used by Eeschema
|
2011-09-23 20:00:30 +00:00
|
|
|
|
2014-03-11 13:50:53 +00:00
|
|
|
wxString m_ShortNetname; ///< short net name, like vout from /mysheet/mysubsheet/vout
|
2011-09-23 20:00:30 +00:00
|
|
|
|
|
|
|
wxString m_NetClassName; // Net Class name. if void this is equivalent
|
|
|
|
// to "default" (the first
|
|
|
|
// item of the net classes list
|
|
|
|
NETCLASS* m_NetClass;
|
|
|
|
|
2013-01-12 17:32:24 +00:00
|
|
|
BOARD_ITEM* m_parent; ///< The parent board item object the net belongs to.
|
2011-09-23 20:00:30 +00:00
|
|
|
|
|
|
|
public:
|
2014-03-11 13:50:53 +00:00
|
|
|
std::vector<D_PAD*> m_PadInNetList; ///< List of pads connected to this net
|
2011-09-23 20:00:30 +00:00
|
|
|
|
|
|
|
unsigned m_RatsnestStartIdx; /* Starting point of ratsnests of this
|
|
|
|
* net (included) in a general buffer of
|
|
|
|
* ratsnest (a vector<RATSNEST_ITEM*>
|
|
|
|
* buffer) */
|
|
|
|
|
|
|
|
unsigned m_RatsnestEndIdx; // Ending point of ratsnests of this net
|
|
|
|
// (excluded) in this buffer
|
|
|
|
|
2014-01-16 13:20:51 +00:00
|
|
|
NETINFO_ITEM( BOARD_ITEM* aParent, const wxString& aNetName = wxEmptyString, int aNetCode = -1 );
|
2011-09-23 20:00:30 +00:00
|
|
|
~NETINFO_ITEM();
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function SetClass
|
|
|
|
* sets \a aNetclass into this NET
|
|
|
|
*/
|
|
|
|
void SetClass( const NETCLASS* aNetClass )
|
|
|
|
{
|
|
|
|
m_NetClass = (NETCLASS*) aNetClass;
|
|
|
|
|
|
|
|
if( aNetClass )
|
|
|
|
m_NetClassName = aNetClass->GetName();
|
|
|
|
else
|
|
|
|
m_NetClassName = NETCLASS::Default;
|
|
|
|
}
|
|
|
|
|
|
|
|
NETCLASS* GetNetClass()
|
|
|
|
{
|
|
|
|
return m_NetClass;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetClassName
|
|
|
|
* returns the class name
|
|
|
|
*/
|
|
|
|
const wxString& GetClassName() const
|
|
|
|
{
|
|
|
|
return m_NetClassName;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 1
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetTrackWidth
|
|
|
|
* returns the width of tracks used to route this net.
|
|
|
|
*/
|
|
|
|
int GetTrackWidth()
|
|
|
|
{
|
|
|
|
wxASSERT( m_NetClass );
|
|
|
|
return m_NetClass->GetTrackWidth();
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetViaSize
|
|
|
|
* returns the size of vias used to route this net
|
|
|
|
*/
|
|
|
|
int GetViaSize()
|
|
|
|
{
|
|
|
|
wxASSERT( m_NetClass );
|
|
|
|
return m_NetClass->GetViaDiameter();
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetMicroViaSize
|
|
|
|
* returns the size of vias used to route this net
|
|
|
|
*/
|
|
|
|
int GetMicroViaSize()
|
|
|
|
{
|
|
|
|
wxASSERT( m_NetClass );
|
|
|
|
return m_NetClass->GetuViaDiameter();
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetViaDrillSize
|
|
|
|
* returns the size of via drills used to route this net
|
|
|
|
*/
|
|
|
|
int GetViaDrillSize()
|
|
|
|
{
|
|
|
|
wxASSERT( m_NetClass );
|
|
|
|
return m_NetClass->GetViaDrill();
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetViaDrillSize
|
|
|
|
* returns the size of via drills used to route this net
|
|
|
|
*/
|
|
|
|
int GetMicroViaDrillSize()
|
|
|
|
{
|
|
|
|
wxASSERT( m_NetClass );
|
|
|
|
return m_NetClass->GetuViaDrill();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetViaMinSize
|
|
|
|
* returns the Minimum value for via sizes (used in DRC)
|
|
|
|
*/
|
|
|
|
int GetViaMinSize()
|
|
|
|
{
|
|
|
|
wxASSERT( m_NetClass );
|
|
|
|
return m_NetClass->GetViaMinSize();
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetClearance
|
|
|
|
* returns the clearance when routing near aBoardItem
|
|
|
|
*/
|
|
|
|
int GetClearance( BOARD_ITEM* aBoardItem )
|
|
|
|
{
|
|
|
|
wxASSERT( m_NetClass );
|
|
|
|
return m_NetClass->GetClearance();
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function Draw
|
|
|
|
* @todo we actually could show a NET, simply show all the tracks and
|
|
|
|
* a pads or net name on pad and vias
|
|
|
|
*/
|
2012-09-01 13:38:27 +00:00
|
|
|
void Draw( EDA_DRAW_PANEL* panel, wxDC* DC, GR_DRAWMODE aDrawMode,
|
|
|
|
const wxPoint& offset );
|
2011-09-23 20:00:30 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Function GetNet
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* @return int - the netcode
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*/
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int GetNet() const { return m_NetCode; }
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2014-01-09 14:51:47 +00:00
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/**
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* Function GetNodesCount
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* @return int - number of nodes in the net
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*/
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2011-12-17 21:21:03 +00:00
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int GetNodesCount() const { return m_PadInNetList.size(); }
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2011-09-23 20:00:30 +00:00
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/**
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* Function GetNetname
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2014-01-10 17:04:07 +00:00
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* @return const wxString&, a reference to the full netname
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2011-09-23 20:00:30 +00:00
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*/
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2014-01-10 17:04:07 +00:00
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const wxString& GetNetname() const { return m_Netname; }
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2011-09-23 20:00:30 +00:00
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/**
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* Function GetShortNetname
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2014-01-10 17:04:07 +00:00
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* @return const wxString &, a reference to the short netname
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2011-09-23 20:00:30 +00:00
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*/
|
2014-01-10 17:04:07 +00:00
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const wxString& GetShortNetname() const { return m_ShortNetname; }
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2011-09-23 20:00:30 +00:00
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2013-04-25 16:29:35 +00:00
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/**
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* Function GetMsgPanelInfo
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* returns the information about the #NETINFO_ITEM in \a aList to display in the
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* message panel.
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*
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* @param aList is the list in which to place the status information.
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*/
|
2013-01-12 17:32:24 +00:00
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void GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList );
|
2014-01-09 14:51:47 +00:00
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/**
|
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|
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* Function Clear
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* sets all fields to their defaults values.
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*/
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void Clear()
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{
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m_PadInNetList.clear();
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m_RatsnestStartIdx = 0; // Starting point of ratsnests of this net in a
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// general buffer of ratsnest
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m_RatsnestEndIdx = 0; // Ending point of ratsnests of this net
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|
SetClass( NULL );
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|
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}
|
2011-09-23 20:00:30 +00:00
|
|
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};
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|
|
/***********************************************************/
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|
|
|
/* Description of a trace point for monitoring connections */
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|
|
|
/***********************************************************/
|
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|
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#define START_ON_PAD 0x10
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|
|
#define END_ON_PAD 0x20
|
|
|
|
#define START_ON_TRACK 0x40
|
|
|
|
#define END_ON_TRACK 0x80
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|
|
|
|
|
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|
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|
|
|
/* Status bit (OR'ed bits) for class BOARD member .m_Status_Pcb */
|
|
|
|
enum StatusPcbFlags {
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|
|
LISTE_PAD_OK = 1, /* Pad list is Ok */
|
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|
|
LISTE_RATSNEST_ITEM_OK = 2, /* General Ratsnest is Ok */
|
|
|
|
RATSNEST_ITEM_LOCAL_OK = 4, /* current MODULE ratsnest is Ok */
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|
|
CONNEXION_OK = 8, /* List of connections exists. */
|
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|
|
NET_CODES_OK = 0x10, /* Bit indicating that Netcode is OK,
|
|
|
|
* do not change net name. */
|
|
|
|
DO_NOT_SHOW_GENERAL_RASTNEST = 0x20 /* Do not display the general
|
|
|
|
* ratsnest (used in module moves) */
|
|
|
|
};
|
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|
#endif // __CLASSES_NETINFO__
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