kicad/pcbnew/editrack-part2.cpp

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2015 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
* Copyright (C) 2012 Wayne Stambaugh <stambaughw@verizon.net>
* Copyright (C) 1992-2015 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
/**
* @file editrack-part2.cpp
*/
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#include <fctsys.h>
#include <gr_basic.h>
#include <class_drawpanel.h>
#include <confirm.h>
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#include <pcb_edit_frame.h>
#include <class_board.h>
#include <class_module.h>
#include <class_track.h>
#include <class_marker_pcb.h>
#include <pcbnew.h>
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#include <drc.h>
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#include <connectivity_data.h>
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bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
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{
unsigned itmp;
if( aTrack == NULL )
{
if( GetActiveLayer() != GetScreen()->m_Route_Layer_TOP )
SetActiveLayer( GetScreen()->m_Route_Layer_TOP );
else
SetActiveLayer( GetScreen()->m_Route_Layer_BOTTOM );
UpdateStatusBar();
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return true;
}
// Avoid more than one via on the current location:
if( GetBoard()->GetViaByPosition( g_CurrentTrackSegment->GetEnd(),
g_CurrentTrackSegment->GetLayer() ) )
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return false;
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for( TRACK* segm = g_FirstTrackSegment; segm; segm = segm->Next() )
{
if( segm->Type() == PCB_VIA_T && g_CurrentTrackSegment->GetEnd() == segm->GetStart() )
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return false;
}
// Is the current segment Ok (no DRC error) ?
if( Settings().m_legacyDrcOn )
{
if( BAD_DRC==m_drc->Drc( g_CurrentTrackSegment, GetBoard()->m_Track ) )
// DRC error, the change layer is not made
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return false;
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// Handle 2 segments.
if( Settings().m_legacyUseTwoSegmentTracks && g_CurrentTrackSegment->Back() )
{
if( BAD_DRC == m_drc->Drc( g_CurrentTrackSegment->Back(), GetBoard()->m_Track ) )
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return false;
}
}
/* Save current state before placing a via.
* If the via cannot be placed this current state will be reused
*/
itmp = g_CurrentTrackList.GetCount();
Begin_Route( g_CurrentTrackSegment, DC );
m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
// create the via
VIA* via = new VIA( GetBoard() );
via->SetFlags( IS_NEW );
via->SetViaType( GetDesignSettings().m_CurrentViaType );
via->SetNetCode( GetBoard()->GetHighLightNetCode() );
via->SetPosition( g_CurrentTrackSegment->GetEnd() );
// for microvias, the size and hole will be changed later.
via->SetWidth( GetDesignSettings().GetCurrentViaSize());
via->SetDrill( GetDesignSettings().GetCurrentViaDrill() );
// Usual via is from copper to component.
// layer pair is B_Cu and F_Cu.
via->SetLayerPair( B_Cu, F_Cu );
PCB_LAYER_ID first_layer = GetActiveLayer();
PCB_LAYER_ID last_layer;
// prepare switch to new active layer:
if( first_layer != GetScreen()->m_Route_Layer_TOP )
last_layer = GetScreen()->m_Route_Layer_TOP;
else
last_layer = GetScreen()->m_Route_Layer_BOTTOM;
// Adjust the actual via layer pair
switch( via->GetViaType() )
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{
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case VIA_BLIND_BURIED:
via->SetLayerPair( first_layer, last_layer );
break;
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case VIA_MICROVIA: // from external to the near neighbor inner layer
{
PCB_LAYER_ID last_inner_layer = ToLAYER_ID( ( GetBoard()->GetCopperLayerCount() - 2 ) );
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if( first_layer == B_Cu )
last_layer = last_inner_layer;
else if( first_layer == F_Cu )
last_layer = In1_Cu;
else if( first_layer == last_inner_layer )
last_layer = B_Cu;
else if( first_layer == In1_Cu )
last_layer = F_Cu;
// else error: will be removed later
via->SetLayerPair( first_layer, last_layer );
// Update diameter and hole size, which where set previously
// for normal vias
NETINFO_ITEM* net = via->GetNet();
via->SetWidth( net->GetMicroViaSize() );
via->SetDrill( net->GetMicroViaDrillSize() );
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}
break;
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default:
break;
}
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if( Settings().m_legacyDrcOn && BAD_DRC == m_drc->Drc( via, GetBoard()->m_Track ) )
{
// DRC fault: the Via cannot be placed here ...
delete via;
m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
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// delete the track(s) added in Begin_Route()
while( g_CurrentTrackList.GetCount() > itmp )
{
Delete_Segment( DC, g_CurrentTrackSegment );
}
SetCurItem( g_CurrentTrackSegment, false );
// Refresh DRC diag, erased by previous calls
if( m_drc->GetCurrentMarker() )
SetMsgPanel( m_drc->GetCurrentMarker() );
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return false;
}
SetActiveLayer( last_layer );
TRACK* lastNonVia = g_CurrentTrackSegment;
/* A new via was created. It was Ok.
*/
g_CurrentTrackList.PushBack( via );
/* The via is now in linked list and we need a new track segment
* after the via, starting at via location.
* it will become the new current segment (from via to the mouse cursor)
*/
TRACK* track = (TRACK*)lastNonVia->Clone();
/* the above creates a new segment from the last entered segment, with the
* current width, flags, netcode, etc... values.
* layer, start and end point are not correct,
* and will be modified next
*/
// set the layer to the new value
track->SetLayer( GetActiveLayer() );
/* the start point is the via position and the end point is the cursor
* which also is on the via (will change when moving mouse)
*/
track->SetEnd( via->GetStart() );
track->SetStart( via->GetStart() );
g_CurrentTrackList.PushBack( track );
if( Settings().m_legacyUseTwoSegmentTracks )
{
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// Create a second segment (we must have 2 track segments to adjust)
g_CurrentTrackList.PushBack( (TRACK*)g_CurrentTrackSegment->Clone() );
}
m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
SetMsgPanel( via );
UpdateStatusBar();
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return true;
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}
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static void ListSetState( EDA_ITEM* Start, int NbItem, STATUS_FLAGS State,
bool onoff );
void DrawTraces( EDA_DRAW_PANEL* panel, wxDC* DC, TRACK* aTrackList, int nbsegment,
GR_DRAWMODE draw_mode )
{
// preserve the start of the list for debugging.
for( TRACK* track = aTrackList; nbsegment > 0 && track; nbsegment--, track = track->Next() )
{
track->Draw( panel, DC, draw_mode );
}
}
/*
* This function try to remove an old track, when a new track is created,
* and the old track is no more needed
*/
int PCB_EDIT_FRAME::EraseRedundantTrack( wxDC* aDC,
TRACK* aNewTrack,
int aNewTrackSegmentsCount,
PICKED_ITEMS_LIST* aItemsListPicker )
{
TRACK* StartTrack, * EndTrack;
TRACK* pt_segm;
TRACK* pt_del;
int ii, jj, nb_segm, nbconnect;
wxPoint start;
wxPoint end;
LSET startmasklayer, endmasklayer;
int netcode = aNewTrack->GetNetCode();
/* Reconstruct the complete track (the new track has to start on a segment of track).
*/
ListSetState( aNewTrack, aNewTrackSegmentsCount, BUSY, false );
/* If the new track begins with a via, complete the track segment using
* the following segment as a reference because a via is often a hub of
* segments, and does not characterize track.
*/
if( aNewTrack->Type() == PCB_VIA_T && ( aNewTrackSegmentsCount > 1 ) )
aNewTrack = aNewTrack->Next();
aNewTrack = GetBoard()->MarkTrace( aNewTrack, &aNewTrackSegmentsCount, NULL, NULL, true );
wxASSERT( aNewTrack );
#if 0 && defined(DEBUG)
TRACK* EndNewTrack; // The last segment of the list chained to the track
EndNewTrack = aNewTrack;
for( ii = 1; ii < aNewTrackSegmentsCount; ii++ )
{
wxASSERT( EndNewTrack->GetState( -1 ) != 0 );
D( printf( "track %p is newly part of net %d\n", EndNewTrack, netcode ); )
EndNewTrack = EndNewTrack->Next();
}
wxASSERT( EndNewTrack->GetState( -1 ) != 0 );
D( printf( "track %p is newly part of net %d\n", EndNewTrack, netcode ); )
for( TRACK* track = m_Pcb->m_Track; track; track = track->Next() )
track->Show( 0, std::cout );
#endif
TRACK* bufStart = m_Pcb->m_Track->GetStartNetCode( netcode ); // Beginning of tracks of the net
TRACK* bufEnd = bufStart->GetEndNetCode( netcode ); // End of tracks of the net
// Flags for cleaning the net.
for( pt_del = bufStart; pt_del; pt_del = pt_del->Next() )
{
// D( std::cout<<"track "<<pt_del<<" turning off BUSY | IN_EDIT | IS_LINKED"<<std::endl; )
pt_del->SetState( BUSY | IN_EDIT | IS_LINKED, false );
if( pt_del == bufEnd ) // Last segment reached
break;
}
if( aNewTrack->GetEndSegments( aNewTrackSegmentsCount, &StartTrack, &EndTrack ) == 0 )
return 0;
if( ( StartTrack == NULL ) || ( EndTrack == NULL ) )
return 0;
start = StartTrack->GetStart();
end = EndTrack->GetEnd();
// The start and end points cannot be the same.
if( start == end )
return 0;
// Determine layers interconnected these points.
startmasklayer = StartTrack->GetLayerSet();
endmasklayer = EndTrack->GetLayerSet();
// There may be a via or a pad on the end points.
pt_segm = m_Pcb->m_Track->GetVia( NULL, start, startmasklayer );
if( pt_segm )
startmasklayer |= pt_segm->GetLayerSet();
if( StartTrack->start && ( StartTrack->start->Type() == PCB_PAD_T ) )
{
// Start on pad.
D_PAD* pad = (D_PAD*) StartTrack->start;
startmasklayer |= pad->GetLayerSet();
}
pt_segm = m_Pcb->m_Track->GetVia( NULL, end, endmasklayer );
if( pt_segm )
endmasklayer |= pt_segm->GetLayerSet();
if( EndTrack->end && ( EndTrack->end->Type() == PCB_PAD_T ) )
{
D_PAD* pad = (D_PAD*) EndTrack->end;
endmasklayer |= pad->GetLayerSet();
}
// Mark as deleted a new track (which is not involved in the search for other connections)
ListSetState( aNewTrack, aNewTrackSegmentsCount, IS_DELETED, true );
/* A segment must be connected to the starting point, otherwise
* it is unnecessary to analyze the other point
*/
pt_segm = GetTrack( bufStart, bufEnd, start, startmasklayer );
if( pt_segm == NULL ) // Not connected to the track starting point.
{
// Clear the delete flag.
ListSetState( aNewTrack, aNewTrackSegmentsCount, IS_DELETED, false );
return 0;
}
/* Marking a list of candidate segmented connect to endpoint
* Note: the vias are not taken into account because they do
* not define a track, since they are on an intersection.
*/
for( pt_del = bufStart, nbconnect = 0; ; )
{
pt_segm = GetTrack( pt_del, bufEnd, end, endmasklayer );
if( pt_segm == NULL )
break;
if( pt_segm->Type() != PCB_VIA_T )
{
if( pt_segm->GetState( IS_LINKED ) == 0 )
{
pt_segm->SetState( IS_LINKED, true );
nbconnect++;
}
}
if( pt_del == bufEnd )
break;
pt_del = pt_segm->Next();
}
if( nbconnect == 0 )
{
// Clear used flags
for( pt_del = bufStart; pt_del; pt_del = pt_del->Next() )
{
pt_del->SetState( BUSY | IS_DELETED | IN_EDIT | IS_LINKED, false );
if( pt_del == bufEnd ) // Last segment reached
break;
}
return 0;
}
// Mark trace as edited (which does not involve searching for other tracks)
ListSetState( aNewTrack, aNewTrackSegmentsCount, IS_DELETED, false );
ListSetState( aNewTrack, aNewTrackSegmentsCount, IN_EDIT, true );
// Test all marked segments.
while( nbconnect )
{
for( pt_del = bufStart; pt_del; pt_del = pt_del->Next() )
{
if( pt_del->GetState( IS_LINKED ) )
break;
if( pt_del == bufEnd ) // Last segment reached
break;
}
nbconnect--;
if( pt_del )
pt_del->SetState( IS_LINKED, false );
pt_del = GetBoard()->MarkTrace( pt_del, &nb_segm, NULL, NULL, true );
/* Test if the marked track is redundant, i.e. if one of marked segments
* is connected to the starting point of the new track.
*/
ii = 0;
pt_segm = pt_del;
for( ; pt_segm && (ii < nb_segm); pt_segm = pt_segm->Next(), ii++ )
{
if( pt_segm->GetState( BUSY ) == 0 )
break;
if( pt_segm->GetStart() == start || pt_segm->GetEnd() == start )
{
// Marked track can be erased.
TRACK* NextS;
DrawTraces( m_canvas, aDC, pt_del, nb_segm, GR_XOR | GR_HIGHLIGHT );
for( jj = 0; jj < nb_segm; jj++, pt_del = NextS )
{
NextS = pt_del->Next();
if( aItemsListPicker )
{
pt_del->UnLink();
pt_del->SetStatus( 0 );
pt_del->ClearFlags();
GetBoard()->GetConnectivity()->Remove( pt_del );
ITEM_PICKER picker( pt_del, UR_DELETED );
aItemsListPicker->PushItem( picker );
}
else
{
GetBoard()->GetConnectivity()->Remove( pt_del );
pt_del->DeleteStructure();
}
}
// Clean up flags.
for( pt_del = m_Pcb->m_Track; pt_del != NULL; pt_del = pt_del->Next() )
{
if( pt_del->GetState( IN_EDIT ) )
{
pt_del->SetState( IN_EDIT, false );
if( aDC )
pt_del->Draw( m_canvas, aDC, GR_OR );
}
pt_del->SetState( IN_EDIT | IS_LINKED, false );
}
return 1;
}
}
// Clear BUSY flag here because the track did not get marked.
ListSetState( pt_del, nb_segm, BUSY, false );
}
// Clear used flags
for( pt_del = m_Pcb->m_Track; pt_del; pt_del = pt_del->Next() )
{
pt_del->SetState( BUSY | IS_DELETED | IN_EDIT | IS_LINKED, false );
if( pt_del == bufEnd ) // Last segment reached
break;
}
return 0;
}
/* Set the bits of .m_State member to on/off value, using bit mask State
* of a list of EDA_ITEM
*/
static void ListSetState( EDA_ITEM* Start, int NbItem, STATUS_FLAGS State,
bool onoff )
{
for( ; (Start != NULL ) && ( NbItem > 0 ); NbItem--, Start = Start->Next() )
{
Start->SetState( State, onoff );
}
}