2021-08-08 13:37:14 +00:00
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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2022-03-11 21:16:52 +00:00
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* Copyright (C) 2021-2022 KiCad Developers.
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2021-08-08 13:37:14 +00:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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2021-08-09 10:10:09 +00:00
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#include <board.h>
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#include <board_design_settings.h>
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#include <connectivity/connectivity_data.h>
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#include <zone.h>
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#include <footprint.h>
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#include <pad.h>
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#include <pcb_track.h>
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2022-06-15 00:41:10 +00:00
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#include <thread_pool.h>
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2021-08-09 10:10:09 +00:00
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#include <geometry/shape_line_chain.h>
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#include <geometry/shape_poly_set.h>
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2021-08-08 13:37:14 +00:00
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#include <drc/drc_rule.h>
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2021-12-01 14:42:44 +00:00
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#include <drc/drc_item.h>
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2021-08-08 13:37:14 +00:00
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#include <drc/drc_test_provider.h>
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/*
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2021-08-09 10:10:09 +00:00
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This loads some rule resolvers for the ZONE_FILLER, and checks that pad thermal relief
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connections have at least the required number of spokes.
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Errors generated:
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- DRCE_STARVED_THERMAL
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2021-08-08 13:37:14 +00:00
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*/
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class DRC_TEST_PROVIDER_ZONE_CONNECTIONS : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_ZONE_CONNECTIONS()
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{
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}
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virtual ~DRC_TEST_PROVIDER_ZONE_CONNECTIONS()
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{
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}
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2021-08-09 10:10:09 +00:00
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virtual bool Run() override;
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2021-08-08 13:37:14 +00:00
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virtual const wxString GetName() const override
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{
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2022-03-11 21:16:52 +00:00
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return wxT( "zone connections" );
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2021-08-08 13:37:14 +00:00
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};
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virtual const wxString GetDescription() const override
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{
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2022-03-11 21:16:52 +00:00
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return wxT( "Checks thermal reliefs for a sufficient number of connecting spokes" );
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2021-08-08 13:37:14 +00:00
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}
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2022-06-18 18:47:11 +00:00
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private:
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void testZoneLayer( ZONE* aZone, PCB_LAYER_ID aLayer );
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2021-08-08 13:37:14 +00:00
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};
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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void DRC_TEST_PROVIDER_ZONE_CONNECTIONS::testZoneLayer( ZONE* aZone, PCB_LAYER_ID aLayer )
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{
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2021-08-09 10:10:09 +00:00
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BOARD* board = m_drcEngine->GetBoard();
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BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
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std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->GetConnectivity();
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DRC_CONSTRAINT constraint;
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2022-06-18 18:47:11 +00:00
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const std::shared_ptr<SHAPE_POLY_SET>& zoneFill = aZone->GetFilledPolysList( aLayer );
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2021-08-09 10:10:09 +00:00
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for( FOOTPRINT* footprint : board->Footprints() )
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{
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2022-06-18 18:47:11 +00:00
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for( PAD* pad : footprint->Pads() )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_STARVED_THERMAL ) )
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return;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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if( m_drcEngine->IsCancelled() )
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return;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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// Quick tests for "connected":
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//
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if( !pad->FlashLayer( aLayer ) )
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continue;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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if( pad->GetNetCode() != aZone->GetNetCode() || pad->GetNetCode() <= 0 )
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continue;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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EDA_RECT item_boundingbox = pad->GetBoundingBox();
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2022-03-11 20:13:47 +00:00
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2022-06-18 18:47:11 +00:00
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if( !item_boundingbox.Intersects( aZone->GetCachedBoundingBox() ) )
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continue;
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2022-02-07 20:39:39 +00:00
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2022-06-18 18:47:11 +00:00
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// If those passed, do a thorough test:
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//
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constraint = bds.m_DRCEngine->EvalZoneConnection( pad, aZone, aLayer );
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ZONE_CONNECTION conn = constraint.m_ZoneConnection;
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2022-06-18 18:47:11 +00:00
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if( conn != ZONE_CONNECTION::THERMAL )
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continue;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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constraint = bds.m_DRCEngine->EvalRules( MIN_RESOLVED_SPOKES_CONSTRAINT, pad, aZone,
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aLayer );
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int minCount = constraint.m_Value.Min();
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || minCount <= 0 )
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continue;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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SHAPE_POLY_SET padPoly;
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pad->TransformShapeWithClearanceToPolygon( padPoly, aLayer, 0, ARC_LOW_DEF,
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ERROR_OUTSIDE );
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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SHAPE_LINE_CHAIN& padOutline = padPoly.Outline( 0 );
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std::vector<SHAPE_LINE_CHAIN::INTERSECTION> intersections;
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int spokes = 0;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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for( int jj = 0; jj < zoneFill->OutlineCount(); ++jj )
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padOutline.Intersect( zoneFill->Outline( jj ), intersections, true );
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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spokes += intersections.size() / 2;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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if( spokes <= 0 )
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continue;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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// Now we know we're connected, so see if there are any other manual spokes
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// added:
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//
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for( PCB_TRACK* track : connectivity->GetConnectedTracks( pad ) )
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{
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if( padOutline.PointInside( track->GetStart() ) )
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{
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if( aZone->GetFilledPolysList( aLayer )->Collide( track->GetEnd() ) )
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spokes++;
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}
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else if( padOutline.PointInside( track->GetEnd() ) )
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{
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if( aZone->GetFilledPolysList( aLayer )->Collide( track->GetStart() ) )
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spokes++;
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}
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}
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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// And finally report it if there aren't enough:
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//
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if( spokes < minCount )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_STARVED_THERMAL );
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wxString msg;
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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msg.Printf( _( "(%s min spoke count %d; actual %d)" ),
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constraint.GetName(),
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minCount,
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spokes );
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2022-02-07 17:49:01 +00:00
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2022-06-18 18:47:11 +00:00
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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drce->SetItems( aZone, pad );
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drce->SetViolatingRule( constraint.GetParentRule() );
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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reportViolation( drce, pad->GetPosition(), UNDEFINED_LAYER );
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}
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}
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}
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}
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2021-08-09 10:10:09 +00:00
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2022-06-18 18:47:11 +00:00
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bool DRC_TEST_PROVIDER_ZONE_CONNECTIONS::Run()
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{
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BOARD* board = m_drcEngine->GetBoard();
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std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->GetConnectivity();
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DRC_CONSTRAINT constraint;
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if( !reportPhase( _( "Checking thermal reliefs..." ) ) )
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return false; // DRC cancelled
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std::vector< std::pair<ZONE*, PCB_LAYER_ID> > zoneLayers;
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for( ZONE* zone : board->m_DRCCopperZones )
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{
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for( PCB_LAYER_ID layer : zone->GetLayerSet().Seq() )
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zoneLayers.push_back( { zone, layer } );
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}
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2021-08-09 10:10:09 +00:00
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2022-06-15 00:41:10 +00:00
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thread_pool& tp = GetKiCadThreadPool();
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std::vector<std::future<int>> returns;
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returns.reserve( zoneLayers.size() );
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2022-06-18 18:47:11 +00:00
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2022-06-15 00:41:10 +00:00
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for( auto& zonelayer : zoneLayers )
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{
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2022-06-15 00:41:10 +00:00
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returns.emplace_back( tp.submit([&]( ZONE* aZone, PCB_LAYER_ID aLayer ) -> int
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2022-06-18 18:47:11 +00:00
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{
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2022-06-15 00:41:10 +00:00
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if( !m_drcEngine->IsCancelled() )
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2022-06-18 18:47:11 +00:00
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{
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2022-06-15 00:41:10 +00:00
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testZoneLayer( aZone, aLayer );
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m_drcEngine->AdvanceProgress();
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2021-08-09 10:10:09 +00:00
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}
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2022-06-15 00:41:10 +00:00
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return 0;
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}, zonelayer.first, zonelayer.second ) );
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2022-06-18 18:47:11 +00:00
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}
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2022-06-15 00:41:10 +00:00
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for( auto& retval : returns )
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{
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std::future_status status;
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do
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{
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m_drcEngine->KeepRefreshing();
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status = retval.wait_for( std::chrono::milliseconds( 100 ) );
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} while( status != std::future_status::ready );
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2021-08-09 10:10:09 +00:00
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}
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2022-03-11 20:13:47 +00:00
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return !m_drcEngine->IsCancelled();
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2021-08-09 10:10:09 +00:00
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}
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2021-08-08 13:37:14 +00:00
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_ZONE_CONNECTIONS> dummy;
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}
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