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Prefix TRACK, ARC and VIA.

This commit is contained in:
Jeff Young 2021-06-11 22:07:02 +01:00
parent 63c263090f
commit 096e342386
123 changed files with 746 additions and 756 deletions
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5
3d-viewer/3d_canvas/board_adapter.h
View File

@ -37,7 +37,7 @@
#include <layers_id_colors_and_visibility.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <wx/gdicmn.h>
#include <pcb_base_frame.h>
#include <pcb_text.h>
@ -564,7 +564,8 @@ private:
void destroyLayers();
// Helper functions to create the board
void createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer, int aClearanceValue );
void createTrack( const PCB_TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer,
int aClearanceValue );
void createPadWithClearance( const PAD *aPad, CONTAINER_2D_BASE* aDstContainer,
PCB_LAYER_ID aLayer, wxSize aClearanceValue ) const;

4
3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp
View File

@ -226,7 +226,7 @@ void BOARD_ADAPTER::addFootprintShapesWithClearance( const FOOTPRINT* aFootprint
}
void BOARD_ADAPTER::createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer,
void BOARD_ADAPTER::createTrack( const PCB_TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer,
int aClearanceValue )
{
SFVEC2F start3DU( aTrack->GetStart().x * m_biuTo3Dunits,
@ -243,7 +243,7 @@ void BOARD_ADAPTER::createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstCon
case PCB_ARC_T:
{
const ARC* arc = static_cast<const ARC*>( aTrack );
const PCB_ARC* arc = static_cast<const PCB_ARC*>( aTrack );
VECTOR2D center( arc->GetCenter() );
double arc_angle = arc->GetAngle();
double radius = arc->GetRadius();

30
3d-viewer/3d_canvas/create_layer_items.cpp
View File

@ -149,22 +149,22 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
m_averageHoleDiameter = 0;
// Prepare track list, convert in a vector. Calc statistic for the holes
std::vector< const TRACK *> trackList;
std::vector<const PCB_TRACK*> trackList;
trackList.clear();
trackList.reserve( m_board->Tracks().size() );
for( TRACK* track : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
if( !Is3dLayerEnabled( track->GetLayer() ) ) // Skip non enabled layers
continue;
// Note: a TRACK holds normal segment tracks and
// also vias circles (that have also drill values)
// Note: a PCB_TRACK holds normal segment tracks and also vias circles (that have also
// drill values)
trackList.push_back( track );
if( track->Type() == PCB_VIA_T )
{
const VIA *via = static_cast< const VIA*>( track );
const PCB_VIA *via = static_cast< const PCB_VIA*>( track );
m_viaCount++;
m_averageViaHoleDiameter += via->GetDrillValue() * m_biuTo3Dunits;
}
@ -235,14 +235,14 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
// NOTE: Vias can be on multiple layers
if( !track->IsOnLayer( curr_layer_id ) )
continue;
// Skip vias annulus when not connected on this layer (if removing is enabled)
const VIA *via = dyn_cast< const VIA*>( track );
const PCB_VIA *via = dyn_cast< const PCB_VIA*>( track );
if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
continue;
@ -260,7 +260,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
if( !track->IsOnLayer( curr_layer_id ) )
continue;
@ -268,13 +268,13 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
// ADD VIAS and THT
if( track->Type() == PCB_VIA_T )
{
const VIA* via = static_cast<const VIA*>( track );
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
const VIATYPE viatype = via->GetViaType();
const float holediameter = via->GetDrillValue() * BiuTo3dUnits();
// holes and layer copper extend half info cylinder wall to hide transition
const float thickness = GetHolePlatingThickness() * BiuTo3dUnits() / 2.0f;
const float hole_inner_radius = ( holediameter / 2.0f );
const float hole_inner_radius = holediameter / 2.0f;
const float ring_radius = via->GetWidth() * BiuTo3dUnits() / 2.0f;
const SFVEC2F via_center( via->GetStart().x * m_biuTo3Dunits,
@ -337,7 +337,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
if( !track->IsOnLayer( curr_layer_id ) )
continue;
@ -345,12 +345,12 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
// ADD VIAS and THT
if( track->Type() == PCB_VIA_T )
{
const VIA *via = static_cast< const VIA*>( track );
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
const VIATYPE viatype = via->GetViaType();
if( viatype != VIATYPE::THROUGH )
{
// Add VIA hole contours
// Add PCB_VIA hole contours
// Add outer holes of VIAs
SHAPE_POLY_SET *layerOuterHolesPoly = nullptr;
@ -430,13 +430,13 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
if( !track->IsOnLayer( curr_layer_id ) )
continue;
// Skip vias annulus when not connected on this layer (if removing is enabled)
const VIA *via = dyn_cast< const VIA*>( track );
const PCB_VIA *via = dyn_cast<const PCB_VIA*>( track );
if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
continue;

2
3d-viewer/3d_canvas/eda_3d_canvas.cpp
View File

@ -742,7 +742,7 @@ void EDA_3D_CANVAS::OnMouseMove( wxMouseEvent& event )
case PCB_VIA_T:
case PCB_ARC_T:
{
TRACK* track = dynamic_cast<TRACK*>( rollOverItem );
PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( rollOverItem );
if( track )
{

6
3d-viewer/3d_rendering/3d_render_raytracing/create_scene.cpp
View File

@ -1023,7 +1023,7 @@ void RENDER_3D_RAYTRACE::Reload( REPORTER* aStatusReporter, REPORTER* aWarningRe
}
void RENDER_3D_RAYTRACE::insertHole( const VIA* aVia )
void RENDER_3D_RAYTRACE::insertHole( const PCB_VIA* aVia )
{
PCB_LAYER_ID top_layer, bottom_layer;
int radiusBUI = ( aVia->GetDrillValue() / 2 );
@ -1254,11 +1254,11 @@ void RENDER_3D_RAYTRACE::addPadsAndVias()
// Insert plated vertical holes inside the board
// Insert vias holes (vertical cylinders)
for( TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
for( PCB_TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
{
if( track->Type() == PCB_VIA_T )
{
const VIA* via = static_cast<const VIA*>( track );
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
insertHole( via );
}
}

2
3d-viewer/3d_rendering/3d_render_raytracing/render_3d_raytrace.h
View File

@ -114,7 +114,7 @@ private:
float aZMax, const MATERIAL* aMaterial, const SFVEC3F& aObjColor );
void addPadsAndVias();
void insertHole( const VIA* aVia );
void insertHole( const PCB_VIA* aVia );
void insertHole( const PAD* aPad );
void loadModels( CONTAINER_3D& aDstContainer, bool aSkipMaterialInformation );
void addModels( CONTAINER_3D& aDstContainer, const S3DMODEL* a3DModel,

4
3d-viewer/3d_rendering/legacy/create_scene.cpp
View File

@ -737,11 +737,11 @@ void RENDER_3D_LEGACY::generateViasAndPads()
// Insert plated vertical holes inside the board
// Insert vias holes (vertical cylinders)
for( const TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
for( const PCB_TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
{
if( track->Type() == PCB_VIA_T )
{
const VIA* via = static_cast<const VIA*>( track );
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
const float holediameter = via->GetDrillValue() * m_boardAdapter.BiuTo3dUnits();
const int nrSegments = m_boardAdapter.GetCircleSegmentCount( via->GetDrillValue() );

2
common/CMakeLists.txt
View File

@ -529,7 +529,7 @@ set( PCB_COMMON_SRCS
${CMAKE_SOURCE_DIR}/pcbnew/pcb_text.cpp
${CMAKE_SOURCE_DIR}/pcbnew/board_stackup_manager/board_stackup.cpp
${CMAKE_SOURCE_DIR}/pcbnew/fp_text.cpp
${CMAKE_SOURCE_DIR}/pcbnew/track.cpp
${CMAKE_SOURCE_DIR}/pcbnew/pcb_track.cpp
${CMAKE_SOURCE_DIR}/pcbnew/zone.cpp
${CMAKE_SOURCE_DIR}/pcbnew/collectors.cpp
${CMAKE_SOURCE_DIR}/pcbnew/connectivity/connectivity_algo.cpp

2
gerbview/export_to_pcbnew.h
View File

@ -138,7 +138,7 @@ private:
void export_segarc_copper_item( const GERBER_DRAW_ITEM* aGbrItem, LAYER_NUM aLayer );
/**
* Basic write function to write a a #TRACK item to the board file from a non flashed item.
* Basic write function to write a a #PCB_TRACK to the board file from a non flashed item.
*/
void writeCopperLineItem( const wxPoint& aStart, const wxPoint& aEnd,
int aWidth, LAYER_NUM aLayer );

8
include/core/typeinfo.h
View File

@ -92,10 +92,10 @@ enum KICAD_T
PCB_FP_TEXT_T, ///< class FP_TEXT, text in a footprint
PCB_FP_SHAPE_T, ///< class FP_SHAPE, a footprint edge
PCB_FP_ZONE_T, ///< class ZONE, managed by a footprint
PCB_TRACE_T, ///< class TRACK, a track segment (segment on a copper layer)
PCB_VIA_T, ///< class VIA, a via (like a track segment on a copper layer)
PCB_ARC_T, ///< class ARC, an arc track segment on a copper layer
PCB_MARKER_T, ///< class MARKER_PCB, a marker used to show something
PCB_TRACE_T, ///< class PCB_TRACK, a track segment (segment on a copper layer)
PCB_VIA_T, ///< class PCB_VIA, a via (like a track segment on a copper layer)
PCB_ARC_T, ///< class PCB_ARC, an arc track segment on a copper layer
PCB_MARKER_T, ///< class PCB_MARKER, a marker used to show something
PCB_DIMENSION_T, ///< class PCB_DIMENSION_BASE: abstract dimension meta-type
PCB_DIM_ALIGNED_T, ///< class PCB_DIM_ALIGNED, a linear dimension (graphic item)
PCB_DIM_LEADER_T, ///< class PCB_DIM_LEADER, a leader dimension (graphic item)

1
include/pcb_base_frame.h
View File

@ -51,7 +51,6 @@ class BOARD;
class BOARD_CONNECTED_ITEM;
class COLOR_SETTINGS;
class FOOTPRINT;
class TRACK;
class PAD;
class EDA_3D_VIEWER;
class GENERAL_COLLECTOR;

1
pcbnew/autorouter/ar_autoplacer.cpp
View File

@ -31,7 +31,6 @@
#include <widgets/msgpanel.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_shape.h>
#include <pad.h>
#include <board_commit.h>

1
pcbnew/autorouter/ar_matrix.h
View File

@ -33,7 +33,6 @@
#include <layers_id_colors_and_visibility.h>
class PCB_SHAPE;
class TRACK;
class PAD;
class FOOTPRINT;

38
pcbnew/board.cpp
View File

@ -34,7 +34,7 @@
#include <board_commit.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <pcb_marker.h>
#include <pcb_group.h>
@ -116,7 +116,7 @@ BOARD::~BOARD()
m_footprints.clear();
for( TRACK* t : m_tracks )
for( PCB_TRACK* t : m_tracks )
delete t;
m_tracks.clear();
@ -307,7 +307,7 @@ TRACKS BOARD::TracksInNet( int aNetCode )
INSPECTOR_FUNC inspector = [aNetCode, &ret]( EDA_ITEM* item, void* testData )
{
TRACK* t = static_cast<TRACK*>( item );
PCB_TRACK* t = static_cast<PCB_TRACK*>( item );
if( t->GetNetCode() == aNetCode )
ret.push_back( t );
@ -315,7 +315,7 @@ TRACKS BOARD::TracksInNet( int aNetCode )
return SEARCH_RESULT::CONTINUE;
};
// visit this BOARD's TRACKs and VIAs with above TRACK INSPECTOR which
// visit this BOARD's PCB_TRACKs and PCB_VIAs with above TRACK INSPECTOR which
// appends all in aNetCode to ret.
Visit( inspector, nullptr, GENERAL_COLLECTOR::Tracks );
@ -546,7 +546,7 @@ void BOARD::SetElementVisibility( GAL_LAYER_ID aLayer, bool isEnabled )
// because we have a tool to show/hide ratsnest relative to a pad or a footprint
// so the hide/show option is a per item selection
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
track->SetLocalRatsnestVisible( isEnabled );
for( FOOTPRINT* footprint : Footprints() )
@ -644,9 +644,9 @@ void BOARD::Add( BOARD_ITEM* aBoardItem, ADD_MODE aMode )
}
if( aMode == ADD_MODE::APPEND || aMode == ADD_MODE::BULK_APPEND )
m_tracks.push_back( static_cast<TRACK*>( aBoardItem ) );
m_tracks.push_back( static_cast<PCB_TRACK*>( aBoardItem ) );
else
m_tracks.push_front( static_cast<TRACK*>( aBoardItem ) );
m_tracks.push_front( static_cast<PCB_TRACK*>( aBoardItem ) );
break;
@ -732,7 +732,7 @@ void BOARD::Remove( BOARD_ITEM* aBoardItem, REMOVE_MODE aRemoveMode )
zone->SetNet( unconnected );
}
for( TRACK* track : m_tracks )
for( PCB_TRACK* track : m_tracks )
{
if( track->GetNet() == item )
track->SetNet( unconnected );
@ -869,7 +869,7 @@ BOARD_ITEM* BOARD::GetItem( const KIID& aID ) const
if( aID == niluuid )
return nullptr;
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
{
if( track->m_Uuid == aID )
return track;
@ -948,7 +948,7 @@ void BOARD::FillItemMap( std::map<KIID, EDA_ITEM*>& aMap )
// the board itself
aMap[ m_Uuid ] = this;
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
aMap[ track->m_Uuid ] = track;
for( FOOTPRINT* footprint : Footprints() )
@ -1144,7 +1144,7 @@ EDA_RECT BOARD::ComputeBoundingBox( bool aBoardEdgesOnly ) const
if( !aBoardEdgesOnly )
{
// Check tracks
for( TRACK* track : m_tracks )
for( PCB_TRACK* track : m_tracks )
{
if( ( track->GetLayerSet() & visible ).any() )
area.Merge( track->GetBoundingBox() );
@ -1168,7 +1168,7 @@ void BOARD::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>
int viasCount = 0;
int trackSegmentsCount = 0;
for( TRACK* item : m_tracks )
for( PCB_TRACK* item : m_tracks )
{
if( item->Type() == PCB_VIA_T )
viasCount++;
@ -1288,13 +1288,13 @@ SEARCH_RESULT BOARD::Visit( INSPECTOR inspector, void* testData, const KICAD_T s
break;
case PCB_VIA_T:
result = IterateForward<TRACK*>( m_tracks, inspector, testData, p );
result = IterateForward<PCB_TRACK*>( m_tracks, inspector, testData, p );
++p;
break;
case PCB_TRACE_T:
case PCB_ARC_T:
result = IterateForward<TRACK*>( m_tracks, inspector, testData, p );
result = IterateForward<PCB_TRACK*>( m_tracks, inspector, testData, p );
++p;
break;
@ -1572,7 +1572,7 @@ PAD* BOARD::GetPad( const wxPoint& aPosition, LSET aLayerSet ) const
}
PAD* BOARD::GetPad( const TRACK* aTrace, ENDPOINT_T aEndPoint ) const
PAD* BOARD::GetPad( const PCB_TRACK* aTrace, ENDPOINT_T aEndPoint ) const
{
const wxPoint& aPosition = aTrace->GetEndPoint( aEndPoint );
@ -1734,7 +1734,7 @@ void BOARD::PadDelete( PAD* aPad )
}
std::tuple<int, double, double> BOARD::GetTrackLength( const TRACK& aTrack ) const
std::tuple<int, double, double> BOARD::GetTrackLength( const PCB_TRACK& aTrack ) const
{
int count = 0;
double length = 0.0;
@ -1750,11 +1750,11 @@ std::tuple<int, double, double> BOARD::GetTrackLength( const TRACK& aTrack ) con
{
count++;
if( TRACK* track = dynamic_cast<TRACK*>( item ) )
if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( item ) )
{
if( track->Type() == PCB_VIA_T && useHeight )
{
VIA* via = static_cast<VIA*>( track );
PCB_VIA* via = static_cast<PCB_VIA*>( track );
length += stackup.GetLayerDistance( via->TopLayer(), via->BottomLayer() );
continue;
}
@ -2018,7 +2018,7 @@ const std::vector<BOARD_CONNECTED_ITEM*> BOARD::AllConnectedItems()
{
std::vector<BOARD_CONNECTED_ITEM*> items;
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
items.push_back( track );
for( FOOTPRINT* footprint : Footprints() )

8
pcbnew/board.h
View File

@ -47,7 +47,7 @@ class PICKED_ITEMS_LIST;
class BOARD;
class FOOTPRINT;
class ZONE;
class TRACK;
class PCB_TRACK;
class PAD;
class PCB_GROUP;
class PCB_MARKER;
@ -927,11 +927,11 @@ public:
/**
* Find a pad connected to \a aEndPoint of \a aTrace.
*
* @param aTrace A pointer to a TRACK object to hit test against.
* @param aTrace A pointer to a PCB_TRACK object to hit test against.
* @param aEndPoint The end point of \a aTrace the hit test against.
* @return A pointer to a PAD object if found or NULL if not found.
*/
PAD* GetPad( const TRACK* aTrace, ENDPOINT_T aEndPoint ) const;
PAD* GetPad( const PCB_TRACK* aTrace, ENDPOINT_T aEndPoint ) const;
/**
* Return pad found at \a aPosition on \a aLayerMask using the fast search method.
@ -988,7 +988,7 @@ public:
* @param aTrack Starting track (can also be a via) to check against for connection.
* @return a tuple containing <number, length, package length>
*/
std::tuple<int, double, double> GetTrackLength( const TRACK& aTrack ) const;
std::tuple<int, double, double> GetTrackLength( const PCB_TRACK& aTrack ) const;
/**
* Collect all the TRACKs and VIAs that are members of a net given by aNetCode.

1
pcbnew/board_connected_item.h
View File

@ -30,7 +30,6 @@
class NETCLASS;
class NETINFO_ITEM;
class TRACK;
class PAD;
/**

2
pcbnew/board_design_settings.cpp
View File

@ -22,7 +22,7 @@
*/
#include <pcb_dimension.h>
#include <track.h>
#include <pcb_track.h>
#include <layers_id_colors_and_visibility.h>
#include <kiface_i.h>
#include <pad.h>

8
pcbnew/board_items_to_polygon_shape_transform.cpp
View File

@ -29,7 +29,7 @@
#include <board.h>
#include <pad.h>
#include <pcb_dimension.h>
#include <track.h>
#include <pcb_track.h>
#include <kicad_string.h>
#include <pcb_shape.h>
#include <pcb_text.h>
@ -72,7 +72,7 @@ void BOARD::ConvertBrdLayerToPolygonalContours( PCB_LAYER_ID aLayer, SHAPE_POLY_
int maxError = GetDesignSettings().m_MaxError;
// convert tracks and vias:
for( const TRACK* track : m_tracks )
for( const PCB_TRACK* track : m_tracks )
{
if( !track->IsOnLayer( aLayer ) )
continue;
@ -538,7 +538,7 @@ void PCB_SHAPE::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuf
}
void TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer,
void PCB_TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer,
PCB_LAYER_ID aLayer, int aClearanceValue,
int aError, ERROR_LOC aErrorLoc,
bool ignoreLineWidth ) const
@ -557,7 +557,7 @@ void TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer,
case PCB_ARC_T:
{
const ARC* arc = static_cast<const ARC*>( this );
const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
int width = m_Width + ( 2 * aClearanceValue );
TransformArcToPolygon( aCornerBuffer, arc->GetStart(), arc->GetMid(),

6
pcbnew/collectors.cpp
View File

@ -28,7 +28,7 @@
#include <footprint.h>
#include <fp_shape.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <pcb_marker.h>
#include <pcb_dimension.h>
#include <zone.h>
@ -161,7 +161,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData )
PCB_GROUP* group = nullptr;
PAD* pad = nullptr;
bool pad_through = false;
VIA* via = nullptr;
PCB_VIA* via = nullptr;
PCB_MARKER* marker = nullptr;
ZONE* zone = nullptr;
PCB_SHAPE* shape = nullptr;
@ -258,7 +258,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData )
break;
case PCB_VIA_T: // vias are on many layers, so layer test is specific
via = static_cast<VIA*>( item );
via = static_cast<PCB_VIA*>( item );
break;
case PCB_TRACE_T:

14
pcbnew/connectivity/connectivity_algo.cpp
View File

@ -148,21 +148,21 @@ bool CN_CONNECTIVITY_ALGO::Add( BOARD_ITEM* aItem )
if( m_itemMap.find( aItem ) != m_itemMap.end() )
return false;
add( m_itemList, static_cast<TRACK*>( aItem ) );
add( m_itemList, static_cast<PCB_TRACK*>( aItem ) );
break;
case PCB_ARC_T:
if( m_itemMap.find( aItem ) != m_itemMap.end() )
return false;
add( m_itemList, static_cast<ARC*>( aItem ) );
add( m_itemList, static_cast<PCB_ARC*>( aItem ) );
break;
case PCB_VIA_T:
if( m_itemMap.find( aItem ) != m_itemMap.end() )
return false;
add( m_itemList, static_cast<VIA*>( aItem ) );
add( m_itemList, static_cast<PCB_VIA*>( aItem ) );
break;
case PCB_ZONE_T:
@ -436,7 +436,7 @@ void CN_CONNECTIVITY_ALGO::Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter )
reportProgress( aReporter, ii++, size, delta );
}
for( TRACK* tv : aBoard->Tracks() )
for( PCB_TRACK* tv : aBoard->Tracks() )
{
Add( tv );
reportProgress( aReporter, ii++, size, delta );
@ -657,7 +657,7 @@ void CN_VISITOR::checkZoneItemConnection( CN_ZONE_LAYER* aZoneLayer, CN_ITEM* aI
|| aItem->Parent()->Type() == PCB_TRACE_T
|| aItem->Parent()->Type() == PCB_ARC_T )
{
accuracy = ( static_cast<TRACK*>( aItem->Parent() )->GetWidth() + 1 ) / 2;
accuracy = ( static_cast<PCB_TRACK*>( aItem->Parent() )->GetWidth() + 1 ) / 2;
}
for( int i = 0; i < aItem->AnchorCount(); ++i )
@ -776,12 +776,12 @@ bool CN_VISITOR::operator()( CN_ITEM* aCandidate )
if( parentA->Type() == PCB_VIA_T
|| parentA->Type() == PCB_TRACE_T
|| parentA->Type() == PCB_ARC_T)
accuracyA = ( static_cast<const TRACK*>( parentA )->GetWidth() + 1 ) / 2;
accuracyA = ( static_cast<const PCB_TRACK*>( parentA )->GetWidth() + 1 ) / 2;
if( parentB->Type() == PCB_VIA_T
|| parentB->Type() == PCB_TRACE_T
|| parentB->Type() == PCB_ARC_T )
accuracyB = ( static_cast<const TRACK*>( parentB )->GetWidth() + 1 ) / 2;
accuracyB = ( static_cast<const PCB_TRACK*>( parentB )->GetWidth() + 1 ) / 2;
// Items do not necessarily have reciprocity as we only check for anchors
// therefore, we check HitTest both directions A->B & B->A

16
pcbnew/connectivity/connectivity_data.cpp
View File

@ -484,23 +484,23 @@ bool CONNECTIVITY_DATA::CheckConnectivity( std::vector<CN_DISJOINT_NET_ENTRY>& a
}
const std::vector<TRACK*> CONNECTIVITY_DATA::GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem )
const
const std::vector<PCB_TRACK*> CONNECTIVITY_DATA::GetConnectedTracks(
const BOARD_CONNECTED_ITEM* aItem ) const
{
auto& entry = m_connAlgo->ItemEntry( aItem );
std::set<TRACK*> tracks;
std::vector<TRACK*> rv;
std::set<PCB_TRACK*> tracks;
std::vector<PCB_TRACK*> rv;
for( auto citem : entry.GetItems() )
for( CN_ITEM* citem : entry.GetItems() )
{
for( auto connected : citem->ConnectedItems() )
for( CN_ITEM* connected : citem->ConnectedItems() )
{
if( connected->Valid() &&
( connected->Parent()->Type() == PCB_TRACE_T ||
connected->Parent()->Type() == PCB_VIA_T ||
connected->Parent()->Type() == PCB_ARC_T ) )
tracks.insert( static_cast<TRACK*> ( connected->Parent() ) );
tracks.insert( static_cast<PCB_TRACK*> ( connected->Parent() ) );
}
}
@ -586,7 +586,7 @@ void CONNECTIVITY_DATA::GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges) const
}
bool CONNECTIVITY_DATA::TestTrackEndpointDangling( TRACK* aTrack, wxPoint* aPos )
bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* aPos )
{
auto items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems();

9
pcbnew/connectivity/connectivity_data.h
View File

@ -50,7 +50,7 @@ class BOARD_ITEM;
class ZONE;
class RN_DATA;
class RN_NET;
class TRACK;
class PCB_TRACK;
class PAD;
class FOOTPRINT;
class PROGRESS_REPORTER;
@ -195,13 +195,14 @@ public:
*/
unsigned int GetUnconnectedCount() const;
bool IsConnectedOnLayer( const BOARD_CONNECTED_ITEM* aItem, int aLayer, std::vector<KICAD_T> aTypes = {} ) const;
bool IsConnectedOnLayer( const BOARD_CONNECTED_ITEM* aItem,
int aLayer, std::vector<KICAD_T> aTypes = {} ) const;
unsigned int GetNodeCount( int aNet = -1 ) const;
unsigned int GetPadCount( int aNet = -1 ) const;
const std::vector<TRACK*> GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) const;
const std::vector<PCB_TRACK*> GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) const;
const std::vector<PAD*> GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem ) const;
@ -225,7 +226,7 @@ public:
void GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges ) const;
bool TestTrackEndpointDangling( TRACK* aTrack, wxPoint* aPos = nullptr );
bool TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* aPos = nullptr );
/**
* Function ClearDynamicRatsnest()

18
pcbnew/connectivity/connectivity_items.cpp
View File

@ -138,12 +138,12 @@ const VECTOR2I CN_ITEM::GetAnchor( int n ) const
case PCB_TRACE_T:
case PCB_ARC_T:
if( n == 0 )
return static_cast<const TRACK*>( m_parent )->GetStart();
return static_cast<const PCB_TRACK*>( m_parent )->GetStart();
else
return static_cast<const TRACK*>( m_parent )->GetEnd();
return static_cast<const PCB_TRACK*>( m_parent )->GetEnd();
case PCB_VIA_T:
return static_cast<const VIA*>( m_parent )->GetStart();
return static_cast<const PCB_VIA*>( m_parent )->GetStart();
default:
assert( false );
@ -158,9 +158,9 @@ void CN_ITEM::Dump()
{
wxLogDebug(" valid: %d, connected: \n", !!Valid());
for( auto i : m_connected )
for( CN_ITEM* i : m_connected )
{
TRACK* t = static_cast<TRACK*>( i->Parent() );
PCB_TRACK* t = static_cast<PCB_TRACK*>( i->Parent() );
wxLogDebug( " - %p %d\n", t, t->Type() );
}
}
@ -239,7 +239,7 @@ CN_ITEM* CN_LIST::Add( PAD* pad )
return item;
}
CN_ITEM* CN_LIST::Add( TRACK* track )
CN_ITEM* CN_LIST::Add( PCB_TRACK* track )
{
auto item = new CN_ITEM( track, true );
m_items.push_back( item );
@ -251,7 +251,7 @@ CN_ITEM* CN_LIST::Add( TRACK* track )
return item;
}
CN_ITEM* CN_LIST::Add( ARC* aArc )
CN_ITEM* CN_LIST::Add( PCB_ARC* aArc )
{
auto item = new CN_ITEM( aArc, true );
m_items.push_back( item );
@ -263,7 +263,7 @@ CN_ITEM* CN_LIST::Add( ARC* aArc )
return item;
}
CN_ITEM* CN_LIST::Add( VIA* via )
CN_ITEM* CN_LIST::Add( PCB_VIA* via )
{
auto item = new CN_ITEM( via, !via->GetIsFree(), 1 );
@ -365,7 +365,7 @@ bool CN_ANCHOR::IsDangling() const
return connected_count < minimal_count;
if( Parent()->Type() == PCB_TRACE_T || Parent()->Type() == PCB_ARC_T )
accuracy = ( static_cast<const TRACK*>( Parent() )->GetWidth() + 1 )/ 2;
accuracy = ( static_cast<const PCB_TRACK*>( Parent() )->GetWidth() + 1 ) / 2;
// Items with multiple anchors have usually items connected to each anchor.
// We want only the item count of this anchor point

8
pcbnew/connectivity/connectivity_items.h
View File

@ -32,7 +32,7 @@
#include <board.h>
#include <pad.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <geometry/shape_poly_set.h>
@ -432,11 +432,11 @@ public:
CN_ITEM* Add( PAD* pad );
CN_ITEM* Add( TRACK* track );
CN_ITEM* Add( PCB_TRACK* track );
CN_ITEM* Add( ARC* track );
CN_ITEM* Add( PCB_ARC* track );
CN_ITEM* Add( VIA* via );
CN_ITEM* Add( PCB_VIA* via );
const std::vector<CN_ITEM*> Add( ZONE* zone, PCB_LAYER_ID aLayer );

1
pcbnew/connectivity/from_to_cache.cpp
View File

@ -21,7 +21,6 @@
#include <memory>
#include <reporter.h>
#include <board.h>
#include <track.h>
#include <kicad_string.h>
#include <pcb_expr_evaluator.h>

4
pcbnew/cross-probing.cpp
View File

@ -35,7 +35,7 @@
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <collectors.h>
#include <eda_dde.h>
@ -257,7 +257,7 @@ void PCB_EDIT_FRAME::ExecuteRemoteCommand( const char* cmdline )
for( ZONE* zone : pcb->Zones() )
merge_area( zone );
for( TRACK* track : pcb->Tracks() )
for( PCB_TRACK* track : pcb->Tracks() )
merge_area( track );
for( FOOTPRINT* fp : pcb->Footprints() )

4
pcbnew/dialogs/dialog_board_statistics.cpp
View File

@ -257,9 +257,9 @@ void DIALOG_BOARD_STATISTICS::getDataFromPCB()
}
// Get via counts
for( TRACK* track : board->Tracks() )
for( PCB_TRACK* track : board->Tracks() )
{
if( VIA* via = dyn_cast<VIA*>( track ) )
if( PCB_VIA* via = dyn_cast<PCB_VIA*>( track ) )
{
for( auto& type : m_viasTypes )
{

2
pcbnew/dialogs/dialog_board_statistics.h
View File

@ -30,7 +30,7 @@
#include <base_units.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <dialog_board_statistics_base.h>
#include <pad_shapes.h>
#include <pcb_base_frame.h>

6
pcbnew/dialogs/dialog_gendrill.cpp
View File

@ -35,7 +35,7 @@
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <paths.h>
#include <project.h>
#include <dialog_gendrill.h>
@ -172,9 +172,9 @@ void DIALOG_GENDRILL::InitDisplayParams()
}
}
for( TRACK* track : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
const VIA *via = dynamic_cast<const VIA*>( track );
const PCB_VIA *via = dynamic_cast<const PCB_VIA*>( track );
if( via )
{

4
pcbnew/dialogs/dialog_global_deletion.cpp
View File

@ -30,7 +30,7 @@ using namespace std::placeholders;
#include <board_commit.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <tool/tool_manager.h>
#include <tools/pcb_actions.h>
#include <tools/global_edit_tool.h>
@ -213,7 +213,7 @@ void DIALOG_GLOBAL_DELETION::doGlobalDeletions()
if( delete_all || m_delTracks->GetValue() )
{
for( TRACK* track : board->Tracks() )
for( PCB_TRACK* track : board->Tracks() )
{
if( !delete_all )
{

11
pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp
View File

@ -25,7 +25,7 @@
#include <pcb_edit_frame.h>
#include <board.h>
#include <board_design_settings.h>
#include <track.h>
#include <pcb_track.h>
#include <connectivity/connectivity_data.h>
#include <pcb_layer_box_selector.h>
#include <tool/tool_manager.h>
@ -85,8 +85,8 @@ protected:
}
private:
void visitItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem );
void processItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem );
void visitItem( PICKED_ITEMS_LIST* aUndoList, PCB_TRACK* aItem );
void processItem( PICKED_ITEMS_LIST* aUndoList, PCB_TRACK* aItem );
bool TransferDataToWindow() override;
bool TransferDataFromWindow() override;
@ -271,7 +271,8 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::onSpecifiedValuesUpdateUi( wxUpdateUIEv
}
void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem )
void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem( PICKED_ITEMS_LIST* aUndoList,
PCB_TRACK* aItem )
{
BOARD_DESIGN_SETTINGS& brdSettings = m_brd->GetDesignSettings();
bool isTrack = aItem->Type() == PCB_TRACE_T;
@ -320,7 +321,7 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem( PICKED_ITEMS_LIST* aUndoLi
}
void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::visitItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem )
void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::visitItem( PICKED_ITEMS_LIST* aUndoList, PCB_TRACK* aItem )
{
if( m_selectedItemsFilter->GetValue() && !m_selection.Contains( aItem ) )
return;

12
pcbnew/dialogs/dialog_net_inspector.cpp
View File

@ -28,7 +28,7 @@
#include <board.h>
#include <board_design_settings.h>
#include <confirm.h>
#include <track.h>
#include <pcb_track.h>
#include <dialog_net_inspector.h>
#include <eda_pattern_match.h>
#include <wildcards_and_files_ext.h>
@ -1129,7 +1129,7 @@ void DIALOG_NET_INSPECTOR::OnBoardItemAdded( BOARD& aBoard, BOARD_ITEM* aBoardIt
if( r )
{
// try to handle frequent operations quickly.
if( TRACK* track = dynamic_cast<TRACK*>( i ) )
if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( i ) )
{
const std::unique_ptr<LIST_ITEM>& list_item = *r.get();
int len = track->GetLength();
@ -1228,7 +1228,7 @@ void DIALOG_NET_INSPECTOR::OnBoardItemRemoved( BOARD& aBoard, BOARD_ITEM* aBoard
if( r )
{
// try to handle frequent operations quickly.
if( TRACK* track = dynamic_cast<TRACK*>( i ) )
if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( i ) )
{
const std::unique_ptr<LIST_ITEM>& list_item = *r.get();
int len = track->GetLength();
@ -1370,9 +1370,9 @@ void DIALOG_NET_INSPECTOR::updateNet( NETINFO_ITEM* aNet )
}
unsigned int DIALOG_NET_INSPECTOR::calculateViaLength( const TRACK* aTrack ) const
unsigned int DIALOG_NET_INSPECTOR::calculateViaLength( const PCB_TRACK* aTrack ) const
{
const VIA& via = dynamic_cast<const VIA&>( *aTrack );
const PCB_VIA& via = dynamic_cast<const PCB_VIA&>( *aTrack );
BOARD_DESIGN_SETTINGS& bds = m_brd->GetDesignSettings();
// calculate the via length individually from the board stackup and via's start and end layer.
@ -1417,7 +1417,7 @@ DIALOG_NET_INSPECTOR::buildNewItem( NETINFO_ITEM* aNet, unsigned int aPadCount,
if( item->Type() == PCB_PAD_T )
new_item->AddChipWireLength( static_cast<PAD*>( item )->GetPadToDieLength() );
else if( TRACK* track = dynamic_cast<TRACK*>( item ) )
else if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( item ) )
{
new_item->AddBoardWireLength( track->GetLength() );

2
pcbnew/dialogs/dialog_net_inspector.h
View File

@ -89,7 +89,7 @@ private:
std::vector<CN_ITEM*> relevantConnectivityItems() const;
bool netFilterMatches( NETINFO_ITEM* aNet ) const;
void updateNet( NETINFO_ITEM* aNet );
unsigned int calculateViaLength( const TRACK* ) const;
unsigned int calculateViaLength( const PCB_TRACK* ) const;
void onSelChanged( wxDataViewEvent& event ) override;
void onSelChanged();

1
pcbnew/dialogs/dialog_swap_layers.cpp
View File

@ -23,7 +23,6 @@
#include <pcb_base_edit_frame.h>
#include <grid_layer_box_helpers.h>
#include <track.h>
#include <view/view.h>
#include <widgets/wx_grid.h>
#include <board.h>

14
pcbnew/dialogs/dialog_track_via_properties.cpp
View File

@ -30,7 +30,7 @@
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <pcb_edit_frame.h>
#include <confirm.h>
#include <connectivity/connectivity_data.h>
@ -108,7 +108,7 @@ DIALOG_TRACK_VIA_PROPERTIES::DIALOG_TRACK_VIA_PROPERTIES( PCB_BASE_FRAME* aParen
case PCB_TRACE_T:
case PCB_ARC_T:
{
const TRACK* t = static_cast<const TRACK*>( item );
const PCB_TRACK* t = static_cast<const PCB_TRACK*>( item );
if( !m_tracks ) // first track in the list
{
@ -155,7 +155,7 @@ DIALOG_TRACK_VIA_PROPERTIES::DIALOG_TRACK_VIA_PROPERTIES( PCB_BASE_FRAME* aParen
case PCB_VIA_T:
{
const VIA* v = static_cast<const VIA*>( item );
const PCB_VIA* v = static_cast<const PCB_VIA*>( item );
if( !m_vias ) // first via in the list
{
@ -426,7 +426,7 @@ bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow()
case PCB_ARC_T:
{
wxASSERT( m_tracks );
TRACK* t = static_cast<TRACK*>( item );
PCB_TRACK* t = static_cast<PCB_TRACK*>( item );
if( !m_trackStartX.IsIndeterminate() )
t->SetStart( wxPoint( m_trackStartX.GetValue(), t->GetStart().y ) );
@ -459,7 +459,7 @@ bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow()
case PCB_VIA_T:
{
wxASSERT( m_vias );
VIA* v = static_cast<VIA*>( item );
PCB_VIA* v = static_cast<PCB_VIA*>( item );
if( !m_viaX.IsIndeterminate() )
v->SetPosition( wxPoint( m_viaX.GetValue(), v->GetPosition().y ) );
@ -584,11 +584,11 @@ bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow()
{
case PCB_TRACE_T:
case PCB_ARC_T:
static_cast<TRACK*>( item )->SetNetCode( newNetCode );
static_cast<PCB_TRACK*>( item )->SetNetCode( newNetCode );
break;
case PCB_VIA_T:
static_cast<VIA*>( item )->SetNetCode( newNetCode );
static_cast<PCB_VIA*>( item )->SetNetCode( newNetCode );
break;
default:

8
pcbnew/dialogs/dialog_unused_pad_layers.cpp
View File

@ -27,7 +27,7 @@
#include <bitmaps.h>
#include <board_commit.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <pad.h>
#include <pcb_edit_frame.h>
#include <tools/pcb_selection_tool.h>
@ -88,7 +88,7 @@ bool DIALOG_UNUSED_PAD_LAYERS::TransferDataFromWindow()
if( item->Type() == PCB_VIA_T && m_rbScope->GetSelection() == SCOPE_VIAS )
{
VIA* via = static_cast<VIA*>( item );
PCB_VIA* via = static_cast<PCB_VIA*>( item );
via->SetRemoveUnconnected( m_rbAction->GetSelection() == PAD_ACTION_REMOVE );
via->SetKeepTopBottom( m_cbPreservePads->IsChecked() );
}
@ -130,13 +130,13 @@ bool DIALOG_UNUSED_PAD_LAYERS::TransferDataFromWindow()
}
else
{
for( TRACK* item : m_frame->GetBoard()->Tracks() )
for( PCB_TRACK* item : m_frame->GetBoard()->Tracks() )
{
if( item->Type() != PCB_VIA_T )
continue;
m_commit.Modify( item );
VIA* via = static_cast<VIA*>( item );
PCB_VIA* via = static_cast<PCB_VIA*>( item );
via->SetRemoveUnconnected( m_rbAction->GetSelection() == PAD_ACTION_REMOVE );
via->SetKeepTopBottom( m_cbPreservePads->IsChecked() );
}

1
pcbnew/dialogs/panel_pcbnew_color_settings.cpp
View File

@ -31,7 +31,6 @@
#include <widgets/appearance_controls.h>
#include <drawing_sheet/ds_proxy_view_item.h>
#include <pcb_painter.h>
#include <track.h>
#include <plugins/kicad/kicad_plugin.h>
#include <wx/treebook.h>

6
pcbnew/drc/drc_engine.cpp
View File

@ -35,7 +35,7 @@
#include <drc/drc_test_provider.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <geometry/shape.h>
#include <geometry/shape_segment.h>
@ -895,9 +895,9 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintId, const BOAR
}
else if( a->Type() == PCB_VIA_T )
{
if( static_cast<const VIA*>( a )->GetViaType() == VIATYPE::BLIND_BURIED )
if( static_cast<const PCB_VIA*>( a )->GetViaType() == VIATYPE::BLIND_BURIED )
mask = DRC_DISALLOW_VIAS | DRC_DISALLOW_BB_VIAS;
else if( static_cast<const VIA*>( a )->GetViaType() == VIATYPE::MICROVIA )
else if( static_cast<const PCB_VIA*>( a )->GetViaType() == VIATYPE::MICROVIA )
mask = DRC_DISALLOW_VIAS | DRC_DISALLOW_MICRO_VIAS;
else
mask = DRC_DISALLOW_VIAS;

1
pcbnew/drc/drc_rtree.h
View File

@ -28,7 +28,6 @@
#include <eda_rect.h>
#include <board_item.h>
#include <fp_text.h>
#include <track.h>
#include <memory>
#include <unordered_set>
#include <set>

4
pcbnew/drc/drc_test_provider.cpp
View File

@ -24,7 +24,7 @@
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_test_provider.h>
#include <track.h>
#include <pcb_track.h>
#include <footprint.h>
#include <pad.h>
#include <zone.h>
@ -167,7 +167,7 @@ int DRC_TEST_PROVIDER::forEachGeometryItem( const std::vector<KICAD_T>& aTypes,
typeMask[ aType ] = true;
}
for( TRACK* item : brd->Tracks() )
for( PCB_TRACK* item : brd->Tracks() )
{
if( (item->GetLayerSet() & aLayers).any() )
{

6
pcbnew/drc/drc_test_provider_annulus.cpp
View File

@ -22,7 +22,7 @@
*/
#include <common.h>
#include <track.h>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
@ -95,7 +95,7 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run()
int v_min = 0;
int v_max = 0;
VIA* via = dyn_cast<VIA*>( item );
PCB_VIA* via = dyn_cast<PCB_VIA*>( item );
// fixme: check minimum IAR/OAR ring for THT pads too
if( !via )
@ -149,7 +149,7 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run()
BOARD* board = m_drcEngine->GetBoard();
int ii = 0;
for( TRACK* item : board->Tracks() )
for( PCB_TRACK* item : board->Tracks() )
{
if( !reportProgress( ii++, board->Tracks().size(), delta ) )
break;

2
pcbnew/drc/drc_test_provider_connectivity.cpp
View File

@ -90,7 +90,7 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
ii += count; // We gave half of this phase to CONNECTIVITY_DATA::Build()
count += count;
for( TRACK* track : board->Tracks() )
for( PCB_TRACK* track : board->Tracks() )
{
bool exceedT = m_drcEngine->IsErrorLimitExceeded( DRCE_DANGLING_TRACK );
bool exceedV = m_drcEngine->IsErrorLimitExceeded( DRCE_DANGLING_VIA );

12
pcbnew/drc/drc_test_provider_copper_clearance.cpp
View File

@ -27,7 +27,7 @@
#include <footprint.h>
#include <pcb_shape.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <geometry/seg.h>
@ -81,7 +81,7 @@ public:
int GetNumPhases() const override;
private:
bool testTrackAgainstItem( TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer,
bool testTrackAgainstItem( PCB_TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer,
BOARD_ITEM* other );
void testTrackClearances();
@ -255,7 +255,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run()
}
bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( TRACK* track, SHAPE* trackShape,
bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( PCB_TRACK* track, SHAPE* trackShape,
PCB_LAYER_ID layer,
BOARD_ITEM* other )
{
@ -328,7 +328,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( TRACK* track, SHA
if( other->Type() == PCB_VIA_T )
{
VIA* via = static_cast<VIA*>( other );
PCB_VIA* via = static_cast<PCB_VIA*>( other );
pos = via->GetPosition();
if( via->GetLayerSet().Contains( layer ) )
@ -458,7 +458,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances()
std::map< std::pair<BOARD_ITEM*, BOARD_ITEM*>, int> checkedPairs;
for( TRACK* track : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
if( !reportProgress( ii++, m_board->Tracks().size(), delta ) )
break;
@ -541,7 +541,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa
testClearance = false;
// Track clearances are tested in testTrackClearances()
if( dynamic_cast<TRACK*>( other) )
if( dynamic_cast<PCB_TRACK*>( other) )
testClearance = false;
if( !testClearance && !testShorting && !testHoles )

22
pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp
View File

@ -20,7 +20,7 @@
#include <common.h>
#include <board.h>
#include <track.h>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
@ -162,8 +162,8 @@ struct DIFF_PAIR_COUPLED_SEGMENTS
{
SEG coupledN;
SEG coupledP;
TRACK* parentN;
TRACK* parentP;
PCB_TRACK* parentN;
PCB_TRACK* parentP;
int computedGap;
PCB_LAYER_ID layer;
bool couplingOK;
@ -190,18 +190,18 @@ static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp, DRC_RTREE& aTree
{
for( BOARD_CONNECTED_ITEM* itemP : aDp.itemsP )
{
TRACK* sp = dyn_cast<TRACK*>( itemP );
PCB_TRACK* sp = dyn_cast<PCB_TRACK*>( itemP );
OPT<DIFF_PAIR_COUPLED_SEGMENTS> bestCoupled;
int bestGap = std::numeric_limits<int>::max();
if(!sp)
if( !sp )
continue;
for ( BOARD_CONNECTED_ITEM* itemN : aDp.itemsN )
{
auto sn = dyn_cast<TRACK*> ( itemN );
PCB_TRACK* sn = dyn_cast<PCB_TRACK*> ( itemN );
if(!sn)
if( !sn )
continue;
if( ( sn->GetLayerSet() & sp->GetLayerSet() ).none() )
@ -374,17 +374,17 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
OPT<DRC_CONSTRAINT> maxUncoupledConstraint =
it.first.parentRule->FindConstraint( DIFF_PAIR_MAX_UNCOUPLED_CONSTRAINT );
for( auto& item : it.second.itemsN )
for( BOARD_CONNECTED_ITEM* item : it.second.itemsN )
{
// fixme: include vias
if( auto track = dyn_cast<TRACK*>( item ) )
if( PCB_TRACK* track = dyn_cast<PCB_TRACK*>( item ) )
it.second.totalLengthN += track->GetLength();
}
for( auto& item : it.second.itemsP )
for( BOARD_CONNECTED_ITEM* item : it.second.itemsP )
{
// fixme: include vias
if( auto track = dyn_cast<TRACK*>( item ) )
if( PCB_TRACK* track = dyn_cast<PCB_TRACK*>( item ) )
it.second.totalLengthP += track->GetLength();
}

14
pcbnew/drc/drc_test_provider_hole_size.cpp
View File

@ -23,7 +23,7 @@
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
@ -66,7 +66,7 @@ public:
int GetNumPhases() const override;
private:
void checkVia( VIA* via, bool aExceedMicro, bool aExceedStd );
void checkVia( PCB_VIA* via, bool aExceedMicro, bool aExceedStd );
void checkPad( PAD* aPad );
BOARD* m_board;
@ -111,15 +111,15 @@ bool DRC_TEST_PROVIDER_HOLE_SIZE::Run()
return false; // DRC cancelled
}
std::vector<VIA*> vias;
std::vector<PCB_VIA*> vias;
for( TRACK* track : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
if( track->Type() == PCB_VIA_T )
vias.push_back( static_cast<VIA*>( track ) );
vias.push_back( static_cast<PCB_VIA*>( track ) );
}
for( VIA* via : vias )
for( PCB_VIA* via : vias )
{
bool exceedMicro = m_drcEngine->IsErrorLimitExceeded( DRCE_MICROVIA_DRILL_OUT_OF_RANGE );
bool exceedStd = m_drcEngine->IsErrorLimitExceeded( DRCE_DRILL_OUT_OF_RANGE );
@ -191,7 +191,7 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkPad( PAD* aPad )
}
void DRC_TEST_PROVIDER_HOLE_SIZE::checkVia( VIA* via, bool aExceedMicro, bool aExceedStd )
void DRC_TEST_PROVIDER_HOLE_SIZE::checkVia( PCB_VIA* via, bool aExceedMicro, bool aExceedStd )
{
int errorCode;

10
pcbnew/drc/drc_test_provider_hole_to_hole.cpp
View File

@ -25,7 +25,7 @@
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <geometry/shape_segment.h>
#include <geometry/shape_circle.h>
#include <drc/drc_engine.h>
@ -84,7 +84,7 @@ static std::shared_ptr<SHAPE_CIRCLE> getDrilledHoleShape( BOARD_ITEM* aItem )
{
if( aItem->Type() == PCB_VIA_T )
{
VIA* via = static_cast<VIA*>( aItem );
PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
return std::make_shared<SHAPE_CIRCLE>( via->GetCenter(), via->GetDrillValue() / 2 );
}
else if( aItem->Type() == PCB_PAD_T )
@ -158,7 +158,7 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run()
}
else if( item->Type() == PCB_VIA_T )
{
VIA* via = static_cast<VIA*>( item );
PCB_VIA* via = static_cast<PCB_VIA*>( item );
// We only care about mechanically drilled (ie: non-laser) holes
if( via->GetViaType() == VIATYPE::THROUGH )
@ -176,12 +176,12 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run()
std::map< std::pair<BOARD_ITEM*, BOARD_ITEM*>, int> checkedPairs;
for( TRACK* track : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
if( track->Type() != PCB_VIA_T )
continue;
VIA* via = static_cast<VIA*>( track );
PCB_VIA* via = static_cast<PCB_VIA*>( track );
if( !reportProgress( ii++, count, delta ) )
return false; // DRC cancelled

11
pcbnew/drc/drc_test_provider_matched_length.cpp
View File

@ -20,7 +20,7 @@
#include <common.h>
#include <board.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
@ -92,7 +92,7 @@ private:
};
static int computeViaThruLength( VIA *aVia, const std::set<BOARD_CONNECTED_ITEM*> &conns )
static int computeViaThruLength( PCB_VIA *aVia, const std::set<BOARD_CONNECTED_ITEM*> &conns )
{
return 0; // fixme: not yet there...
}
@ -294,15 +294,16 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
if( citem->Type() == PCB_VIA_T )
{
ent.viaCount++;
ent.totalVia += computeViaThruLength( static_cast<VIA*>( citem ), nitem.second );
ent.totalVia += computeViaThruLength( static_cast<PCB_VIA*>( citem ),
nitem.second );
}
else if( citem->Type() == PCB_TRACE_T )
{
ent.totalRoute += static_cast<TRACK*>( citem )->GetLength();
ent.totalRoute += static_cast<PCB_TRACK*>( citem )->GetLength();
}
else if ( citem->Type() == PCB_ARC_T )
{
ent.totalRoute += static_cast<ARC*>( citem )->GetLength();
ent.totalRoute += static_cast<PCB_ARC*>( citem )->GetLength();
}
else if( citem->Type() == PCB_PAD_T )
{

8
pcbnew/drc/drc_test_provider_track_width.cpp
View File

@ -22,7 +22,7 @@
*/
//#include <common.h>
#include <track.h>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
@ -92,12 +92,12 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run()
int actual;
wxPoint p0;
if( ARC* arc = dyn_cast<ARC*>( item ) )
if( PCB_ARC* arc = dyn_cast<PCB_ARC*>( item ) )
{
actual = arc->GetWidth();
p0 = arc->GetStart();
}
else if( TRACK* trk = dyn_cast<TRACK*>( item ) )
else if( PCB_TRACK* trk = dyn_cast<PCB_TRACK*>( item ) )
{
actual = trk->GetWidth();
p0 = ( trk->GetStart() + trk->GetEnd() ) / 2;
@ -156,7 +156,7 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run()
int ii = 0;
for( TRACK* item : m_drcEngine->GetBoard()->Tracks() )
for( PCB_TRACK* item : m_drcEngine->GetBoard()->Tracks() )
{
if( !reportProgress( ii++, m_drcEngine->GetBoard()->Tracks().size(), delta ) )
break;

6
pcbnew/drc/drc_test_provider_via_diameter.cpp
View File

@ -21,7 +21,7 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <track.h>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
@ -88,7 +88,7 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run()
if( m_drcEngine->IsErrorLimitExceeded( DRCE_VIA_DIAMETER ) )
return false;
VIA* via = dyn_cast<VIA*>( item );
PCB_VIA* via = dyn_cast<PCB_VIA*>( item );
// fixme: move to pad stack check?
if( !via )
@ -145,7 +145,7 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run()
int ii = 0;
for( TRACK* item : m_drcEngine->GetBoard()->Tracks() )
for( PCB_TRACK* item : m_drcEngine->GetBoard()->Tracks() )
{
if( !reportProgress( ii++, m_drcEngine->GetBoard()->Tracks().size(), delta ) )
break;

1
pcbnew/edit.cpp
View File

@ -32,7 +32,6 @@
#include <board.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <zone.h>
#include <pcb_target.h>
#include <pcb_dimension.h>

8
pcbnew/edit_track_width.cpp
View File

@ -25,12 +25,12 @@
#include <board_design_settings.h>
#include <pcb_edit_frame.h>
#include <pcbnew_id.h>
#include <track.h>
#include <pcb_track.h>
#include <tools/pcb_actions.h>
#include <tool/tool_manager.h>
#include <wx/choice.h>
void PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
void PCB_EDIT_FRAME::SetTrackSegmentWidth( PCB_TRACK* aTrackItem,
PICKED_ITEMS_LIST* aItemsListPicker,
bool aUseNetclassValue )
{
@ -48,7 +48,7 @@ void PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
if( aTrackItem->Type() == PCB_VIA_T )
{
const VIA *via = static_cast<const VIA *>( aTrackItem );
const PCB_VIA *via = static_cast<const PCB_VIA*>( aTrackItem );
// Get the drill value, regardless it is default or specific
initial_drill = via->GetDrillValue();
@ -89,7 +89,7 @@ void PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
if( aTrackItem->Type() == PCB_VIA_T )
{
// Set new drill value. Note: currently microvias have only a default drill value
VIA *via = static_cast<VIA *>( aTrackItem );
PCB_VIA *via = static_cast<PCB_VIA*>( aTrackItem );
if( new_drill > 0 )
via->SetDrill( new_drill );

4
pcbnew/exporters/export_d356.cpp
View File

@ -41,7 +41,7 @@
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <vector>
#include <cctype>
#include <math/util.h> // for KiROUND
@ -175,7 +175,7 @@ static void build_via_testpoints( BOARD *aPcb, std::vector <D356_RECORD>& aRecor
{
if( track->Type() == PCB_VIA_T )
{
VIA *via = (VIA*) track;
PCB_VIA *via = static_cast<PCB_VIA*>( track );
NETINFO_ITEM *net = track->GetNet();
D356_RECORD rk;

26
pcbnew/exporters/export_gencad.cpp
View File

@ -35,7 +35,7 @@
#include <fp_shape.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <confirm.h>
#include <core/arraydim.h>
#include <dialogs/dialog_gencad_export_options.h>
@ -333,7 +333,7 @@ void PCB_EDIT_FRAME::ExportToGenCAD( wxCommandEvent& aEvent )
// Sort vias for uniqueness
static bool ViaSort( const VIA* aPadref, const VIA* aPadcmp )
static bool ViaSort( const PCB_VIA* aPadref, const PCB_VIA* aPadcmp )
{
if( aPadref->GetWidth() != aPadcmp->GetWidth() )
return aPadref->GetWidth() < aPadcmp->GetWidth();
@ -362,8 +362,8 @@ static void CreateArtworksSection( FILE* aFile )
static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb )
{
std::vector<PAD*> padstacks;
std::vector<VIA*> vias;
std::vector<VIA*> viastacks;
std::vector<PCB_VIA*> vias;
std::vector<PCB_VIA*> viastacks;
padstacks.resize( 1 ); // We count pads from 1
@ -383,14 +383,14 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb )
// The same for vias
for( TRACK* track : aPcb->Tracks() )
for( PCB_TRACK* track : aPcb->Tracks() )
{
if( VIA* via = dyn_cast<VIA*>( track ) )
if( PCB_VIA* via = dyn_cast<PCB_VIA*>( track ) )
vias.push_back( via );
}
std::sort( vias.begin(), vias.end(), ViaSort );
vias.erase( std::unique( vias.begin(), vias.end(), []( const VIA* a, const VIA* b )
vias.erase( std::unique( vias.begin(), vias.end(), []( const PCB_VIA* a, const PCB_VIA* b )
{
return ViaSort( a, b ) == false;
} ),
@ -398,7 +398,7 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb )
// Emit vias pads
for( VIA* via : vias )
for( PCB_VIA* via : vias )
{
viastacks.push_back( via );
fprintf( aFile, "PAD V%d.%d.%s ROUND %g\nCIRCLE 0 0 %g\n",
@ -608,7 +608,7 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb )
// Via padstacks
for( unsigned i = 0; i < viastacks.size(); i++ )
{
VIA* via = viastacks[i];
PCB_VIA* via = viastacks[i];
LSET mask = via->GetLayerSet() & master_layermask;
@ -982,7 +982,7 @@ static void CreateRoutesSection( FILE* aFile, BOARD* aPcb )
TRACKS tracks( aPcb->Tracks() );
std::sort( tracks.begin(), tracks.end(),
[]( const TRACK* a, const TRACK* b )
[]( const PCB_TRACK* a, const PCB_TRACK* b )
{
if( a->GetNetCode() == b->GetNetCode() )
{
@ -999,7 +999,7 @@ static void CreateRoutesSection( FILE* aFile, BOARD* aPcb )
old_netcode = -1; old_width = -1; old_layer = -1;
for( TRACK* track : tracks )
for( PCB_TRACK* track : tracks )
{
if( old_netcode != track->GetNetCode() )
{
@ -1037,7 +1037,7 @@ static void CreateRoutesSection( FILE* aFile, BOARD* aPcb )
if( track->Type() == PCB_VIA_T )
{
const VIA* via = static_cast<const VIA*>(track);
const PCB_VIA* via = static_cast<const PCB_VIA*>(track);
LSET vset = via->GetLayerSet() & master_layermask;
@ -1130,7 +1130,7 @@ static void CreateTracksInfoData( FILE* aFile, BOARD* aPcb )
std::set<int> trackinfo;
for( TRACK* track : aPcb->Tracks() )
for( PCB_TRACK* track : aPcb->Tracks() )
trackinfo.insert( track->GetWidth() );
// Write data

16
pcbnew/exporters/export_hyperlynx.cpp
View File

@ -29,7 +29,7 @@
#include <board_item.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <cstdio>
#include <vector>
@ -54,7 +54,7 @@ public:
friend class HYPERLYNX_EXPORTER;
HYPERLYNX_PAD_STACK( BOARD* aBoard, const PAD* aPad );
HYPERLYNX_PAD_STACK( BOARD* aBoard, const VIA* aVia );
HYPERLYNX_PAD_STACK( BOARD* aBoard, const PCB_VIA* aVia );
~HYPERLYNX_PAD_STACK(){};
bool isThrough() const
@ -246,7 +246,7 @@ HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PAD* aPad )
}
HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const VIA* aVia )
HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PCB_VIA* aVia )
{
m_board = aBoard;
m_sx = aVia->GetWidth();
@ -416,9 +416,9 @@ bool HYPERLYNX_EXPORTER::writePadStacks()
}
}
for( TRACK* trk : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
if( VIA* via = dyn_cast<VIA*>( trk ) )
if( PCB_VIA* via = dyn_cast<PCB_VIA*>( track ) )
{
HYPERLYNX_PAD_STACK* ps = addPadStack( HYPERLYNX_PAD_STACK( m_board, via ) );
m_padMap[via] = ps;
@ -459,7 +459,7 @@ bool HYPERLYNX_EXPORTER::writeNetObjects( const std::vector<BOARD_ITEM*>& aObjec
pstackIter->second->GetId() );
}
}
else if( VIA* via = dyn_cast<VIA*>( item ) )
else if( PCB_VIA* via = dyn_cast<PCB_VIA*>( item ) )
{
auto pstackIter = m_padMap.find( via );
@ -469,7 +469,7 @@ bool HYPERLYNX_EXPORTER::writeNetObjects( const std::vector<BOARD_ITEM*>& aObjec
iu2hyp( via->GetPosition().y ), pstackIter->second->GetId() );
}
}
else if( TRACK* track = dyn_cast<TRACK*>( item ) )
else if( PCB_TRACK* track = dyn_cast<PCB_TRACK*>( item ) )
{
const wxString layerName = m_board->GetLayerName( track->GetLayer() );
@ -560,7 +560,7 @@ const std::vector<BOARD_ITEM*> HYPERLYNX_EXPORTER::collectNetObjects( int netcod
}
}
for( TRACK* item : m_board->Tracks() )
for( PCB_TRACK* item : m_board->Tracks() )
{
if( check( item ) )
rv.push_back( item );

6
pcbnew/exporters/export_vrml.cpp
View File

@ -39,7 +39,7 @@
#include "footprint.h"
#include "pad.h"
#include "pcb_text.h"
#include "track.h"
#include "pcb_track.h"
#include "convert_to_biu.h"
#include <core/arraydim.h>
#include <filename_resolver.h>
@ -615,12 +615,12 @@ void EXPORTER_PCB_VRML::ExportVrmlViaHoles()
{
PCB_LAYER_ID top_layer, bottom_layer;
for( TRACK* track : m_Pcb->Tracks() )
for( PCB_TRACK* track : m_Pcb->Tracks() )
{
if( track->Type() != PCB_VIA_T )
continue;
const VIA* via = (const VIA*) track;
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
via->LayerPair( &top_layer, &bottom_layer );

2
pcbnew/exporters/exporter_vrml.h
View File

@ -140,7 +140,7 @@ public:
// Build and exports the board outlines (board body)
void ExportVrmlBoard();
void ExportVrmlVia( const VIA* aVia );
void ExportVrmlVia( const PCB_VIA* aVia );
// Export all via holes
void ExportVrmlViaHoles();

6
pcbnew/exporters/gendrill_file_writer_base.cpp
View File

@ -26,7 +26,7 @@
#include <board.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <collectors.h>
#include <reporter.h>
@ -81,7 +81,7 @@ void GENDRILL_WRITER_BASE::buildHolesList( DRILL_LAYER_PAIR aLayerPair,
if( track->Type() != PCB_VIA_T )
continue;
auto via = static_cast<VIA*>( track );
PCB_VIA* via = static_cast<PCB_VIA*>( track );
int hole_sz = via->GetDrillValue();
if( hole_sz == 0 ) // Should not occur.
@ -222,7 +222,7 @@ std::vector<DRILL_LAYER_PAIR> GENDRILL_WRITER_BASE::getUniqueLayerPairs() const
for( int i = 0; i < vias.GetCount(); ++i )
{
VIA* v = (VIA*) vias[i];
PCB_VIA* v = static_cast<PCB_VIA*>( vias[i] );
v->LayerPair( &layer_pair.first, &layer_pair.second );

4
pcbnew/exporters/gendrill_gerber_writer.cpp
View File

@ -36,7 +36,7 @@
#include <pcb_edit_frame.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <pad.h>
#include <pcbplot.h>
#include <gendrill_gerber_writer.h>
@ -182,7 +182,7 @@ int GERBER_WRITER::createDrillFile( wxString& aFullFilename, bool aIsNpth,
// "Slot" for oblong holes;
GBR_METADATA gbr_metadata;
if( dyn_cast<const VIA*>(hole_descr.m_ItemParent ) )
if( dyn_cast<const PCB_VIA*>( hole_descr.m_ItemParent ) )
{
gbr_metadata.SetApertureAttrib( GBR_APERTURE_METADATA::GBR_APERTURE_ATTRIB_VIADRILL );

4
pcbnew/exporters/gerber_jobfile_writer.cpp
View File

@ -40,7 +40,7 @@
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <board_stackup_manager/stackup_predefined_prms.h>
@ -496,7 +496,7 @@ void GERBER_JOBFILE_WRITER::addJSONDesignRules()
int mintrackWidthOuter = INT_MAX;
int mintrackWidthInner = INT_MAX;
for( TRACK* track : m_pcb->Tracks() )
for( PCB_TRACK* track : m_pcb->Tracks() )
{
if( track->Type() == PCB_VIA_T )
continue;

4
pcbnew/footprint.cpp
View File

@ -39,7 +39,7 @@
#include <pcb_text.h>
#include <pcb_marker.h>
#include <pcb_group.h>
#include <track.h>
#include <pcb_track.h>
#include <footprint.h>
#include <zone.h>
#include <view/view.h>
@ -1817,7 +1817,7 @@ double FOOTPRINT::GetCoverageArea( const BOARD_ITEM* aItem, const GENERAL_COLLEC
}
else if( aItem->Type() == PCB_TRACE_T || aItem->Type() == PCB_ARC_T )
{
double width = static_cast<const TRACK*>( aItem )->GetWidth();
double width = static_cast<const PCB_TRACK*>( aItem )->GetWidth();
return width * width;
}
else

1
pcbnew/kicad_clipboard.cpp
View File

@ -27,7 +27,6 @@
#include <build_version.h>
#include <board.h>
#include <track.h>
#include <pad.h>
#include <pcb_group.h>
#include <pcb_shape.h>

6
pcbnew/netinfo_item.cpp
View File

@ -34,7 +34,7 @@
#include <board.h>
#include <board_design_settings.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <pad.h>
@ -85,7 +85,7 @@ void NETINFO_ITEM::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANE
if( board )
{
int count = 0;
TRACK* startTrack = nullptr;
PCB_TRACK* startTrack = nullptr;
for( FOOTPRINT* footprint : board->Footprints() )
{
@ -100,7 +100,7 @@ void NETINFO_ITEM::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANE
count = 0;
for( TRACK* track : board->Tracks() )
for( PCB_TRACK* track : board->Tracks() )
{
if( track->GetNetCode() == GetNetCode() )
{

4
pcbnew/netinfo_list.cpp
View File

@ -25,7 +25,7 @@
#include <footprint.h>
#include <macros.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <netinfo.h>
#include <wx/log.h>
@ -223,7 +223,7 @@ void NETINFO_MAPPING::Update()
nets.insert( zone->GetNetCode() );
// Tracks
for( TRACK* track : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
nets.insert( track->GetNetCode() );
// footprints/pads

4
pcbnew/netlist_reader/board_netlist_updater.cpp
View File

@ -33,7 +33,7 @@
#include <netinfo.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <kicad_string.h>
#include <pcbnew_settings.h>
@ -608,7 +608,7 @@ bool BOARD_NETLIST_UPDATER::updateCopperZoneNets( NETLIST& aNetlist )
}
}
for( TRACK* via : m_board->Tracks() )
for( PCB_TRACK* via : m_board->Tracks() )
{
if( via->Type() != PCB_VIA_T )
continue;

1
pcbnew/pad.h
View File

@ -48,7 +48,6 @@ class LINE_READER;
class EDA_3D_CANVAS;
class FOOTPRINT;
class FP_SHAPE;
class TRACK;
namespace KIGFX
{

2
pcbnew/pcb_base_frame.cpp
View File

@ -751,7 +751,7 @@ void PCB_BASE_FRAME::SetDisplayOptions( const PCB_DISPLAY_OPTIONS& aOptions, boo
GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT,
[]( KIGFX::VIEW_ITEM* aItem ) -> bool
{
if( VIA* via = dynamic_cast<VIA*>( aItem ) )
if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
{
return via->GetViaType() == VIATYPE::BLIND_BURIED
|| via->GetViaType() == VIATYPE::MICROVIA;

6
pcbnew/pcb_draw_panel_gal.cpp
View File

@ -31,7 +31,7 @@
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <macros.h>
#include <pcb_marker.h>
#include <pcb_base_frame.h>
@ -207,7 +207,7 @@ void PCB_DRAW_PANEL_GAL::DisplayBoard( BOARD* aBoard )
m_view->Add( drawing );
// Load tracks
for( TRACK* track : aBoard->Tracks() )
for( PCB_TRACK* track : aBoard->Tracks() )
m_view->Add( track );
// Load footprints and its additional elements
@ -442,7 +442,7 @@ void PCB_DRAW_PANEL_GAL::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame,
int viasCount = 0;
int trackSegmentsCount = 0;
for( TRACK* item : board->Tracks() )
for( PCB_TRACK* item : board->Tracks() )
{
if( item->Type() == PCB_VIA_T )
viasCount++;

10
pcbnew/pcb_edit_frame.cpp
View File

@ -936,11 +936,11 @@ void PCB_EDIT_FRAME::ShowBoardSetupDialog( const wxString& aInitialPage )
GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT,
[&]( KIGFX::VIEW_ITEM* aItem ) -> bool
{
TRACK* track = dynamic_cast<TRACK*>( aItem );
PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( aItem );
PAD* pad = dynamic_cast<PAD*>( aItem );
// TRACK is the base class of VIA and ARC so we don't need to
// check them independently
// PCB_TRACK is the base class of PCB_VIA and PCB_ARC so we don't need
// to check them independently
return ( track && opts.m_ShowTrackClearanceMode )
|| ( pad && opts.m_DisplayPadClearance );
@ -1031,7 +1031,7 @@ void PCB_EDIT_FRAME::SetActiveLayer( PCB_LAYER_ID aLayer )
GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT,
[&]( KIGFX::VIEW_ITEM* aItem ) -> bool
{
if( VIA* via = dynamic_cast<VIA*>( aItem ) )
if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
{
// Vias on a restricted layer set must be redrawn when the active layer
// is changed
@ -1059,7 +1059,7 @@ void PCB_EDIT_FRAME::SetActiveLayer( PCB_LAYER_ID aLayer )
return true;
}
}
else if( TRACK* track = dynamic_cast<TRACK*>( aItem ) )
else if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( aItem ) )
{
// Clearances could be layer-dependent so redraw them when the active layer
// is changed

6
pcbnew/pcb_edit_frame.h
View File

@ -33,8 +33,8 @@ class BOARD;
class BOARD_COMMIT;
class BOARD_ITEM_CONTAINER;
class FOOTPRINT;
class TRACK;
class VIA;
class PCB_TRACK;
class PCB_VIA;
class PAD;
class PCB_TARGET;
class PCB_GROUP;
@ -544,7 +544,7 @@ public:
* @param aUseNetclassValue true to use NetClass value, false to use current designSettings
* value.
*/
void SetTrackSegmentWidth( TRACK* aTrackItem, PICKED_ITEMS_LIST* aItemsListPicker,
void SetTrackSegmentWidth( PCB_TRACK* aTrackItem, PICKED_ITEMS_LIST* aItemsListPicker,
bool aUseNetclassValue );

12
pcbnew/pcb_expr_evaluator.cpp
View File

@ -27,7 +27,7 @@
#include <board.h>
#include <board_design_settings.h>
#include <drc/drc_rtree.h>
#include <track.h>
#include <pcb_track.h>
#include <pcb_group.h>
#include <geometry/shape_segment.h>
#include <pcb_expr_evaluator.h>
@ -476,7 +476,7 @@ static void insideArea( LIBEVAL::CONTEXT* aCtx, void* self )
}
else if( item->Type() == PCB_VIA_T )
{
VIA* via = static_cast<VIA*>( item );
PCB_VIA* via = static_cast<PCB_VIA*>( item );
const SHAPE_CIRCLE holeShape( via->GetPosition(), via->GetDrillValue() );
return areaOutline.Collide( &holeShape );
@ -712,12 +712,10 @@ static void isMicroVia( LIBEVAL::CONTEXT* aCtx, void* self )
result->Set( 0.0 );
aCtx->Push( result );
auto via = dyn_cast<VIA*>( item );
PCB_VIA* via = dyn_cast<PCB_VIA*>( item );
if( via && via->GetViaType() == VIATYPE::MICROVIA )
{
result->Set ( 1.0 );
}
}
@ -730,12 +728,10 @@ static void isBlindBuriedVia( LIBEVAL::CONTEXT* aCtx, void* self )
result->Set( 0.0 );
aCtx->Push( result );
auto via = dyn_cast<VIA*>( item );
PCB_VIA* via = dyn_cast<PCB_VIA*>( item );
if( via && via->GetViaType() == VIATYPE::BLIND_BURIED )
{
result->Set ( 1.0 );
}
}

4
pcbnew/pcb_item_containers.h
View File

@ -28,14 +28,14 @@
// Board-level items
class FOOTPRINT;
class TRACK;
class PCB_TRACK;
class PCB_GROUP;
class PCB_MARKER;
class ZONE;
DECL_VEC_FOR_SWIG( MARKERS, PCB_MARKER* )
DECL_VEC_FOR_SWIG( ZONES, ZONE* )
DECL_DEQ_FOR_SWIG( TRACKS, TRACK* )
DECL_DEQ_FOR_SWIG( TRACKS, PCB_TRACK* )
DECL_DEQ_FOR_SWIG( FOOTPRINTS, FOOTPRINT* )
// Dequeue rather than Vector just so we can use moveUnflaggedItems in pcbnew_control.cpp
DECL_DEQ_FOR_SWIG( GROUPS, PCB_GROUP* )

28
pcbnew/pcb_painter.cpp
View File

@ -25,7 +25,7 @@
#include <board.h>
#include <board_design_settings.h>
#include <track.h>
#include <pcb_track.h>
#include <pcb_group.h>
#include <footprint.h>
#include <pad.h>
@ -234,7 +234,7 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons
// Careful that we don't end up with the same colour for the annular ring and the hole
// when printing in B&W.
const PAD* pad = dynamic_cast<const PAD*>( item );
const VIA* via = dynamic_cast<const VIA*>( item );
const PCB_VIA* via = dynamic_cast<const PCB_VIA*>( item );
int holeLayer = aLayer;
int annularRingLayer = UNDEFINED_LAYER;
@ -349,13 +349,13 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons
case LAYER_VIA_BBLIND:
case LAYER_VIA_MICROVIA:
// Target graphic is active if the via crosses the primary layer
if( static_cast<const VIA*>( item )->GetLayerSet().test( primary ) == 0 )
if( static_cast<const PCB_VIA*>( item )->GetLayerSet().test( primary ) == 0 )
isActive = false;
break;
case LAYER_VIA_THROUGH:
if( !static_cast<const VIA*>( item )->FlashLayer( primary ) )
if( !static_cast<const PCB_VIA*>( item )->FlashLayer( primary ) )
isActive = false;
break;
@ -371,11 +371,11 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons
case LAYER_VIA_HOLES:
case LAYER_VIA_HOLEWALLS:
if( static_cast<const VIA*>( item )->GetViaType() == VIATYPE::BLIND_BURIED
|| static_cast<const VIA*>( item )->GetViaType() == VIATYPE::MICROVIA )
if( static_cast<const PCB_VIA*>( item )->GetViaType() == VIATYPE::BLIND_BURIED
|| static_cast<const PCB_VIA*>( item )->GetViaType() == VIATYPE::MICROVIA )
{
// A blind or micro via's hole is active if it crosses the primary layer
if( static_cast<const VIA*>( item )->GetLayerSet().test( primary ) == 0 )
if( static_cast<const PCB_VIA*>( item )->GetLayerSet().test( primary ) == 0 )
isActive = false;
}
else
@ -445,7 +445,7 @@ VECTOR2D PCB_PAINTER::getDrillSize( const PAD* aPad ) const
}
int PCB_PAINTER::getDrillSize( const VIA* aVia ) const
int PCB_PAINTER::getDrillSize( const PCB_VIA* aVia ) const
{
return aVia->GetDrillValue();
}
@ -474,15 +474,15 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer )
switch( item->Type() )
{
case PCB_TRACE_T:
draw( static_cast<const TRACK*>( item ), aLayer );
draw( static_cast<const PCB_TRACK*>( item ), aLayer );
break;
case PCB_ARC_T:
draw( static_cast<const ARC*>( item ), aLayer );
draw( static_cast<const PCB_ARC*>( item ), aLayer );
break;
case PCB_VIA_T:
draw( static_cast<const VIA*>( item ), aLayer );
draw( static_cast<const PCB_VIA*>( item ), aLayer );
break;
case PCB_PAD_T:
@ -542,7 +542,7 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer )
}
void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
void PCB_PAINTER::draw( const PCB_TRACK* aTrack, int aLayer )
{
VECTOR2D start( aTrack->GetStart() );
VECTOR2D end( aTrack->GetEnd() );
@ -633,7 +633,7 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
}
void PCB_PAINTER::draw( const ARC* aArc, int aLayer )
void PCB_PAINTER::draw( const PCB_ARC* aArc, int aLayer )
{
VECTOR2D center( aArc->GetCenter() );
int width = aArc->GetWidth();
@ -679,7 +679,7 @@ void PCB_PAINTER::draw( const ARC* aArc, int aLayer )
}
void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
void PCB_PAINTER::draw( const PCB_VIA* aVia, int aLayer )
{
BOARD* board = aVia->GetBoard();
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();

14
pcbnew/pcb_painter.h
View File

@ -37,10 +37,10 @@
class EDA_ITEM;
class PCB_DISPLAY_OPTIONS;
class BOARD_ITEM;
class ARC;
class PCB_ARC;
class BOARD;
class VIA;
class TRACK;
class PCB_VIA;
class PCB_TRACK;
class PAD;
class PCB_SHAPE;
class PCB_GROUP;
@ -254,9 +254,9 @@ public:
protected:
// Drawing functions for various types of PCB-specific items
void draw( const TRACK* aTrack, int aLayer );
void draw( const ARC* aArc, int aLayer );
void draw( const VIA* aVia, int aLayer );
void draw( const PCB_TRACK* aTrack, int aLayer );
void draw( const PCB_ARC* aArc, int aLayer );
void draw( const PCB_VIA* aVia, int aLayer );
void draw( const PAD* aPad, int aLayer );
void draw( const PCB_SHAPE* aSegment, int aLayer );
void draw( const PCB_TEXT* aText, int aLayer );
@ -289,7 +289,7 @@ protected:
/**
* Return drill diameter for a via (internal units).
*/
virtual int getDrillSize( const VIA* aVia ) const;
virtual int getDrillSize( const PCB_VIA* aVia ) const;
protected:
PCB_RENDER_SETTINGS m_pcbSettings;

225
pcbnew/track.cpp → pcbnew/pcb_track.cpp
View File

@ -28,7 +28,7 @@
#include <connectivity/connectivity_data.h>
#include <board.h>
#include <board_design_settings.h>
#include <track.h>
#include <pcb_track.h>
#include <base_units.h>
#include <bitmaps.h>
#include <kicad_string.h>
@ -47,20 +47,21 @@
using KIGFX::PCB_PAINTER;
using KIGFX::PCB_RENDER_SETTINGS;
TRACK::TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) :
PCB_TRACK::PCB_TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) :
BOARD_CONNECTED_ITEM( aParent, idtype )
{
m_Width = Millimeter2iu( 0.2 ); // Gives a reasonable default width
}
EDA_ITEM* TRACK::Clone() const
EDA_ITEM* PCB_TRACK::Clone() const
{
return new TRACK( *this );
return new PCB_TRACK( *this );
}
ARC::ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) : TRACK( aParent, PCB_ARC_T )
PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
PCB_TRACK( aParent, PCB_ARC_T )
{
m_Start = wxPoint( aArc->GetP0() );
m_End = wxPoint( aArc->GetP1() );
@ -68,14 +69,14 @@ ARC::ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) : TRACK( aParent, PCB_ARC
}
EDA_ITEM* ARC::Clone() const
EDA_ITEM* PCB_ARC::Clone() const
{
return new ARC( *this );
return new PCB_ARC( *this );
}
VIA::VIA( BOARD_ITEM* aParent ) :
TRACK( aParent, PCB_VIA_T )
PCB_VIA::PCB_VIA( BOARD_ITEM* aParent ) :
PCB_TRACK( aParent, PCB_VIA_T )
{
SetViaType( VIATYPE::THROUGH );
m_bottomLayer = B_Cu;
@ -86,13 +87,13 @@ VIA::VIA( BOARD_ITEM* aParent ) :
}
EDA_ITEM* VIA::Clone() const
EDA_ITEM* PCB_VIA::Clone() const
{
return new VIA( *this );
return new PCB_VIA( *this );
}
wxString VIA::GetSelectMenuText( EDA_UNITS aUnits ) const
wxString PCB_VIA::GetSelectMenuText( EDA_UNITS aUnits ) const
{
wxString formatStr;
@ -109,13 +110,13 @@ wxString VIA::GetSelectMenuText( EDA_UNITS aUnits ) const
}
BITMAPS VIA::GetMenuImage() const
BITMAPS PCB_VIA::GetMenuImage() const
{
return BITMAPS::via;
}
bool TRACK::ApproxCollinear( const TRACK& aTrack )
bool PCB_TRACK::ApproxCollinear( const PCB_TRACK& aTrack )
{
SEG a( m_Start, m_End );
SEG b( aTrack.GetStart(), aTrack.GetEnd() );
@ -123,14 +124,14 @@ bool TRACK::ApproxCollinear( const TRACK& aTrack )
}
int TRACK::GetLocalClearance( wxString* aSource ) const
int PCB_TRACK::GetLocalClearance( wxString* aSource ) const
{
// Not currently implemented
return 0;
}
void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const
void PCB_TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const
{
*aMin = 0;
*aMax = INT_MAX;
@ -158,7 +159,7 @@ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const
}
int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
{
if( !FlashLayer( aLayer ) )
{
@ -189,7 +190,7 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
}
int VIA::GetDrillValue() const
int PCB_VIA::GetDrillValue() const
{
if( m_drill > 0 ) // Use the specific value.
return m_drill;
@ -204,7 +205,7 @@ int VIA::GetDrillValue() const
}
EDA_ITEM_FLAGS TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) const
EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) const
{
EDA_ITEM_FLAGS result = 0;
@ -236,7 +237,7 @@ EDA_ITEM_FLAGS TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) const
}
const EDA_RECT TRACK::GetBoundingBox() const
const EDA_RECT PCB_TRACK::GetBoundingBox() const
{
// end of track is round, this is its radius, rounded up
int radius = ( m_Width + 1 ) / 2;
@ -282,20 +283,20 @@ const EDA_RECT TRACK::GetBoundingBox() const
}
double TRACK::GetLength() const
double PCB_TRACK::GetLength() const
{
return GetLineLength( m_Start, m_End );
}
void TRACK::Rotate( const wxPoint& aRotCentre, double aAngle )
void PCB_TRACK::Rotate( const wxPoint& aRotCentre, double aAngle )
{
RotatePoint( &m_Start, aRotCentre, aAngle );
RotatePoint( &m_End, aRotCentre, aAngle );
}
void ARC::Rotate( const wxPoint& aRotCentre, double aAngle )
void PCB_ARC::Rotate( const wxPoint& aRotCentre, double aAngle )
{
RotatePoint( &m_Start, aRotCentre, aAngle );
RotatePoint( &m_End, aRotCentre, aAngle );
@ -303,7 +304,7 @@ void ARC::Rotate( const wxPoint& aRotCentre, double aAngle )
}
void TRACK::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
void PCB_TRACK::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
{
if( aFlipLeftRight )
{
@ -321,7 +322,7 @@ void TRACK::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
}
void ARC::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
void PCB_ARC::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
{
if( aFlipLeftRight )
{
@ -341,7 +342,7 @@ void ARC::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
}
void VIA::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
void PCB_VIA::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
{
if( aFlipLeftRight )
{
@ -368,7 +369,7 @@ void VIA::Flip( const wxPoint& aCentre, bool aFlipLeftRight )
// see class_track.h
SEARCH_RESULT TRACK::Visit( INSPECTOR inspector, void* testData, const KICAD_T scanTypes[] )
SEARCH_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData, const KICAD_T scanTypes[] )
{
KICAD_T stype = *scanTypes;
@ -383,7 +384,7 @@ SEARCH_RESULT TRACK::Visit( INSPECTOR inspector, void* testData, const KICAD_T s
}
bool VIA::IsOnLayer( PCB_LAYER_ID layer_number ) const
bool PCB_VIA::IsOnLayer( PCB_LAYER_ID layer_number ) const
{
PCB_LAYER_ID bottom_layer, top_layer;
@ -398,7 +399,7 @@ bool VIA::IsOnLayer( PCB_LAYER_ID layer_number ) const
}
LSET VIA::GetLayerSet() const
LSET PCB_VIA::GetLayerSet() const
{
if( GetViaType() == VIATYPE::THROUGH )
return LSET::AllCuMask();
@ -419,7 +420,7 @@ LSET VIA::GetLayerSet() const
}
void VIA::SetLayerSet( LSET aLayerSet )
void PCB_VIA::SetLayerSet( LSET aLayerSet )
{
bool first = true;
@ -436,7 +437,7 @@ void VIA::SetLayerSet( LSET aLayerSet )
}
void VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
{
m_layer = aTopLayer;
@ -445,19 +446,19 @@ void VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
}
void VIA::SetTopLayer( PCB_LAYER_ID aLayer )
void PCB_VIA::SetTopLayer( PCB_LAYER_ID aLayer )
{
m_layer = aLayer;
}
void VIA::SetBottomLayer( PCB_LAYER_ID aLayer )
void PCB_VIA::SetBottomLayer( PCB_LAYER_ID aLayer )
{
m_bottomLayer = aLayer;
}
void VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
{
PCB_LAYER_ID t_layer = F_Cu;
PCB_LAYER_ID b_layer = B_Cu;
@ -479,19 +480,19 @@ void VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
}
PCB_LAYER_ID VIA::TopLayer() const
PCB_LAYER_ID PCB_VIA::TopLayer() const
{
return m_layer;
}
PCB_LAYER_ID VIA::BottomLayer() const
PCB_LAYER_ID PCB_VIA::BottomLayer() const
{
return m_bottomLayer;
}
void VIA::SanitizeLayers()
void PCB_VIA::SanitizeLayers()
{
if( GetViaType() == VIATYPE::THROUGH )
{
@ -504,7 +505,7 @@ void VIA::SanitizeLayers()
}
bool VIA::FlashLayer( LSET aLayers ) const
bool PCB_VIA::FlashLayer( LSET aLayers ) const
{
for( auto layer : aLayers.Seq() )
{
@ -516,7 +517,7 @@ bool VIA::FlashLayer( LSET aLayers ) const
}
bool VIA::FlashLayer( int aLayer ) const
bool PCB_VIA::FlashLayer( int aLayer ) const
{
std::vector<KICAD_T> types
{ PCB_TRACE_T, PCB_ARC_T, PCB_PAD_T, PCB_ZONE_T, PCB_FP_ZONE_T };
@ -544,7 +545,7 @@ bool VIA::FlashLayer( int aLayer ) const
}
void TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
void PCB_TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
{
// Show the track and its netname on different layers
aLayers[0] = GetLayer();
@ -553,7 +554,7 @@ void TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
}
double TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
{
constexpr double HIDE = std::numeric_limits<double>::max();
@ -581,7 +582,7 @@ double TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
}
const BOX2I TRACK::ViewBBox() const
const BOX2I PCB_TRACK::ViewBBox() const
{
BOX2I bbox = GetBoundingBox();
@ -594,7 +595,7 @@ const BOX2I TRACK::ViewBBox() const
}
void VIA::ViewGetLayers( int aLayers[], int& aCount ) const
void PCB_VIA::ViewGetLayers( int aLayers[], int& aCount ) const
{
aLayers[0] = LAYER_VIA_HOLES;
aLayers[1] = LAYER_VIA_HOLEWALLS;
@ -613,7 +614,7 @@ void VIA::ViewGetLayers( int aLayers[], int& aCount ) const
}
double VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
{
constexpr double HIDE = (double)std::numeric_limits<double>::max();
@ -675,7 +676,7 @@ double VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
// see class_track.h
void TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
{
EDA_UNITS units = aFrame->GetUserUnits();
wxString msg;
@ -693,7 +694,7 @@ void TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>
if( Type() == PCB_ARC_T )
{
double radius = static_cast<ARC*>( this )->GetRadius();
double radius = static_cast<PCB_ARC*>( this )->GetRadius();
aList.emplace_back( _( "Radius" ), MessageTextFromValue( units, radius ) );
}
@ -736,7 +737,7 @@ void TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>
}
void VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
{
EDA_UNITS units = aFrame->GetUserUnits();
wxString msg;
@ -778,7 +779,8 @@ void VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>&
}
void TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList ) const
void PCB_TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame,
std::vector<MSG_PANEL_ITEM>& aList ) const
{
wxString msg;
@ -810,7 +812,7 @@ void TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame, std::vector<MSG_
}
wxString VIA::layerMaskDescribe() const
wxString PCB_VIA::layerMaskDescribe() const
{
BOARD* board = GetBoard();
PCB_LAYER_ID top_layer;
@ -822,13 +824,13 @@ wxString VIA::layerMaskDescribe() const
}
bool TRACK::HitTest( const wxPoint& aPosition, int aAccuracy ) const
bool PCB_TRACK::HitTest( const wxPoint& aPosition, int aAccuracy ) const
{
return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_Width / 2 ) );
}
bool ARC::HitTest( const wxPoint& aPosition, int aAccuracy ) const
bool PCB_ARC::HitTest( const wxPoint& aPosition, int aAccuracy ) const
{
int max_dist = aAccuracy + ( m_Width / 2 );
@ -864,7 +866,7 @@ bool ARC::HitTest( const wxPoint& aPosition, int aAccuracy ) const
}
bool VIA::HitTest( const wxPoint& aPosition, int aAccuracy ) const
bool PCB_VIA::HitTest( const wxPoint& aPosition, int aAccuracy ) const
{
int max_dist = aAccuracy + ( m_Width / 2 );
@ -875,7 +877,7 @@ bool VIA::HitTest( const wxPoint& aPosition, int aAccuracy ) const
}
bool TRACK::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
bool PCB_TRACK::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
{
EDA_RECT arect = aRect;
arect.Inflate( aAccuracy );
@ -887,7 +889,7 @@ bool TRACK::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) con
}
bool ARC::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
bool PCB_ARC::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
{
EDA_RECT box;
EDA_RECT arect = aRect;
@ -906,7 +908,7 @@ bool ARC::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
}
bool VIA::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
bool PCB_VIA::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
{
EDA_RECT box;
EDA_RECT arect = aRect;
@ -922,10 +924,9 @@ bool VIA::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) const
}
wxString TRACK::GetSelectMenuText( EDA_UNITS aUnits ) const
wxString PCB_TRACK::GetSelectMenuText( EDA_UNITS aUnits ) const
{
return wxString::Format( Type() == PCB_ARC_T ?
_("Track (arc) %s on %s, length %s" )
return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
: _("Track %s on %s, length %s" ),
GetNetnameMsg(),
GetLayerName(),
@ -933,46 +934,46 @@ wxString TRACK::GetSelectMenuText( EDA_UNITS aUnits ) const
}
BITMAPS TRACK::GetMenuImage() const
BITMAPS PCB_TRACK::GetMenuImage() const
{
return BITMAPS::add_tracks;
}
void TRACK::SwapData( BOARD_ITEM* aImage )
void PCB_TRACK::SwapData( BOARD_ITEM* aImage )
{
assert( aImage->Type() == PCB_TRACE_T );
std::swap( *((TRACK*) this), *((TRACK*) aImage) );
std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
}
void ARC::SwapData( BOARD_ITEM* aImage )
void PCB_ARC::SwapData( BOARD_ITEM* aImage )
{
assert( aImage->Type() == PCB_ARC_T );
std::swap( *this, *static_cast<ARC*>( aImage ) );
std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
}
void VIA::SwapData( BOARD_ITEM* aImage )
void PCB_VIA::SwapData( BOARD_ITEM* aImage )
{
assert( aImage->Type() == PCB_VIA_T );
std::swap( *((VIA*) this), *((VIA*) aImage) );
std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
}
wxPoint ARC::GetPosition() const
wxPoint PCB_ARC::GetPosition() const
{
auto center = GetArcCenter( VECTOR2I( m_Start ), VECTOR2I( m_Mid ), VECTOR2I( m_End ) );
return wxPoint( center.x, center.y );
}
double ARC::GetRadius() const
double PCB_ARC::GetRadius() const
{
auto center = GetArcCenter( VECTOR2I( m_Start ), VECTOR2I( m_Mid ), VECTOR2I( m_End ) );
return GetLineLength( wxPoint( center ), m_Start );
}
double ARC::GetAngle() const
double PCB_ARC::GetAngle() const
{
wxPoint center = GetPosition();
wxPoint p0 = m_Start - center;
@ -984,7 +985,7 @@ double ARC::GetAngle() const
return NormalizeAngle180( angle1 ) + NormalizeAngle180( angle2 );
}
double ARC::GetArcAngleStart() const
double PCB_ARC::GetArcAngleStart() const
{
wxPoint center = GetPosition();
@ -993,7 +994,7 @@ double ARC::GetArcAngleStart() const
return NormalizeAnglePos( angleStart );
}
double ARC::GetArcAngleEnd() const
double PCB_ARC::GetArcAngleEnd() const
{
wxPoint center = GetPosition();
@ -1003,7 +1004,7 @@ double ARC::GetArcAngleEnd() const
}
bool TRACK::cmp_tracks::operator() ( const TRACK* a, const TRACK* b ) const
bool PCB_TRACK::cmp_tracks::operator() ( const PCB_TRACK* a, const PCB_TRACK* b ) const
{
if( a->GetNetCode() != b->GetNetCode() )
return a->GetNetCode() < b->GetNetCode();
@ -1021,13 +1022,13 @@ bool TRACK::cmp_tracks::operator() ( const TRACK* a, const TRACK* b ) const
}
std::shared_ptr<SHAPE> TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
{
return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, m_Width );
}
std::shared_ptr<SHAPE> VIA::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
{
if( FlashLayer( aLayer ) )
return std::make_shared<SHAPE_CIRCLE>( m_Start, m_Width / 2 );
@ -1036,7 +1037,7 @@ std::shared_ptr<SHAPE> VIA::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
}
std::shared_ptr<SHAPE> ARC::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
{
return std::make_shared<SHAPE_ARC>( GetStart(), GetMid(), GetEnd(), GetWidth() );
}
@ -1045,7 +1046,7 @@ std::shared_ptr<SHAPE> ARC::GetEffectiveShape( PCB_LAYER_ID aLayer ) const
#if defined(DEBUG)
wxString TRACK::ShowState( int stateBits )
wxString PCB_TRACK::ShowState( int stateBits )
{
wxString ret;
@ -1102,57 +1103,57 @@ static struct TRACK_VIA_DESC
PROPERTY_MANAGER& propMgr = PROPERTY_MANAGER::Instance();
// Track
REGISTER_TYPE( TRACK );
propMgr.InheritsAfter( TYPE_HASH( TRACK ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
REGISTER_TYPE( PCB_TRACK );
propMgr.InheritsAfter( TYPE_HASH( PCB_TRACK ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
propMgr.AddProperty( new PROPERTY<TRACK, int>( _HKI( "Width" ),
&TRACK::SetWidth, &TRACK::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
&PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
new PROPERTY<TRACK, int, BOARD_ITEM>( _HKI( "Origin X" ),
&TRACK::SetX, &TRACK::GetX, PROPERTY_DISPLAY::DISTANCE ) );
new PROPERTY<PCB_TRACK, int, BOARD_ITEM>( _HKI( "Origin X" ),
&PCB_TRACK::SetX, &PCB_TRACK::GetX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
new PROPERTY<TRACK, int, BOARD_ITEM>( _HKI( "Origin Y" ),
&TRACK::SetY, &TRACK::GetY, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<TRACK, int>( _HKI( "End X" ),
&TRACK::SetEndX, &TRACK::GetEndX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<TRACK, int>( _HKI( "End Y" ),
&TRACK::SetEndY, &TRACK::GetEndY, PROPERTY_DISPLAY::DISTANCE ) );
new PROPERTY<PCB_TRACK, int, BOARD_ITEM>( _HKI( "Origin Y" ),
&PCB_TRACK::SetY, &PCB_TRACK::GetY, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
&PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
&PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::DISTANCE ) );
// Arc
REGISTER_TYPE( ARC );
propMgr.InheritsAfter( TYPE_HASH( ARC ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
REGISTER_TYPE( PCB_ARC );
propMgr.InheritsAfter( TYPE_HASH( PCB_ARC ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
propMgr.AddProperty( new PROPERTY<TRACK, int>( _HKI( "Width" ),
&ARC::SetWidth, &ARC::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
&PCB_ARC::SetWidth, &PCB_ARC::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
new PROPERTY<ARC, int, BOARD_ITEM>( _HKI( "Origin X" ),
&TRACK::SetX, &ARC::GetX, PROPERTY_DISPLAY::DISTANCE ) );
new PROPERTY<PCB_ARC, int, BOARD_ITEM>( _HKI( "Origin X" ),
&PCB_TRACK::SetX, &PCB_ARC::GetX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
new PROPERTY<ARC, int, BOARD_ITEM>( _HKI( "Origin Y" ),
&TRACK::SetY, &ARC::GetY, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<TRACK, int>( _HKI( "End X" ),
&TRACK::SetEndX, &ARC::GetEndX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<TRACK, int>( _HKI( "End Y" ),
&TRACK::SetEndY, &ARC::GetEndY, PROPERTY_DISPLAY::DISTANCE ) );
new PROPERTY<PCB_ARC, int, BOARD_ITEM>( _HKI( "Origin Y" ),
&PCB_TRACK::SetY, &PCB_ARC::GetY, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
&PCB_TRACK::SetEndX, &PCB_ARC::GetEndX, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
&PCB_TRACK::SetEndY, &PCB_ARC::GetEndY, PROPERTY_DISPLAY::DISTANCE ) );
// Via
REGISTER_TYPE( VIA );
propMgr.InheritsAfter( TYPE_HASH( VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
REGISTER_TYPE( PCB_VIA );
propMgr.InheritsAfter( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
// TODO layerset for vias?
// TODO test drill, use getdrillvalue?
propMgr.ReplaceProperty( TYPE_HASH( TRACK ), _HKI( "Width" ),
new PROPERTY<VIA, int, TRACK>( _HKI( "Diameter" ),
&VIA::SetWidth, &VIA::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<VIA, int>( _HKI( "Drill" ),
&VIA::SetDrill, &VIA::GetDrillValue, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( PCB_TRACK ), _HKI( "Width" ),
new PROPERTY<PCB_VIA, int, PCB_TRACK>( _HKI( "Diameter" ),
&PCB_VIA::SetWidth, &PCB_VIA::GetWidth, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Drill" ),
&PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::DISTANCE ) );
propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Layer" ),
new PROPERTY_ENUM<VIA, PCB_LAYER_ID, BOARD_ITEM>( _HKI( "Layer Top" ),
&VIA::SetLayer, &VIA::GetLayer ) );
propMgr.AddProperty( new PROPERTY_ENUM<VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
&VIA::SetBottomLayer, &VIA::BottomLayer ) );
propMgr.AddProperty( new PROPERTY_ENUM<VIA, VIATYPE>( _HKI( "Via Type" ),
&VIA::SetViaType, &VIA::GetViaType ) );
new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID, BOARD_ITEM>( _HKI( "Layer Top" ),
&PCB_VIA::SetLayer, &PCB_VIA::GetLayer ) );
propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
&PCB_VIA::SetBottomLayer, &PCB_VIA::BottomLayer ) );
propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
&PCB_VIA::SetViaType, &PCB_VIA::GetViaType ) );
}
} _TRACK_VIA_DESC;

40
pcbnew/track.h → pcbnew/pcb_track.h
View File

@ -2,7 +2,7 @@
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2004 Jean-Pierre Charras, jaen-pierre.charras@gipsa-lab.inpg.com
* Copyright (C) 1992-2020 KiCad Developers, see AUTHORS.txt for contributors.
* Copyright (C) 1992-2021 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -23,9 +23,8 @@
*/
/**
* @file class_track.h
* @brief A single base class (TRACK) represents both tracks and vias, with subclasses
* for curved tracks (ARC) and vias (VIA). All told there are three KICAD_Ts:
* @brief A single base class (PCB_TRACK) represents both tracks and vias, with subclasses
* for curved tracks (PCB_ARC) and vias (PCB_VIA). All told there are three KICAD_Ts:
* PCB_TRACK_T, PCB_ARC_T, and PCB_VIA_T.
*
* For vias there is a further VIATYPE which indicates THROUGH, BLIND_BURIED, or
@ -41,8 +40,8 @@
#include <convert_to_biu.h>
class TRACK;
class VIA;
class PCB_TRACK;
class PCB_VIA;
class PAD;
class MSG_PANEL_ITEM;
class SHAPE_POLY_SET;
@ -73,7 +72,7 @@ enum class VIATYPE : int
#define GEOMETRY_MIN_SIZE ( int )( 0.001 * IU_PER_MM )
class TRACK : public BOARD_CONNECTED_ITEM
class PCB_TRACK : public BOARD_CONNECTED_ITEM
{
public:
static inline bool ClassOf( const EDA_ITEM* aItem )
@ -81,7 +80,7 @@ public:
return aItem && PCB_TRACE_T == aItem->Type();
}
TRACK( BOARD_ITEM* aParent, KICAD_T idtype = PCB_TRACE_T );
PCB_TRACK( BOARD_ITEM* aParent, KICAD_T idtype = PCB_TRACE_T );
// Do not create a copy constructor. The one generated by the compiler is adequate.
@ -177,11 +176,11 @@ public:
bool HitTest( const wxPoint& aPosition, int aAccuracy = 0 ) const override;
bool HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy = 0 ) const override;
bool ApproxCollinear( const TRACK& aTrack );
bool ApproxCollinear( const PCB_TRACK& aTrack );
wxString GetClass() const override
{
return wxT( "TRACK" );
return wxT( "PCB_TRACK" );
}
/**
@ -218,7 +217,7 @@ public:
struct cmp_tracks
{
bool operator()( const TRACK* aFirst, const TRACK* aSecond ) const;
bool operator()( const PCB_TRACK* aFirst, const PCB_TRACK* aSecond ) const;
};
#if defined (DEBUG)
@ -244,12 +243,15 @@ protected:
};
class ARC : public TRACK
class PCB_ARC : public PCB_TRACK
{
public:
ARC( BOARD_ITEM* aParent ) : TRACK( aParent, PCB_ARC_T ){};
PCB_ARC( BOARD_ITEM* aParent ) :
PCB_TRACK( aParent, PCB_ARC_T )
{
};
ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc );
PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc );
static inline bool ClassOf( const EDA_ITEM *aItem )
{
@ -289,7 +291,7 @@ public:
wxString GetClass() const override
{
return wxT( "ARC" );
return wxT( "PCB_ARC" );
}
// @copydoc BOARD_ITEM::GetEffectiveShape
@ -319,10 +321,10 @@ private:
};
class VIA : public TRACK
class PCB_VIA : public PCB_TRACK
{
public:
VIA( BOARD_ITEM* aParent );
PCB_VIA( BOARD_ITEM* aParent );
static inline bool ClassOf( const EDA_ITEM *aItem )
{
@ -397,7 +399,7 @@ public:
wxString GetClass() const override
{
return wxT( "VIA" );
return wxT( "PCB_VIA" );
}
wxString GetSelectMenuText( EDA_UNITS aUnits ) const override;
@ -454,7 +456,7 @@ public:
/**
* Function GetDrill
* returns the local drill setting for this VIA. If you want the calculated value,
* returns the local drill setting for this PCB_VIA. If you want the calculated value,
* use GetDrillValue() instead.
*/
int GetDrill() const { return m_drill; }

2
pcbnew/pcbnew_printout.cpp
View File

@ -309,7 +309,7 @@ VECTOR2D KIGFX::PCB_PRINT_PAINTER::getDrillSize( const PAD* aPad ) const
}
int KIGFX::PCB_PRINT_PAINTER::getDrillSize( const VIA* aVia ) const
int KIGFX::PCB_PRINT_PAINTER::getDrillSize( const PCB_VIA* aVia ) const
{
// TODO should it depend on the via size?
return m_drillMarkReal ? KIGFX::PCB_PAINTER::getDrillSize( aVia ) : m_drillMarkSize;

2
pcbnew/pcbnew_printout.h
View File

@ -105,7 +105,7 @@ protected:
VECTOR2D getDrillSize( const PAD* aPad ) const override;
int getDrillSize( const VIA* aVia ) const override;
int getDrillSize( const PCB_VIA* aVia ) const override;
///< Flag deciding whether use the actual hole size or user-specified size for drill marks
bool m_drillMarkReal;

18
pcbnew/plot_board_layers.cpp
View File

@ -39,7 +39,7 @@
#include <board_design_settings.h>
#include <core/arraydim.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <fp_shape.h>
#include <pad.h>
#include <pcb_text.h>
@ -426,9 +426,9 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask,
aPlotter->StartBlock( NULL );
for( const TRACK* track : aBoard->Tracks() )
for( const PCB_TRACK* track : aBoard->Tracks() )
{
const VIA* via = dyn_cast<const VIA*>( track );
const PCB_VIA* via = dyn_cast<const PCB_VIA*>( track );
if( !via )
continue;
@ -489,7 +489,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask,
gbr_metadata.SetApertureAttrib( GBR_APERTURE_METADATA::GBR_APERTURE_ATTRIB_CONDUCTOR );
// Plot tracks (not vias) :
for( const TRACK* track : aBoard->Tracks() )
for( const PCB_TRACK* track : aBoard->Tracks() )
{
if( track->Type() == PCB_VIA_T )
continue;
@ -507,7 +507,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask,
if( track->Type() == PCB_ARC_T )
{
const ARC* arc = static_cast<const ARC*>( track );
const PCB_ARC* arc = static_cast<const PCB_ARC*>( track );
VECTOR2D center( arc->GetCenter() );
int radius = arc->GetRadius();
double start_angle = arc->GetArcAngleStart();
@ -696,9 +696,9 @@ void PlotLayerOutlines( BOARD* aBoard, PLOTTER* aPlotter, LSET aLayerMask,
}
// Plot vias holes
for( TRACK* track : aBoard->Tracks() )
for( PCB_TRACK* track : aBoard->Tracks() )
{
const VIA* via = dyn_cast<const VIA*>( track );
const PCB_VIA* via = dyn_cast<const PCB_VIA*>( track );
if( via && via->IsOnLayer( layer ) ) // via holes can be not through holes
{
@ -811,9 +811,9 @@ void PlotSolderMaskLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask,
int via_clearance = aBoard->GetDesignSettings().m_SolderMaskMargin;
int via_margin = via_clearance + inflate;
for( TRACK* track : aBoard->Tracks() )
for( PCB_TRACK* track : aBoard->Tracks() )
{
const VIA* via = dyn_cast<const VIA*>( track );
const PCB_VIA* via = dyn_cast<const PCB_VIA*>( track );
if( !via )
continue;

6
pcbnew/plot_brditems_plotter.cpp
View File

@ -59,7 +59,7 @@
#include <fp_shape.h>
#include <footprint.h>
#include <fp_text.h>
#include <track.h>
#include <pcb_track.h>
#include <pad.h>
#include <pcb_target.h>
#include <pcb_text.h>
@ -1016,9 +1016,9 @@ void BRDITEMS_PLOTTER::PlotDrillMarks()
if( GetPlotMode() == FILLED )
m_plotter->SetColor( WHITE );
for( TRACK* tracks : m_board->Tracks() )
for( PCB_TRACK* tracks : m_board->Tracks() )
{
const VIA* via = dyn_cast<const VIA*>( tracks );
const PCB_VIA* via = dyn_cast<const PCB_VIA*>( tracks );
if( via )
{

8
pcbnew/plugins/altium/altium_pcb.cpp
View File

@ -32,7 +32,7 @@
#include <pad.h>
#include <pcb_shape.h>
#include <pcb_text.h>
#include <track.h>
#include <pcb_track.h>
#include <kicad_string.h>
#include <fp_shape.h>
@ -1707,7 +1707,7 @@ void ALTIUM_PCB::ParseArcs6Data( const CFB::CompoundFileReader& aReader,
-KiROUND( std::sin( startradiant ) * elem.radius ) );
SHAPE_ARC shapeArc( elem.center, elem.center + arcStartOffset, angle, elem.width );
ARC* arc = new ARC( m_board, &shapeArc );
PCB_ARC* arc = new PCB_ARC( m_board, &shapeArc );
m_board->Add( arc, ADD_MODE::APPEND );
arc->SetWidth( elem.width );
@ -2166,7 +2166,7 @@ void ALTIUM_PCB::ParseVias6Data( const CFB::CompoundFileReader& aReader,
{
AVIA6 elem( reader );
VIA* via = new VIA( m_board );
PCB_VIA* via = new PCB_VIA( m_board );
m_board->Add( via, ADD_MODE::APPEND );
via->SetPosition( elem.position );
@ -2286,7 +2286,7 @@ void ALTIUM_PCB::ParseTracks6Data( const CFB::CompoundFileReader& aReader,
if( klayer >= F_Cu && klayer <= B_Cu )
{
TRACK* track = new TRACK( m_board );
PCB_TRACK* track = new PCB_TRACK( m_board );
m_board->Add( track, ADD_MODE::APPEND );
track->SetStart( elem.start );

47
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp
View File

@ -37,7 +37,7 @@
#include <pcb_group.h>
#include <pcb_text.h>
#include <project.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <convert_basic_shapes_to_polygon.h>
#include <trigo.h>
@ -2032,8 +2032,9 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadCoppers()
std::vector<PCB_SHAPE*> outlineSegments =
getDrawSegmentsFromVertices( csCopper.Shape.Vertices );
std::vector<TRACK*> outlineTracks = makeTracksFromDrawsegments( outlineSegments, m_board,
getKiCadNet( csCopper.NetRef.NetID ), getKiCadLayer( csCopper.LayerID ),
std::vector<PCB_TRACK*> outlineTracks = makeTracksFromDrawsegments( outlineSegments,
m_board, getKiCadNet( csCopper.NetRef.NetID ),
getKiCadLayer( csCopper.LayerID ),
getKiCadLength( getCopperCode( csCopper.CopperCodeID ).CopperWidth ) );
//cleanup
@ -2045,8 +2046,9 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadCoppers()
std::vector<PCB_SHAPE*> cutoutSeg =
getDrawSegmentsFromVertices( cutout.Vertices );
std::vector<TRACK*> cutoutTracks = makeTracksFromDrawsegments( cutoutSeg, m_board,
getKiCadNet( csCopper.NetRef.NetID ), getKiCadLayer( csCopper.LayerID ),
std::vector<PCB_TRACK*> cutoutTracks = makeTracksFromDrawsegments( cutoutSeg,
m_board, getKiCadNet( csCopper.NetRef.NetID ),
getKiCadLayer( csCopper.LayerID ),
getKiCadLength( getCopperCode( csCopper.CopperCodeID ).CopperWidth ) );
//cleanup
@ -2363,7 +2365,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNetTracks( const NET_ID& aCadstarNe
}
NETINFO_ITEM* net = getKiCadNet( aCadstarNetID );
std::vector<TRACK*> tracks = makeTracksFromDrawsegments( shapes, m_board, net );
std::vector<PCB_TRACK*> tracks = makeTracksFromDrawsegments( shapes, m_board, net );
//cleanup
for( PCB_SHAPE* shape : shapes )
@ -2374,7 +2376,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNetTracks( const NET_ID& aCadstarNe
int CADSTAR_PCB_ARCHIVE_LOADER::loadNetVia(
const NET_ID& aCadstarNetID, const NET_PCB::VIA& aCadstarVia )
{
VIA* via = new VIA( m_board );
PCB_VIA* via = new PCB_VIA( m_board );
m_board->Add( via, ADD_MODE::APPEND );
VIACODE csViaCode = getViaCode( aCadstarVia.ViaCodeID );
@ -2958,23 +2960,24 @@ SHAPE_LINE_CHAIN CADSTAR_PCB_ARCHIVE_LOADER::getLineChainFromDrawsegments( const
}
std::vector<TRACK*> CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments(
std::vector<PCB_TRACK*> CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments(
const std::vector<PCB_SHAPE*> aDrawsegments,
BOARD_ITEM_CONTAINER* aParentContainer,
NETINFO_ITEM* aNet, PCB_LAYER_ID aLayerOverride,
int aWidthOverride )
{
std::vector<TRACK*> tracks;
TRACK* prevTrack = nullptr;
TRACK* track = nullptr;
std::vector<PCB_TRACK*> tracks;
PCB_TRACK* prevTrack = nullptr;
PCB_TRACK* track = nullptr;
auto addTrack = [&]( TRACK* aTrack )
auto addTrack =
[&]( PCB_TRACK* aTrack )
{
// Ignore zero length tracks in the same way as the CADSTAR postprocessor
// does when generating gerbers. Note that CADSTAR reports these as "Route
// offset errors" when running a DRC within CADSTAR, so we shouldn't be
// getting this in general, however it is used to remove any synthetic
// points added to aDrawSegments by the caller of this function.
// Ignore zero length tracks in the same way as the CADSTAR postprocessor does
// when generating gerbers. Note that CADSTAR reports these as "Route offset
// errors" when running a DRC within CADSTAR, so we shouldn't be getting this in
// general, however it is used to remove any synthetic points added to
// aDrawSegments by the caller of this function.
if( aTrack->GetLength() != 0 )
{
tracks.push_back( aTrack );
@ -2995,25 +2998,25 @@ std::vector<TRACK*> CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments(
{
FP_SHAPE* em = (FP_SHAPE*) ds;
SHAPE_ARC arc( em->GetStart0(), em->GetEnd0(), (double) em->GetAngle() / 10.0 );
track = new ARC( aParentContainer, &arc );
track = new PCB_ARC( aParentContainer, &arc );
}
else
{
SHAPE_ARC arc( ds->GetCenter(), ds->GetArcStart(), (double) ds->GetAngle() / 10.0 );
track = new ARC( aParentContainer, &arc );
track = new PCB_ARC( aParentContainer, &arc );
}
break;
case PCB_SHAPE_TYPE::SEGMENT:
if( ds->GetClass() == wxT( "MGRAPHIC" ) )
{
FP_SHAPE* em = (FP_SHAPE*) ds;
track = new TRACK( aParentContainer );
track = new PCB_TRACK( aParentContainer );
track->SetStart( em->GetStart0() );
track->SetEnd( em->GetEnd0() );
}
else
{
track = new TRACK( aParentContainer );
track = new PCB_TRACK( aParentContainer );
track->SetStart( ds->GetStart() );
track->SetEnd( ds->GetEnd() );
}
@ -3067,7 +3070,7 @@ std::vector<TRACK*> CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments(
if( track->GetStart() != prevTrack->GetEnd() )
{
int minWidth = std::min( track->GetWidth(), prevTrack->GetWidth() );
TRACK* synthTrack = new TRACK( aParentContainer );
PCB_TRACK* synthTrack = new PCB_TRACK( aParentContainer );
synthTrack->SetStart( prevTrack->GetEnd() );
synthTrack->SetEnd( track->GetStart() );
synthTrack->SetWidth( minWidth );

2
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.h
View File

@ -363,7 +363,7 @@ private:
* in the DrawSegments
* @return
*/
std::vector<TRACK*> makeTracksFromDrawsegments( const std::vector<PCB_SHAPE*> aDrawsegments,
std::vector<PCB_TRACK*> makeTracksFromDrawsegments( const std::vector<PCB_SHAPE*> aDrawsegments,
BOARD_ITEM_CONTAINER* aParentContainer,
NETINFO_ITEM* aNet = nullptr,
PCB_LAYER_ID aLayerOverride = UNDEFINED_LAYER,

8
pcbnew/plugins/eagle/eagle_plugin.cpp
View File

@ -72,7 +72,7 @@ Load() TODO's
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <fp_shape.h>
#include <zone.h>
#include <pad_shapes.h>
@ -2366,7 +2366,7 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
wxPoint end( KiROUND( radius * cos( end_angle + angle ) + center.x ),
KiROUND( radius * sin( end_angle + angle ) + center.y ) );
TRACK* t = new TRACK( m_board );
PCB_TRACK* t = new PCB_TRACK( m_board );
t->SetPosition( start );
t->SetEnd( end );
@ -2380,7 +2380,7 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
angle -= delta_angle;
}
TRACK* t = new TRACK( m_board );
PCB_TRACK* t = new PCB_TRACK( m_board );
t->SetPosition( start );
t->SetEnd( wxPoint( kicad_x( w.x2 ), kicad_y( w.y2 ) ) );
@ -2411,7 +2411,7 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
{
int kidiam;
int drillz = v.drill.ToPcbUnits();
VIA* via = new VIA( m_board );
PCB_VIA* via = new PCB_VIA( m_board );
m_board->Add( via );
via->SetLayerPair( layer_front_most, layer_back_most );

8
pcbnew/plugins/fabmaster/import_fabmaster.cpp
View File

@ -48,7 +48,7 @@
#include <pad_shapes.h>
#include <pcb_shape.h>
#include <pcb_text.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <common.h>
#include <geometry/shape_arc.h>
@ -2391,7 +2391,7 @@ bool FABMASTER::loadVias( BOARD* aBoard )
auto net_it = netinfo.find( via->net );
auto padstack = pads.find( via->padstack );
VIA* new_via = new VIA( aBoard );
PCB_VIA* new_via = new PCB_VIA( aBoard );
new_via->SetPosition( wxPoint( via->x, via->y ) );
@ -2456,7 +2456,7 @@ bool FABMASTER::loadEtch( BOARD* aBoard, const std::unique_ptr<FABMASTER::TRACE>
{
const GRAPHIC_LINE* src = static_cast<const GRAPHIC_LINE*>( seg.get() );
TRACK* trk = new TRACK( aBoard );
PCB_TRACK* trk = new PCB_TRACK( aBoard );
trk->SetLayer( layer );
trk->SetStart( wxPoint( src->start_x, src->start_y ) );
@ -2472,7 +2472,7 @@ bool FABMASTER::loadEtch( BOARD* aBoard, const std::unique_ptr<FABMASTER::TRACE>
{
const GRAPHIC_ARC* src = static_cast<const GRAPHIC_ARC*>( seg.get() );
ARC* trk = new ARC( aBoard, &src->result );
PCB_ARC* trk = new PCB_ARC( aBoard, &src->result );
trk->SetLayer( layer );
trk->SetWidth( src->width );

14
pcbnew/plugins/kicad/kicad_plugin.cpp
View File

@ -46,7 +46,7 @@
#include <plugins/kicad/kicad_plugin.h>
#include <plugins/kicad/pcb_parser.h>
#include <trace_helpers.h>
#include <track.h>
#include <pcb_track.h>
#include <wildcards_and_files_ext.h>
#include <wx/dir.h>
#include <wx/log.h>
@ -444,7 +444,7 @@ void PCB_IO::Format( const BOARD_ITEM* aItem, int aNestLevel ) const
case PCB_TRACE_T:
case PCB_ARC_T:
case PCB_VIA_T:
format( static_cast<const TRACK*>( aItem ), aNestLevel );
format( static_cast<const PCB_TRACK*>( aItem ), aNestLevel );
break;
case PCB_FP_ZONE_T:
@ -650,7 +650,7 @@ void PCB_IO::format( const BOARD* aBoard, int aNestLevel ) const
aBoard->Footprints().end() );
std::set<BOARD_ITEM*, BOARD_ITEM::ptr_cmp> sorted_drawings( aBoard->Drawings().begin(),
aBoard->Drawings().end() );
std::set<TRACK*, TRACK::cmp_tracks> sorted_tracks( aBoard->Tracks().begin(),
std::set<PCB_TRACK*, PCB_TRACK::cmp_tracks> sorted_tracks( aBoard->Tracks().begin(),
aBoard->Tracks().end() );
std::set<BOARD_ITEM*, BOARD_ITEM::ptr_cmp> sorted_zones( aBoard->Zones().begin(),
aBoard->Zones().end() );
@ -675,7 +675,7 @@ void PCB_IO::format( const BOARD* aBoard, int aNestLevel ) const
// Do not save PCB_MARKERs, they can be regenerated easily.
// Save the tracks and vias.
for( TRACK* track : sorted_tracks )
for( PCB_TRACK* track : sorted_tracks )
Format( track, aNestLevel );
if( sorted_tracks.size() )
@ -1759,13 +1759,13 @@ void PCB_IO::format( const FP_TEXT* aText, int aNestLevel ) const
}
void PCB_IO::format( const TRACK* aTrack, int aNestLevel ) const
void PCB_IO::format( const PCB_TRACK* aTrack, int aNestLevel ) const
{
if( aTrack->Type() == PCB_VIA_T )
{
PCB_LAYER_ID layer1, layer2;
const VIA* via = static_cast<const VIA*>( aTrack );
const PCB_VIA* via = static_cast<const PCB_VIA*>( aTrack );
BOARD* board = (BOARD*) via->GetParent();
wxCHECK_RET( board != nullptr, wxT( "Via " ) +
@ -1826,7 +1826,7 @@ void PCB_IO::format( const TRACK* aTrack, int aNestLevel ) const
}
else if( aTrack->Type() == PCB_ARC_T )
{
const ARC* arc = static_cast<const ARC*>( aTrack );
const PCB_ARC* arc = static_cast<const PCB_ARC*>( aTrack );
std::string locked = arc->IsLocked() ? " locked" : "";
m_out->Print( aNestLevel, "(arc%s (start %s) (mid %s) (end %s) (width %s)",

4
pcbnew/plugins/kicad/kicad_plugin.h
View File

@ -42,7 +42,7 @@ class PCB_TARGET;
class PAD;
class FP_TEXT;
class PCB_GROUP;
class TRACK;
class PCB_TRACK;
class ZONE;
class PCB_TEXT;
@ -261,7 +261,7 @@ private:
void format( const FP_TEXT* aText, int aNestLevel = 0 ) const;
void format( const TRACK* aTrack, int aNestLevel = 0 ) const;
void format( const PCB_TRACK* aTrack, int aNestLevel = 0 ) const;
void format( const ZONE* aZone, int aNestLevel = 0 ) const;

32
pcbnew/plugins/kicad/pcb_parser.cpp
View File

@ -45,7 +45,7 @@
#include <footprint.h>
#include <netclass.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <plugins/kicad/kicad_plugin.h>
#include <pcb_plot_params_parser.h>
@ -679,7 +679,7 @@ BOARD* PCB_PARSER::parseBOARD_unchecked()
break;
case T_segment:
item = parseTRACK();
item = parsePCB_TRACK();
m_board->Add( item, ADD_MODE::BULK_APPEND );
bulkAddedItems.push_back( item );
break;
@ -695,7 +695,7 @@ BOARD* PCB_PARSER::parseBOARD_unchecked()
break;
case T_via:
item = parseVIA();
item = parsePCB_VIA();
m_board->Add( item, ADD_MODE::BULK_APPEND );
bulkAddedItems.push_back( item );
break;
@ -759,11 +759,11 @@ BOARD* PCB_PARSER::parseBOARD_unchecked()
}
};
for( auto segm : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
if( segm->Type() == PCB_VIA_T )
if( track->Type() == PCB_VIA_T )
{
VIA* via = (VIA*) segm;
PCB_VIA* via = static_cast<PCB_VIA*>( track );
PCB_LAYER_ID top_layer, bottom_layer;
if( via->GetViaType() == VIATYPE::THROUGH )
@ -788,7 +788,9 @@ BOARD* PCB_PARSER::parseBOARD_unchecked()
}
}
else
visitItem( segm );
{
visitItem( track );
}
}
for( BOARD_ITEM* zone : m_board->Zones() )
@ -4370,7 +4372,7 @@ void PCB_PARSER::parseGROUP( BOARD_ITEM* aParent )
}
ARC* PCB_PARSER::parseARC()
PCB_ARC* PCB_PARSER::parseARC()
{
wxCHECK_MSG( CurTok() == T_arc, NULL,
wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as ARC." ) );
@ -4378,7 +4380,7 @@ ARC* PCB_PARSER::parseARC()
wxPoint pt;
T token;
std::unique_ptr<ARC> arc = std::make_unique<ARC>( m_board );
std::unique_ptr<PCB_ARC> arc = std::make_unique<PCB_ARC>( m_board );
for( token = NextTok(); token != T_RIGHT; token = NextTok() )
{
@ -4454,15 +4456,15 @@ ARC* PCB_PARSER::parseARC()
}
TRACK* PCB_PARSER::parseTRACK()
PCB_TRACK* PCB_PARSER::parsePCB_TRACK()
{
wxCHECK_MSG( CurTok() == T_segment, NULL,
wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as TRACK." ) );
wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as PCB_TRACK." ) );
wxPoint pt;
T token;
std::unique_ptr<TRACK> track = std::make_unique<TRACK>( m_board );
std::unique_ptr<PCB_TRACK> track = std::make_unique<PCB_TRACK>( m_board );
for( token = NextTok(); token != T_RIGHT; token = NextTok() )
{
@ -4532,15 +4534,15 @@ TRACK* PCB_PARSER::parseTRACK()
}
VIA* PCB_PARSER::parseVIA()
PCB_VIA* PCB_PARSER::parsePCB_VIA()
{
wxCHECK_MSG( CurTok() == T_via, NULL,
wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as VIA." ) );
wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as PCB_VIA." ) );
wxPoint pt;
T token;
std::unique_ptr<VIA> via = std::make_unique<VIA>( m_board );
std::unique_ptr<PCB_VIA> via = std::make_unique<PCB_VIA>( m_board );
for( token = NextTok(); token != T_RIGHT; token = NextTok() )
{

12
pcbnew/plugins/kicad/pcb_parser.h
View File

@ -40,7 +40,7 @@
#include <unordered_map>
class ARC;
class PCB_ARC;
class BOARD;
class BOARD_ITEM;
class BOARD_ITEM_CONTAINER;
@ -52,11 +52,11 @@ class EDA_TEXT;
class FP_SHAPE;
class FP_TEXT;
class PCB_TEXT;
class TRACK;
class PCB_TRACK;
class FOOTPRINT;
class PCB_GROUP;
class PCB_TARGET;
class VIA;
class PCB_VIA;
class ZONE;
class FP_3DMODEL;
struct LAYER;
@ -199,9 +199,9 @@ private:
// Parse only the (option ...) inside a pad description
bool parsePAD_option( PAD* aPad );
ARC* parseARC();
TRACK* parseTRACK();
VIA* parseVIA();
PCB_ARC* parseARC();
PCB_TRACK* parsePCB_TRACK();
PCB_VIA* parsePCB_VIA();
ZONE* parseZONE( BOARD_ITEM_CONTAINER* aParent );
PCB_TARGET* parsePCB_TARGET();
BOARD* parseBOARD();

10
pcbnew/plugins/legacy/legacy_plugin.cpp
View File

@ -75,7 +75,7 @@
#include <board_design_settings.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <pcb_text.h>
#include <zone.h>
#include <pcb_dimension.h>
@ -2265,13 +2265,13 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType )
continue;
}
TRACK* newTrack;
PCB_TRACK* newTrack;
switch( makeType )
{
default:
case PCB_TRACE_T: newTrack = new TRACK( m_board ); break;
case PCB_VIA_T: newTrack = new VIA( m_board ); break;
case PCB_TRACE_T: newTrack = new PCB_TRACK( m_board ); break;
case PCB_VIA_T: newTrack = new PCB_VIA( m_board ); break;
}
const_cast<KIID&>( newTrack->m_Uuid ) = KIID( uuid );
@ -2282,7 +2282,7 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType )
if( makeType == PCB_VIA_T ) // Ensure layers are OK when possible:
{
VIA *via = static_cast<VIA*>( newTrack );
PCB_VIA *via = static_cast<PCB_VIA*>( newTrack );
via->SetViaType( viatype );
if( drill < 0 )

2
pcbnew/plugins/legacy/legacy_plugin.h
View File

@ -40,14 +40,12 @@
class PCB_TARGET;
class FOOTPRINT;
class TRACK;
class NETCLASS;
class NETCLASSES;
class ZONE;
class PCB_DIMENSION_BASE;
class NETINFO_ITEM;
class FP_TEXT;
class TRACK;
class PAD;
struct LP_CACHE;

4
pcbnew/plugins/pcad/pcb_line.cpp
View File

@ -30,7 +30,7 @@
#include <footprint.h>
#include <fp_shape.h>
#include <pcb_shape.h>
#include <track.h>
#include <pcb_track.h>
#include <xnode.h>
#include <wx/string.h>
@ -138,7 +138,7 @@ void PCB_LINE::AddToBoard()
{
if( IsCopperLayer( m_KiCadLayer ) )
{
TRACK* track = new TRACK( m_board );
PCB_TRACK* track = new PCB_TRACK( m_board );
m_board->Add( track );
track->SetPosition( wxPoint( m_positionX, m_positionY ) );

4
pcbnew/plugins/pcad/pcb_pad.cpp
View File

@ -29,7 +29,7 @@
#include <board.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <trigo.h>
#include <xnode.h>
@ -346,7 +346,7 @@ void PCB_PAD::AddToBoard()
if( IsCopperLayer( m_KiCadLayer ) )
{
VIA* via = new VIA( m_board );
PCB_VIA* via = new PCB_VIA( m_board );
m_board->Add( via );
via->SetPosition( wxPoint( m_positionX, m_positionY ) );

8
pcbnew/python/scripting/pcbnew_action_plugins.cpp
View File

@ -26,7 +26,7 @@
#include <board.h>
#include <board_commit.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <menus_helpers.h>
#include <pcbnew_settings.h>
@ -216,7 +216,7 @@ void PCB_EDIT_FRAME::RunActionPlugin( ACTION_PLUGIN* aActionPlugin )
bool fromEmpty = false;
// Append tracks:
for( TRACK* item : currentPcb->Tracks() )
for( PCB_TRACK* item : currentPcb->Tracks() )
{
ITEM_PICKER picker( nullptr, item, UNDO_REDO::CHANGED );
itemsList.PushItem( picker );
@ -277,7 +277,7 @@ void PCB_EDIT_FRAME::RunActionPlugin( ACTION_PLUGIN* aActionPlugin )
std::set<BOARD_ITEM*> currItemList;
// Append tracks:
for( TRACK* item : currentPcb->Tracks() )
for( PCB_TRACK* item : currentPcb->Tracks() )
currItemList.insert( item );
// Append footprints:
@ -324,7 +324,7 @@ void PCB_EDIT_FRAME::RunActionPlugin( ACTION_PLUGIN* aActionPlugin )
}
}
for( TRACK* item : currentPcb->Tracks() )
for( PCB_TRACK* item : currentPcb->Tracks() )
{
if( !oldBuffer->ContainsItem( item ) )
{

30
pcbnew/python/swig/board_item.i
View File

@ -74,9 +74,9 @@ class MARKER_PCB;
class BOARD;
class FP_SHAPE;
class PAD;
class TRACK;
class VIA;
class ARC;
class PCB_TRACK;
class PCB_VIA;
class PCB_ARC;
class ZONE;
class FP_ZONE;
class PCB_TARGET;
@ -100,9 +100,9 @@ static PCB_MARKER* Cast_to_PCB_MARKER( BOARD_ITEM* );
static BOARD* Cast_to_BOARD( BOARD_ITEM* );
static FP_SHAPE* Cast_to_FP_SHAPE( BOARD_ITEM* );
static PAD* Cast_to_PAD( BOARD_ITEM* );
static TRACK* Cast_to_TRACK( BOARD_ITEM* );
static VIA* Cast_to_VIA( BOARD_ITEM* );
static ARC* Cast_to_ARC( BOARD_ITEM* );
static PCB_TRACK* Cast_to_PCB_TRACK( BOARD_ITEM* );
static PCB_VIA* Cast_to_PCB_VIA( BOARD_ITEM* );
static PCB_ARC* Cast_to_PCB_ARC( BOARD_ITEM* );
static ZONE* Cast_to_ZONE( BOARD_ITEM* );
static FP_ZONE* Cast_to_FP_ZONE( BOARD_ITEM* );
static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* );
@ -126,9 +126,9 @@ static PCB_MARKER* Cast_to_PCB_MARKER( BOARD_ITEM* );
static BOARD* Cast_to_BOARD( BOARD_ITEM* );
static FP_SHAPE* Cast_to_FP_SHAPE( BOARD_ITEM* );
static PAD* Cast_to_PAD( BOARD_ITEM* );
static TRACK* Cast_to_TRACK( BOARD_ITEM* );
static VIA* Cast_to_VIA( BOARD_ITEM* );
static ARC* Cast_to_ARC( BOARD_ITEM* );
static PCB_TRACK* Cast_to_PCB_TRACK( BOARD_ITEM* );
static PCB_VIA* Cast_to_PCB_VIA( BOARD_ITEM* );
static PCB_ARC* Cast_to_PCB_ARC( BOARD_ITEM* );
static ZONE* Cast_to_ZONE( BOARD_ITEM* );
static FP_ZONE* Cast_to_FP_ZONE( BOARD_ITEM* );
static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* );
@ -167,11 +167,11 @@ static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* );
elif ct=="MTEXT":
return Cast_to_FP_TEXT(self)
elif ct=="VIA":
return Cast_to_VIA(self)
return Cast_to_PCB_VIA(self)
elif ct=="TRACK":
return Cast_to_TRACK(self)
return Cast_to_PCB_TRACK(self)
elif ct=="ARC":
return Cast_to_ARC(self)
return Cast_to_PCB_ARC(self)
elif ct=="PCB_TARGET":
return Cast_to_PCB_TARGET(self)
elif ct=="ZONE":
@ -217,9 +217,9 @@ static PCB_MARKER* Cast_to_PCB_MARKER( BOARD_ITEM* self ) {
static BOARD* Cast_to_BOARD( BOARD_ITEM* self ) { return dynamic_cast<BOARD*>(self); }
static FP_SHAPE* Cast_to_FP_SHAPE( BOARD_ITEM* self ) { return dynamic_cast<FP_SHAPE*>(self); }
static PAD* Cast_to_PAD( BOARD_ITEM* self ) { return dynamic_cast<PAD*>(self); }
static TRACK* Cast_to_TRACK( BOARD_ITEM* self ) { return dynamic_cast<TRACK*>(self); }
static VIA* Cast_to_VIA( BOARD_ITEM* self ) { return dynamic_cast<VIA*>(self); }
static ARC* Cast_to_ARC( BOARD_ITEM* self ) { return dynamic_cast<ARC*>(self); }
static PCB_TRACK* Cast_to_PCB_TRACK( BOARD_ITEM* self ) { return dynamic_cast<PCB_TRACK *>(self); }
static PCB_VIA* Cast_to_PCB_VIA( BOARD_ITEM* self ) { return dynamic_cast<PCB_VIA *>(self); }
static PCB_ARC* Cast_to_PCB_ARC( BOARD_ITEM* self ) { return dynamic_cast<PCB_ARC *>(self); }
static ZONE* Cast_to_ZONE( BOARD_ITEM* self ) { return dynamic_cast<ZONE*>(self); }
static FP_ZONE* Cast_to_FP_ZONE( BOARD_ITEM* self ) { return dynamic_cast<FP_ZONE*>(self); }
static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* self ) { return dynamic_cast<PCB_TARGET*>(self); }

6
pcbnew/python/swig/track.i
View File

@ -1,8 +1,8 @@
%include track.h
%rename(Get) operator TRACK*;
%include pcb_track.h
%rename(Get) operator PCB_TRACK*;
%{
#include <track.h>
#include <pcb_track.h>
%}

3
pcbnew/ratsnest/ratsnest.cpp
View File

@ -26,7 +26,6 @@
#include <macros.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcbnew.h>
#include <ratsnest/ratsnest_data.h>
@ -43,8 +42,6 @@ void PCB_BASE_FRAME::Compile_Ratsnest( bool aDisplayStatus )
GetBoard()->GetConnectivity()->RecalculateRatsnest();
if( aDisplayStatus )
{
SetMsgPanel( m_pcb );
}
}

38
pcbnew/router/pns_kicad_iface.cpp
View File

@ -25,7 +25,7 @@
#include <fp_text.h>
#include <footprint.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <pcb_shape.h>
#include <pcb_text.h>
@ -94,9 +94,9 @@ private:
private:
PNS::ROUTER_IFACE* m_routerIface;
BOARD* m_board;
TRACK m_dummyTracks[2];
ARC m_dummyArcs[2];
VIA m_dummyVias[2];
PCB_TRACK m_dummyTracks[2];
PCB_ARC m_dummyArcs[2];
PCB_VIA m_dummyVias[2];
int m_clearanceEpsilon;
std::map<std::pair<const PNS::ITEM*, const PNS::ITEM*>, int> m_clearanceCache;
@ -136,7 +136,7 @@ int PNS_PCBNEW_RULE_RESOLVER::holeRadius( const PNS::ITEM* aItem ) const
}
else if( aItem->Kind() == PNS::ITEM::VIA_T )
{
const ::VIA* via = dynamic_cast<const ::VIA*>( aItem->Parent() );
const PCB_VIA* via = dynamic_cast<const PCB_VIA*>( aItem->Parent() );
if( via )
return via->GetDrillValue() / 2;
@ -963,7 +963,7 @@ std::unique_ptr<PNS::SOLID> PNS_KICAD_IFACE_BASE::syncPad( PAD* aPad )
}
std::unique_ptr<PNS::SEGMENT> PNS_KICAD_IFACE_BASE::syncTrack( TRACK* aTrack )
std::unique_ptr<PNS::SEGMENT> PNS_KICAD_IFACE_BASE::syncTrack( PCB_TRACK* aTrack )
{
auto segment = std::make_unique<PNS::SEGMENT>( SEG( aTrack->GetStart(), aTrack->GetEnd() ),
aTrack->GetNetCode() );
@ -979,7 +979,7 @@ std::unique_ptr<PNS::SEGMENT> PNS_KICAD_IFACE_BASE::syncTrack( TRACK* aTrack )
}
std::unique_ptr<PNS::ARC> PNS_KICAD_IFACE_BASE::syncArc( ARC* aArc )
std::unique_ptr<PNS::ARC> PNS_KICAD_IFACE_BASE::syncArc( PCB_ARC* aArc )
{
auto arc = std::make_unique<PNS::ARC>( SHAPE_ARC( aArc->GetStart(), aArc->GetMid(), aArc->GetEnd(),
aArc->GetWidth() ),
@ -995,7 +995,7 @@ std::unique_ptr<PNS::ARC> PNS_KICAD_IFACE_BASE::syncArc( ARC* aArc )
}
std::unique_ptr<PNS::VIA> PNS_KICAD_IFACE_BASE::syncVia( VIA* aVia )
std::unique_ptr<PNS::VIA> PNS_KICAD_IFACE_BASE::syncVia( PCB_VIA* aVia )
{
PCB_LAYER_ID top, bottom;
aVia->LayerPair( &top, &bottom );
@ -1220,7 +1220,7 @@ bool PNS_KICAD_IFACE::IsFlashedOnLayer( const PNS::ITEM* aItem, int aLayer ) con
{
case PCB_VIA_T:
{
const VIA* via = static_cast<const VIA*>( aItem->Parent() );
const PCB_VIA* via = static_cast<const PCB_VIA*>( aItem->Parent() );
return via->FlashLayer( static_cast<PCB_LAYER_ID>( aLayer ) );
}
@ -1336,7 +1336,7 @@ void PNS_KICAD_IFACE_BASE::SyncWorld( PNS::NODE *aWorld )
}
}
for( TRACK* t : m_board->Tracks() )
for( PCB_TRACK* t : m_board->Tracks() )
{
KICAD_T type = t->Type();
@ -1347,12 +1347,12 @@ void PNS_KICAD_IFACE_BASE::SyncWorld( PNS::NODE *aWorld )
}
else if( type == PCB_ARC_T )
{
if( auto arc = syncArc( static_cast<ARC*>( t ) ) )
if( auto arc = syncArc( static_cast<PCB_ARC*>( t ) ) )
aWorld->Add( std::move( arc ) );
}
else if( type == PCB_VIA_T )
{
if( auto via = syncVia( static_cast<VIA*>( t ) ) )
if( auto via = syncVia( static_cast<PCB_VIA*>( t ) ) )
aWorld->Add( std::move( via ) );
}
}
@ -1494,7 +1494,7 @@ void PNS_KICAD_IFACE::UpdateItem( PNS::ITEM* aItem )
case PNS::ITEM::ARC_T:
{
PNS::ARC* arc = static_cast<PNS::ARC*>( aItem );
ARC* arc_board = static_cast<ARC*>( board_item );
PCB_ARC* arc_board = static_cast<PCB_ARC*>( board_item );
const SHAPE_ARC* arc_shape = static_cast<const SHAPE_ARC*>( arc->Shape() );
arc_board->SetStart( wxPoint( arc_shape->GetP0() ) );
arc_board->SetEnd( wxPoint( arc_shape->GetP1() ) );
@ -1506,7 +1506,7 @@ void PNS_KICAD_IFACE::UpdateItem( PNS::ITEM* aItem )
case PNS::ITEM::SEGMENT_T:
{
PNS::SEGMENT* seg = static_cast<PNS::SEGMENT*>( aItem );
TRACK* track = static_cast<TRACK*>( board_item );
PCB_TRACK* track = static_cast<PCB_TRACK*>( board_item );
const SEG& s = seg->Seg();
track->SetStart( wxPoint( s.A.x, s.A.y ) );
track->SetEnd( wxPoint( s.B.x, s.B.y ) );
@ -1516,7 +1516,7 @@ void PNS_KICAD_IFACE::UpdateItem( PNS::ITEM* aItem )
case PNS::ITEM::VIA_T:
{
VIA* via_board = static_cast<VIA*>( board_item );
PCB_VIA* via_board = static_cast<PCB_VIA*>( board_item );
PNS::VIA* via = static_cast<PNS::VIA*>( aItem );
via_board->SetPosition( wxPoint( via->Pos().x, via->Pos().y ) );
via_board->SetWidth( via->Diameter() );
@ -1559,8 +1559,8 @@ void PNS_KICAD_IFACE::AddItem( PNS::ITEM* aItem )
{
case PNS::ITEM::ARC_T:
{
auto arc = static_cast<PNS::ARC*>( aItem );
ARC* new_arc = new ARC( m_board, static_cast<const SHAPE_ARC*>( arc->Shape() ) );
PNS::ARC* arc = static_cast<PNS::ARC*>( aItem );
PCB_ARC* new_arc = new PCB_ARC( m_board, static_cast<const SHAPE_ARC*>( arc->Shape() ) );
new_arc->SetWidth( arc->Width() );
new_arc->SetLayer( ToLAYER_ID( arc->Layers().Start() ) );
new_arc->SetNetCode( std::max<int>( 0, arc->Net() ) );
@ -1571,7 +1571,7 @@ void PNS_KICAD_IFACE::AddItem( PNS::ITEM* aItem )
case PNS::ITEM::SEGMENT_T:
{
PNS::SEGMENT* seg = static_cast<PNS::SEGMENT*>( aItem );
TRACK* track = new TRACK( m_board );
PCB_TRACK* track = new PCB_TRACK( m_board );
const SEG& s = seg->Seg();
track->SetStart( wxPoint( s.A.x, s.A.y ) );
track->SetEnd( wxPoint( s.B.x, s.B.y ) );
@ -1584,7 +1584,7 @@ void PNS_KICAD_IFACE::AddItem( PNS::ITEM* aItem )
case PNS::ITEM::VIA_T:
{
VIA* via_board = new VIA( m_board );
PCB_VIA* via_board = new PCB_VIA( m_board );
PNS::VIA* via = static_cast<PNS::VIA*>( aItem );
via_board->SetPosition( wxPoint( via->Pos().x, via->Pos().y ) );
via_board->SetWidth( via->Diameter() );

6
pcbnew/router/pns_kicad_iface.h
View File

@ -90,9 +90,9 @@ protected:
PNS::DEBUG_DECORATOR* m_debugDecorator;
std::unique_ptr<PNS::SOLID> syncPad( PAD* aPad );
std::unique_ptr<PNS::SEGMENT> syncTrack( TRACK* aTrack );
std::unique_ptr<PNS::ARC> syncArc( ARC* aArc );
std::unique_ptr<PNS::VIA> syncVia( VIA* aVia );
std::unique_ptr<PNS::SEGMENT> syncTrack( PCB_TRACK* aTrack );
std::unique_ptr<PNS::ARC> syncArc( PCB_ARC* aArc );
std::unique_ptr<PNS::VIA> syncVia( PCB_VIA* aVia );
bool syncTextItem( PNS::NODE* aWorld, EDA_TEXT* aText, PCB_LAYER_ID aLayer );
bool syncGraphicalItem( PNS::NODE* aWorld, PCB_SHAPE* aItem );
bool syncZone( PNS::NODE* aWorld, ZONE* aZone, SHAPE_POLY_SET* aBoardOutline );

2
pcbnew/router/pns_sizes_settings.h
View File

@ -25,7 +25,7 @@
#include <map>
#include <core/optional.h>
#include "track.h" // for VIATYPE_T
#include "pcb_track.h" // for VIATYPE_T
class BOARD;
class BOARD_DESIGN_SETTINGS;

2
pcbnew/router/pns_via.h
View File

@ -26,7 +26,7 @@
#include <geometry/shape_circle.h>
#include <math/box2.h>
#include "track.h"
#include "pcb_track.h"
#include "pns_item.h"

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