Translated using Weblate (Chinese (Simplified))
Currently translated at 99.9% (6989 of 6990 strings) Translation: KiCad EDA/master source Translate-URL: https://hosted.weblate.org/projects/kicad/master-source/zh_Hans/
This commit is contained in:
Rigo Ligo
Hosted Weblate
parent
fe215add24
commit
1757631652
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@ -11,7 +11,7 @@ msgstr ""
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"Report-Msgid-Bugs-To: \n"
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"POT-Creation-Date: 2021-06-10 13:22-0700\n"
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"PO-Revision-Date: 2021-06-18 13:11+0000\n"
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"Last-Translator: taotieren <admin@taotieren.com>\n"
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"Last-Translator: Rigo Ligo <rigoligo03@gmail.com>\n"
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"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
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"kicad/master-source/zh_Hans/>\n"
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"Language: zh_CN\n"
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@ -20231,7 +20231,7 @@ msgstr "锁定"
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#: pcbnew/board_stackup_manager/board_stackup.cpp:306
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#, c-format
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msgid "Dielectric %d"
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msgstr "Dielectric %d"
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msgstr "电介质层 %d"
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#: pcbnew/board_stackup_manager/board_stackup.cpp:526
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msgid "Top Silk Screen"
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@ -26507,7 +26507,7 @@ msgstr "如果选中，区域将在使用区域属性对话框编辑区域的属
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#: pcbnew/dialogs/panel_fp_editor_color_settings.cpp:130
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msgid "Internal Layers"
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msgstr "Internal Layers"
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msgstr "内层"
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#: pcbnew/dialogs/panel_fp_editor_defaults.cpp:325
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msgid ""
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@ -27491,6 +27491,7 @@ msgid "Check rule syntax"
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msgstr "检查规则语法"
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#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
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#, fuzzy
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msgid ""
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"### Top-level Clauses\n"
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"\n"
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@ -27698,209 +27699,205 @@ msgid ""
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" (constraint clearance (min \"1.5mm\"))\n"
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" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
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msgstr ""
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"### Top-level Clauses\n"
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"### 顶层语句\n"
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"\n"
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" (version <number>)\n"
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" 版本语句：(version <版本号>)\n"
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"\n"
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" (rule <rule_name> <rule_clause> ...)\n"
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" 规则语句：(rule <规则名> <规则语句> ...)\n"
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"\n"
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"\n"
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"<br><br>\n"
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"\n"
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"### Rule Clauses\n"
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"### 规则语句\n"
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"\n"
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" (constraint <constraint_type> ...)\n"
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" 约束语句：(constraint <约束类型> ...)\n"
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"\n"
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" (condition \"<expression>\")\n"
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" 条件语句：(condition \"<条件表达式>\")\n"
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"\n"
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" (layer \"<layer_name>\")\n"
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" 层语句：(layer \"<层名>\")\n"
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"\n"
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"\n"
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"<br><br>\n"
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"\n"
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"### Constraint Types\n"
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"### 约束类型\n"
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"\n"
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" * annular_width\n"
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" * clearance\n"
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" * courtyard_clearance\n"
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" * diff\\_pair\\_gap\n"
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" * annular_width （孔铜环宽度）\n"
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" * clearance （间隙）\n"
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" * courtyard_clearance （封装外框之间的间隙）\n"
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" * diff\\_pair\\_gap （差分对间隙）\n"
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" * diff\\_pair\\_uncoupled\n"
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" * disallow\n"
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" * edge_clearance\n"
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" * length\n"
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" * hole\n"
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" * hole_clearance\n"
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" * silk_clearance\n"
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" * skew\n"
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" * track_width\n"
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" * via_count\n"
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" * disallow （不允许）\n"
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" * edge_clearance （与板边的间隙）\n"
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" * length （长度）\n"
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" * hole （孔）\n"
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" * hole_clearance （与孔的间隙）\n"
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" * silk_clearance （与丝印的间隙）\n"
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" * skew （偏移）\n"
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" * track_width （线宽）\n"
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" * via_count （过孔个数）\n"
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"\n"
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"\n"
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"<br><br>\n"
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"\n"
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"### Item Types\n"
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"### 电路板元素类型\n"
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"\n"
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" * buried_via\n"
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" * graphic\n"
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" * hole\n"
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" * micro_via\n"
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" * pad\n"
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" * text\n"
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" * track\n"
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" * via\n"
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" * zone\n"
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" * buried_via （埋孔）\n"
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" * graphic （图形）\n"
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" * hole （孔）\n"
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" * micro_via （微孔）\n"
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" * pad （焊盘）\n"
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" * text （文字）\n"
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" * track （布线）\n"
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" * via （过孔）\n"
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" * zone （区域）\n"
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"\n"
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"<br>\n"
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"\n"
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"### Examples\n"
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"### 范例\n"
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"\n"
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" (version 1)\n"
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"\n"
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" (rule HV\n"
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" (rule 高压间距\n"
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" (constraint clearance (min 1.5mm))\n"
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" (condition \"A.NetClass == 'HV'\"))\n"
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"\n"
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"\n"
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" (rule HV\n"
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" (rule 外层高压间距\n"
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" (layer outer)\n"
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" (constraint clearance (min 1.5mm))\n"
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" (condition \"A.NetClass == 'HV'\"))\n"
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"\n"
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"\n"
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" (rule HV_HV\n"
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" # wider clearance between HV tracks\n"
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" (rule 高压之间间距\n"
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" # 高压线路之间间距应该更大\n"
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" (constraint clearance (min \"1.5mm + 2.0mm\"))\n"
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" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n"
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"\n"
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"\n"
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" (rule HV_unshielded\n"
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" (rule 无护罩高压线路\n"
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" (constraint clearance (min 2mm))\n"
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" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n"
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"<br><br>\n"
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"\n"
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"### Notes\n"
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"### \n"
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"\n"
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"Version clause must be the first clause. It indicates the syntax version of "
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"the file so that \n"
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"future rules parsers can perform automatic updates. It should be\n"
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"set to \"1\".\n"
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"版本语句标志着文件的语法版本，所以版本语句必须是第一个语句，\n"
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"以便将来的 KiCad 解析新版本的规则文件。版本应设为“1”。\n"
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"\n"
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"Rules should be ordered by specificity. Later rules take\n"
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"precedence over earlier rules; once a matching rule is found\n"
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"no further rules will be checked.\n"
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"规则应该以优先级排序。后面的规则优先于前面的规则；\n"
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"且一旦检测到某个规则成功匹配，则其余的规则均被忽略。\n"
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"\n"
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"Use Ctrl+/ to comment or uncomment line(s).\n"
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"使用 Ctrl+/ 来对选中的行添加或取消注释。\n"
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"<br><br><br>\n"
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"\n"
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"### Expression functions\n"
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"### 表达式函数\n"
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"\n"
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"All function parameters support simple wildcards (`*` and `?`).\n"
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"函数的参数均支持简单的通配符（`*` 和 `?`）。\n"
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"<br><br>\n"
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"\n"
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" A.insideCourtyard('<footprint_refdes>')\n"
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"True if any part of `A` lies within the given footprint's principal "
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"courtyard.\n"
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" A.insideCourtyard('<封装标号>')\n"
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"若 `A` 的任何部分落在指定封装的主要外框中，则为真。\n"
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"<br><br>\n"
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"\n"
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" A.insideFrontCourtyard('<footprint_refdes>')\n"
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"True if any part of `A` lies within the given footprint's front courtyard.\n"
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"若 `A` 的任何部分落在指定封装的顶层外框中，则为真。\n"
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"<br><br>\n"
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"\n"
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" A.insideBackCourtyard('<footprint_refdes>')\n"
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"True if any part of `A` lies within the given footprint's back courtyard.\n"
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"若 `A` 的任何部分落在指定封装的底层外框中，则为真。\n"
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"<br><br>\n"
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"\n"
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" A.insideArea('<zone_name>')\n"
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"True if any part of `A` lies within the given zone's outline.\n"
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"若 `A` 的任何部分落在指定区域中，则为真。\n"
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"<br><br>\n"
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"\n"
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" A.isPlated()\n"
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"True if `A` has a hole which is plated.\n"
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"若 `A` 含/是铜孔，则为真。\n"
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"<br><br>\n"
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"\n"
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" A.inDiffPair('<net_name>')\n"
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"True if `A` has net that is part of the specified differential pair.\n"
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"`<net_name>` is the base name of the differential pair. For example, "
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"`inDiffPair('CLK')`\n"
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" A.inDiffPair('<网络名>')\n"
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"若 `A` 含有指定差分对的网络，则为真。\n"
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"`<网络名>` 是指定差分对的基础名称。例如， `inDiffPair('CLK')`\n"
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"matches items in the `CLK_P` and `CLK_N` nets.\n"
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"<br><br>\n"
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"\n"
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" AB.isCoupledDiffPair()\n"
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"True if `A` and `B` are members of the same diff pair.\n"
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"若 `A` 和 `B` 分别具有同一差分对的两个网络，则为真。\n"
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"<br><br>\n"
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"\n"
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" A.memberOf('<group_name>')\n"
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"True if `A` is a member of the given group. Includes nested membership.\n"
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" A.memberOf('<组名>')\n"
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"若 `A` 是指定组中的成员，则为真。组内嵌套的组也包括在内。\n"
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"<br><br>\n"
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"\n"
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" A.existsOnLayer('<layer_name>')\n"
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"True if `A` exists on the given layer. The layer name can be\n"
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"either the name assigned in Board Setup > Board Editor Layers or\n"
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"the canonical name (ie: `F.Cu`).\n"
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" A.existsOnLayer('<层名>')\n"
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"若 `A` 在指定的层中，则为真。层名可以是“电路板设置 >\n"
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"电路板编辑图层”菜单中指定的名称，也可以是内部最简名称\n"
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"（如 `F.Cu`）。\n"
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"\n"
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"注：不论是否正在检查指定的层，只要 `A` 在该层上，\n"
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"此条件即为真。对这样的使用场景，请在规则中使用\n"
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"`(layer \"层名\")`。\n"
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"\n"
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"NB: this returns true if `A` is on the given layer, independently\n"
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"of whether or not the rule is being evaluated for that layer.\n"
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"For the latter use a `(layer \"layer_name\")` clause in the rule.\n"
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"<br><br><br>\n"
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"\n"
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"### More Examples\n"
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"### 更多的范例\n"
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"\n"
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" (rule \"copper keepout\"\n"
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" (rule \"禁止铜区\"\n"
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" (constraint disallow track via zone)\n"
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" (condition \"A.insideArea('zone3')\"))\n"
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"\n"
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"\n"
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" (rule \"BGA neckdown\"\n"
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" (rule \"BGA加粗\"\n"
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" (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
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" (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
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" (condition \"A.insideCourtyard('U3')\"))\n"
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"\n"
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"\n"
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" # prevent silk over tented vias\n"
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" # 禁止盖油过孔上印字\n"
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" (rule silk_over_via\n"
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" (constraint silk_clearance (min 0.2mm))\n"
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" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
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"\n"
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"\n"
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" (rule \"Distance between Vias of Different Nets\" \n"
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" (rule \"不同网络的过孔的间距\" \n"
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" (constraint hole_to_hole (min 0.254mm))\n"
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" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
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"\n"
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" (rule \"Clearance between Pads of Different Nets\" \n"
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" (rule \"不同网络的焊盘的间距\" \n"
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" (constraint clearance (min 3.0mm))\n"
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" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
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"\n"
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"\n"
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" (rule \"Via Hole to Track Clearance\" \n"
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" (rule \"过孔到焊盘的间距\" \n"
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" (constraint hole_clearance (min 0.254mm))\n"
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" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
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" \n"
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" (rule \"Pad to Track Clearance\" \n"
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" (rule \"焊盘到导线的间距\" \n"
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" (constraint clearance (min 0.2mm))\n"
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" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
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"\n"
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"\n"
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" (rule \"clearance-to-1mm-cutout\"\n"
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" (rule \"1mm宽开槽周围的间距\"\n"
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" (constraint clearance (min 0.8mm))\n"
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" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
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"\n"
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"\n"
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" (rule \"Max Drill Hole Size Mechanical\" \n"
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" (rule \"最大机械孔孔径\" \n"
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" (constraint hole (max 6.3mm))\n"
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" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
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" \n"
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" (rule \"Max Drill Hole Size PTH\" \n"
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" (rule \"最大铜孔孔径\" \n"
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" (constraint hole (max 6.35mm))\n"
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" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
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"\n"
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"\n"
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" # Specify an optimal gap for a particular diff-pair\n"
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" (rule \"dp clock gap\"\n"
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" # 给单独的差分对设置最优（opt）间距\n"
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" (rule \"CLK信号间距\"\n"
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" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
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" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
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"\n"
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" # Specify a larger clearance around any diff-pair\n"
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" (rule \"dp clearance\"\n"
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" # 给任意差分对周围扩大间距\n"
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" (rule \"差分对外间距\"\n"
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" (constraint clearance (min \"1.5mm\"))\n"
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" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
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@ -28653,7 +28650,7 @@ msgstr "正在测试 %d 丝印功能针对 %d 个电路板项目。"
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#: pcbnew/drc/drc_test_provider_silk_to_mask.cpp:100
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msgid "Checking silkscreen for potential soldermask clipping..."
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msgstr "正在检查丝网印是否存在潜在的阻焊裁剪..."
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msgstr "正在检查丝印是否可能与开窗区相交..."
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#: pcbnew/drc/drc_test_provider_silk_to_mask.cpp:182
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#, c-format
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@ -29519,7 +29516,7 @@ msgstr "未知(%d)"
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#: pcbnew/kicad_clipboard.cpp:406
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msgid "Clipboard content is not KiCad compatible"
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msgstr "剪贴板内容不兼容 KiCad"
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msgstr "剪贴板内容与 KiCad 不兼容"
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#: pcbnew/load_select_footprint.cpp:265
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#, c-format
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@ -32945,7 +32942,7 @@ msgstr "带位号复制"
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#: pcbnew/tools/pcb_actions.cpp:265
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msgid "Copy selected item(s) to clipboard with a specified starting point"
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msgstr "将选定项目复制到具有指定起始点的剪贴板"
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msgstr "将选定项目及指定的起始点复制到剪贴板"
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#: pcbnew/tools/pcb_actions.cpp:271
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msgid "Duplicate and Increment"
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Loading…
Reference in New Issue