Translated using Weblate (Chinese (Simplified))
Currently translated at 98.5% (7230 of 7336 strings) Translation: KiCad EDA/master source Translate-URL: https://hosted.weblate.org/projects/kicad/master-source/zh_Hans/
This commit is contained in:
taotieren
Hosted Weblate
parent
4462f26cfd
commit
34ac49f0fb
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@ -1,7 +1,7 @@
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# SOME DESCRIPTIVE TITLE.
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# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER
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# This file is distributed under the same license as the PACKAGE package.
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# taotieren <admin@taotieren.com>,2019-2020, 2021.
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# taotieren <admin@taotieren.com>,2019-2020, 2021, 2022.
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# Rigo Ligo <rigoligo03@gmail.com>, 2020, 2021, 2022.
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# Eric <spice2wolf@gmail.com>, 2020, 2021.
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# Liu Guang <l.g110@163.com>, 2021.
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@ -19,7 +19,7 @@ msgstr ""
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"Report-Msgid-Bugs-To: \n"
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"POT-Creation-Date: 2022-01-13 10:05-0800\n"
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"PO-Revision-Date: 2022-01-14 10:30+0000\n"
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"Last-Translator: Eric <alchemillatruth@purelymail.com>\n"
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"Last-Translator: taotieren <admin@taotieren.com>\n"
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"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
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"kicad/master-source/zh_Hans/>\n"
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"Language: zh_CN\n"
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@ -1672,7 +1672,7 @@ msgstr "取消 (&C)"
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#: common/dialog_shim.cpp:661
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msgid "&Yes"
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msgstr ""
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msgstr "是 (&Y)"
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#: common/dialog_shim.cpp:662
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msgid "&No"
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@ -2953,7 +2953,7 @@ msgstr "(这个临时解决方案将改善一些 GTK HiDPI 字体缩放问题。
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#: common/dialogs/panel_common_settings_base.cpp:171
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msgid "High-contrast mode dimming factor:"
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msgstr ""
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msgstr "高对比度模式的调光系数："
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#: common/dialogs/panel_common_settings_base.cpp:178
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#: eeschema/dialogs/panel_setup_formatting_base.cpp:75
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@ -6023,7 +6023,7 @@ msgstr "网格属性..."
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#: common/tool/actions.cpp:481
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msgid "Set grid dimensions"
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msgstr "设置网格标注"
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msgstr "设置网格尺寸"
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#: common/tool/actions.cpp:486
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msgid "Use inches"
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@ -8552,7 +8552,7 @@ msgstr "设置为"
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#: pcbnew/dialogs/dialog_global_edit_text_and_graphics_base.cpp:170
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#: pcbnew/dialogs/dialog_text_properties_base.cpp:108
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msgid "Font:"
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msgstr ""
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msgstr "字体："
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#: eeschema/dialogs/dialog_global_edit_text_and_graphics_base.cpp:173
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#: eeschema/dialogs/dialog_label_properties_base.cpp:188
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@ -8923,7 +8923,7 @@ msgstr "点"
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#: eeschema/dialogs/dialog_label_properties_base.cpp:167
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msgid "Diamond"
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msgstr ""
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msgstr "菱形"
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#: eeschema/dialogs/dialog_label_properties_base.cpp:177
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#: eeschema/dialogs/dialog_schematic_setup.cpp:71
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@ -12038,7 +12038,7 @@ msgstr "Gap 长度："
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#: eeschema/dialogs/panel_setup_formatting_base.cpp:237
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#: pcbnew/dialogs/panel_setup_formatting_base.cpp:45
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msgid "Dash and dot lengths are ratios of the line width."
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msgstr ""
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msgstr "虚线和点长度是线条宽度的比率。"
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#: eeschema/dialogs/panel_setup_pinmap.cpp:169
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msgid "No error or warning"
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@ -12077,7 +12077,7 @@ msgstr "默认线宽 (&D)："
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msgid ""
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"Set to 0 to allow symbols to inherit their line widths from\n"
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"their parent Schematic"
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msgstr ""
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msgstr "设置为 0 可允许符号继承其父系原理图的线宽"
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#: eeschema/dialogs/panel_sym_editing_options_base.cpp:55
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msgid "D&efault pin length:"
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@ -20523,7 +20523,6 @@ msgstr ""
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"是否要退出并放弃变更？"
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#: pcb_calculator/tracks_width_versus_current_formula.h:2
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#, fuzzy
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msgid ""
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"If you specify the maximum current, then the trace widths will be calculated "
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"to suit.\n"
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@ -20550,23 +20549,21 @@ msgid ""
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msgstr ""
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"如果你指定最大电流，则会计算相应的布线宽度。\n"
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"\n"
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"如果你指定其中一个布线宽度，则将计算它可以处理的最大电流。然后将计算另外的同"
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"样处理此电流的布线宽度。\n"
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"如果你指定其中一个布线宽度，则将计算它可以处理的最大电流。然后将计算另外的同样处理此电流的布线宽度。\n"
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"\n"
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"控制值以粗体显示。\n"
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"\n"
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"计算适用于最大 35A（外部）或 17.5A（内部）的电流、高达 100 °C的温升和最多 "
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"400mil（10mm）的宽度。\n"
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"计算适用于最大 35A（外部）或 17.5A（内部）的电流、高达 100 °C的温升和最多 400mil（10mm）的宽度。\n"
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"\n"
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"来自 IPC 2221的该公式，为\n"
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"<center>___I = K ⋅ ΔT<sup>0.44</sup> ⋅ (W ⋅ "
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"H)<sup>0.725</sup>___</center> \n"
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"IPC 2221 中的公式为\n"
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"<center>___I = K ⋅ ΔT<sup>0.44</sup> ⋅ (W ⋅ H)<sup>0."
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"725</sup>___</center> \n"
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"其中： \n"
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"__I__ = 最大电流（单位：A 安培） \n"
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"__ΔT__ = 环境温度温升（单位：°C 摄氏度） \n"
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"__W__ = 布线的宽度 （单位：mil 密耳）\n"
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"__H__ = 布线的厚度 （单位：mil 密耳）\n"
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"__K__ = 0.024 用于内部布线，0.048 用于外部布线 \n"
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"__K__ = 0.024 用于内部布线，0.048 用于外部布线\n"
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#: pcb_calculator/transline_dlg_funct.cpp:140
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msgid "Dielectric Loss Factor"
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@ -21369,23 +21366,23 @@ msgstr "黄色"
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#: pcbnew/board_stackup_manager/stackup_predefined_prms.cpp:78
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msgid "FR4 natural"
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msgstr ""
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msgstr "FR4 自然色"
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#: pcbnew/board_stackup_manager/stackup_predefined_prms.cpp:79
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msgid "PTFE natural"
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msgstr ""
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msgstr "聚四氟乙烯自然色"
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#: pcbnew/board_stackup_manager/stackup_predefined_prms.cpp:80
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msgid "Polyimide"
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msgstr "聚酰亚胺"
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msgstr "聚酰亚胺自然色"
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#: pcbnew/board_stackup_manager/stackup_predefined_prms.cpp:81
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msgid "Phenolic natural"
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msgstr ""
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msgstr "酚类自然色"
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#: pcbnew/board_stackup_manager/stackup_predefined_prms.cpp:82
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msgid "Aluminum"
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msgstr ""
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msgstr "铝自然色"
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#: pcbnew/board_stackup_manager/stackup_predefined_prms.h:53
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msgid "Not specified"
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@ -23296,7 +23293,7 @@ msgstr ": (无更改)"
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#: pcbnew/dialogs/dialog_exchange_footprints.cpp:400
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msgid ": OK"
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msgstr ""
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msgstr ": OK"
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#: pcbnew/dialogs/dialog_exchange_footprints_base.cpp:24
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msgid "Update all footprints on board"
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@ -23884,12 +23881,12 @@ msgstr "从 BOM 中排除"
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:206
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:210
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msgid "Exempt from courtyard requirement"
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msgstr ""
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msgstr "排除外框要求"
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:207
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:211
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msgid "Will not generate \"missing courtyard\" DRC violations"
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msgstr ""
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msgstr "不会产生“缺失外框”的 DRC 违规行为"
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:223
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msgid "Update Footprint from Library..."
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@ -23951,7 +23948,7 @@ msgstr ""
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:298
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:269
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msgid "Allow bridged solder mask apertures between pads"
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msgstr ""
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msgstr "允许焊盘之间的桥接阻焊孔径"
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:301
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:272
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@ -24863,7 +24860,7 @@ msgstr "设计规则约束"
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#: pcbnew/dialogs/dialog_import_settings_base.cpp:64
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msgid "Predefined track && via dimensions"
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msgstr "预定义的走线和过孔标注"
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msgstr "预定义的走线和过孔尺寸"
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#: pcbnew/dialogs/dialog_imported_layers.cpp:243
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#: pcbnew/dialogs/dialog_imported_layers.cpp:251
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@ -25769,7 +25766,7 @@ msgstr "来自父级封装"
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:716
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msgid "Zone knockout:"
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msgstr ""
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msgstr "敷铜挖空："
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:720
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msgid "Pad shape"
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@ -25788,14 +25785,12 @@ msgid "Relief gap:"
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msgstr "防散热间距："
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:752
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#, fuzzy
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msgid "Spoke width:"
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msgstr "Spoke 宽度："
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msgstr "辐条 (散热) 宽度："
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:763
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#, fuzzy
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msgid "Spoke angle:"
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msgstr "Spoke 角度："
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msgstr "辐条 (散热) 角度："
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:797
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msgid "Primitives list:"
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@ -27457,9 +27452,7 @@ msgstr "模仿旧行为"
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msgid ""
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"Produces a slightly smoother outline at the expense of performance, some "
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"export fidelity issues, and overly aggressive higher-priority zone knockouts."
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msgstr ""
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"以牺牲性能、一些导出保真度问题和过于激进的高优先级区域挖空为代价，生成稍微平"
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"滑的轮廓。"
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msgstr "以牺牲性能、一些导出保真度问题和过于激进的高优先级敷铜挖空为代价，生成稍微平滑的轮廓。"
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:116
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msgid "Smoothed polygons (best performance)"
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@ -27476,9 +27469,8 @@ msgid "Allow fillets outside zone outline"
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msgstr "允许圆角超出敷铜轮廓"
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:146
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#, fuzzy
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msgid "Min thermal relief spoke count:"
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msgstr "花焊盘最小 spoke 数目："
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msgstr "花焊盘最小辐条 (散热) 数目："
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:165
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msgid "Length tuning"
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@ -28299,12 +28291,11 @@ msgstr "阻焊层到铜间隙："
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#: pcbnew/dialogs/panel_setup_mask_and_paste_base.cpp:95
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msgid "Allow bridged solder mask apertures between pads within footprints"
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msgstr ""
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msgstr "允许在封装内的焊盘之间桥接阻焊孔径"
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#: pcbnew/dialogs/panel_setup_mask_and_paste_base.cpp:98
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#, fuzzy
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msgid "Tent vias"
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msgstr "不允许过孔盖油"
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msgstr "过孔盖油"
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#: pcbnew/dialogs/panel_setup_mask_and_paste_base.cpp:103
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msgid ""
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@ -28370,7 +28361,6 @@ msgid "Check rule syntax"
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msgstr "检查规则语法"
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#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
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#, fuzzy
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msgid ""
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"### Top-level Clauses\n"
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"\n"
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@ -28658,7 +28648,7 @@ msgstr ""
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"# 规则语句：(rule <规则名> <规则语句> ...)\n"
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"\n"
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"\n"
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"<br><br>\n"
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"<br>\n"
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"\n"
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"### Rule Clauses\n"
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"### 规则语句\n"
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@ -28673,7 +28663,7 @@ msgstr ""
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"# 层语句：(layer \"<层名>\")\n"
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"\n"
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"\n"
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"<br><br>\n"
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"<br>\n"
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"\n"
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"### Constraint Types\n"
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"### 约束类型\n"
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@ -28694,21 +28684,44 @@ msgstr ""
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"# （与板边的间隙）\n"
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" * length\n"
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"# （长度）\n"
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" * hole\n"
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"# （通孔）\n"
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" * hole\\_clearance\n"
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"# （与通孔的间隙）\n"
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" * hole\\_size\n"
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"# （通孔尺寸）\n"
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" * mechanical\\_clearance\n"
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"# （机械间隙）\n"
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" * mechanical\\_hole\\_clearance\n"
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"# （机械孔间隙）\n"
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" * min\\_resolved\\_spokes\n"
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"# （与辐条（散热）最小解析）\n"
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" * silk\\_clearance\n"
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"# （与丝印的间隙）\n"
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" * skew\n"
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"# （总偏差）\n"
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" * text\\_height\n"
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"# （文本高度）\n"
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" * text\\_thickness\n"
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"# （文本宽度）\n"
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" * thermal\\_relief\\_gap\n"
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"# （散热（花焊盘）间隙）\n"
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" * thermal\\_spoke\\_width\n"
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"# （散热辐条宽度）\n"
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" * track\\_width\n"
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"# （布线线宽）\n"
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" * via\\_count\n"
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"# （过孔个数）\n"
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"# （过孔计数）\n"
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" * via\\_diameter\n"
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"# （过孔直径）\n"
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" * zone\\_connection\n"
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"# （敷铜连接）\n"
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"\n"
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"\n"
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"<br><br>\n"
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"Note: `clearance` and `hole_clearance` rules are not run against items of "
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"the same net; `mechanical_clearance` and `mechanical_hole_clearance` rules "
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"are.\n"
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"# 注：`clearance(间隙)` 和 `hole_clearance (过孔间隙)` 规则不是针对同一网中的项目运行，`"
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"mechanical_clearance (机械间隙)` 和 `mechanical_hole_clearance (机械孔间隙)` "
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"规则是针对同一网络中的项目运行的。\n"
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"<br>\n"
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"\n"
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"### Item Types\n"
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"### 电路板元素类型\n"
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@ -28734,6 +28747,32 @@ msgstr ""
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"\n"
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"<br>\n"
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"\n"
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"### Zone Connections\n"
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"### 敷铜连接\n"
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"\n"
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" * solid\n"
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"# （实心敷铜）\n"
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" * thermal\\_reliefs\n"
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"# （散热（花焊盘））\n"
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" * none\n"
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"# （无）\n"
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"\n"
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"<br>\n"
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"\n"
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"### Severity Names\n"
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"### 严重性名称\n"
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"\n"
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" * warning\n"
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"# （警告）\n"
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" * error\n"
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"# （错误）\n"
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" * exclusion\n"
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"# （拒绝）\n"
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" * ignore\n"
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"# （忽略）\n"
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"\n"
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"<br>\n"
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"\n"
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"### Examples\n"
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"### 范例\n"
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"\n"
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@ -28764,9 +28803,17 @@ msgstr ""
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"# (rule 无护罩高压线路\n"
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" (constraint clearance (min 2mm))\n"
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" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n"
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||||
"\n"
|
||||
"\n"
|
||||
" (rule heavy_thermals\n"
|
||||
"# (rule 强散热\n"
|
||||
" (constraint thermal_spoke_width (min 0.5mm))\n"
|
||||
" (condition \"A.NetClass == 'HV'\"))\n"
|
||||
"\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
"### \n"
|
||||
"### Notes\n"
|
||||
"### 注意\n"
|
||||
"\n"
|
||||
"版本语句标志着文件的语法版本，所以版本语句必须是第一个语句，\n"
|
||||
"以便将来的 KiCad 解析新版本的规则文件。版本应设为“1”。\n"
|
||||
|
|
@ -28877,7 +28924,7 @@ msgstr ""
|
|||
"\n"
|
||||
"\n"
|
||||
" (rule \"clearance-to-1mm-cutout\"\n"
|
||||
"# (rule \"1mm宽开槽周围的间距\"\n"
|
||||
"# (rule \"1mm 宽开槽周围的间距\"\n"
|
||||
" (constraint clearance (min 0.8mm))\n"
|
||||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28906,6 +28953,44 @@ msgstr ""
|
|||
"# (rule \"差分对外间距\"\n"
|
||||
" (constraint clearance (min \"1.5mm\"))\n"
|
||||
" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" # Don't use thermal reliefs on heatsink pads\n"
|
||||
" # 不要在散热焊盘上使用散热片\n"
|
||||
" (rule heat_sink_pad\n"
|
||||
" (constraint zone_connection solid)\n"
|
||||
" (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n"
|
||||
"\n"
|
||||
" # Require all four thermal relief spokes to connect to parent zone\n"
|
||||
" # 需要所有四个散热辐条才能连接到父系敷铜\n"
|
||||
" (rule fully_spoked_pads\n"
|
||||
" (constraint min_resolved_spokes 4))\n"
|
||||
"\n"
|
||||
" # Set thermal relief gap & spoke width for all zones\n"
|
||||
" # 设置所有敷铜的散热间隙和辐条宽度\n"
|
||||
" (rule defined_relief\n"
|
||||
" (constraint thermal_relief_gap (min 10mil))\n"
|
||||
" (constraint thermal_spoke_width (min 12mil)))\n"
|
||||
"\n"
|
||||
" # Override thermal relief gap & spoke width for GND and PWR zones\n"
|
||||
" # 覆盖 GND 和 PWR 敷铜的散热间隙和辐条宽度\n"
|
||||
" (rule defined_relief_pwr\n"
|
||||
" (constraint thermal_relief_gap (min 10mil))\n"
|
||||
" (constraint thermal_spoke_width (min 12mil))\n"
|
||||
" (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n"
|
||||
" \n"
|
||||
"\n"
|
||||
" # Prevent solder wicking from SMD pads\n"
|
||||
" # 防止 SMD 焊盘的焊芯脱落\n"
|
||||
" (rule holes_in_pads\n"
|
||||
" (constraint mechanical_hole_clearance (min 0.2mm))\n"
|
||||
" (condition \"B.Pad_Type == 'SMD'\"))\n"
|
||||
"\n"
|
||||
" # Disallow solder mask margin overrides\n"
|
||||
" # 禁止阻焊层边距覆盖\n"
|
||||
" (rule \"disallow solder mask margin overrides\"\n"
|
||||
" (constraint assertion \"A.Soldermask_Margin_Override == 0mm\")\n"
|
||||
" (condition \"A.Type == 'Pad'\"))"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72
|
||||
msgid "Default properties for new dimension objects:"
|
||||
|
|
@ -28952,7 +29037,7 @@ msgstr "没有定义差分对间距。"
|
|||
|
||||
#: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:19
|
||||
msgid "Pre-defined track and via dimensions:"
|
||||
msgstr "预定义布线和过孔标注："
|
||||
msgstr "预定义布线和过孔尺寸："
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:54
|
||||
#: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:111
|
||||
|
|
|
|||
Loading…
Reference in New Issue