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Edit microvia: fix incorrect drill size (Bug #1466653) 

Fix a few coverity minor warnings.
This commit is contained in:
jean-pierre charras 2015-06-19 10:55:37 +02:00
parent e211a77d8b
commit 355bd47e16
4 changed files with 16 additions and 5 deletions
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12
pcbnew/edit_track_width.cpp
View File

@ -73,6 +73,12 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
{
const VIA *via = static_cast<const VIA *>( aTrackItem );
// Micro vias have a size only defined in their netclass
// (no specific values defined by a table of specific value)
// Ensure the netcall is accessible:
if( via->GetViaType() == VIA_MICROVIA && net == NULL )
net = aTrackItem->GetNet();
// Get the draill value, regardless it is default or specific
initial_drill = via->GetDrillValue();
@ -96,14 +102,16 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem,
new_drill = net->GetMicroViaDrillSize();
}
else
new_width = GetDesignSettings().GetCurrentMicroViaSize();
{
// Should not occur
}
}
// Old versions set a drill value <= 0, when the default netclass it used
// but it could be better to set the drill value to the actual value
// to avoid issues for existing vias, if the default drill value is modified
// in the netclass, and not in current vias.
if( via->GetDrill() <= 0 ) // means default netclass drill value used
if( via->GetDrill() <= 0 ) // means default netclass drill value used
{
initial_drill = -1; // Force drill vias re-initialization
}

1
pcbnew/exporters/gen_modules_placefile.cpp
View File

@ -99,6 +99,7 @@ public:
m_parent( aParent ),
m_plotOpts( aParent->GetPlotSettings() )
{
m_reporter = &m_messagesPanel->Reporter();
initDialog();
GetSizer()->SetSizeHints(this);

5
pcbnew/pcb_draw_panel_gal.cpp
View File

@ -219,12 +219,13 @@ void PCB_DRAW_PANEL_GAL::DisplayBoard( const BOARD* aBoard )
UseColorScheme( aBoard->GetColorsSettings() );
PCB_BASE_FRAME* frame = dynamic_cast<PCB_BASE_FRAME*>( GetParent() );
SetTopLayer( frame->GetActiveLayer() );
if( frame )
{
SetTopLayer( frame->GetActiveLayer() );
DISPLAY_OPTIONS* displ_opts = (DISPLAY_OPTIONS*) frame->GetDisplayOptions();
static_cast<KIGFX::PCB_RENDER_SETTINGS*>( m_view->GetPainter()->GetSettings() )->LoadDisplayOptions( displ_opts );
static_cast<KIGFX::PCB_RENDER_SETTINGS*>(
m_view->GetPainter()->GetSettings() )->LoadDisplayOptions( displ_opts );
}
m_view->RecacheAllItems( true );

3
pcbnew/router/pns_meander_placer_base.cpp
View File

@ -25,6 +25,7 @@
PNS_MEANDER_PLACER_BASE::PNS_MEANDER_PLACER_BASE( PNS_ROUTER* aRouter ) :
PNS_PLACEMENT_ALGO( aRouter )
{
m_currentWidth = 0;
}
@ -69,7 +70,7 @@ void PNS_MEANDER_PLACER_BASE::cutTunedLine( const SHAPE_LINE_CHAIN& aOrigin,
if ( cp == aTuneStart ) // we don't like tuning segments with 0 length
{
int idx = aOrigin.FindSegment( cp );
if( idx >= 0 )
if( idx >= 0 )
{
const SEG& s = aOrigin.CSegment( idx );
cp += (s.B - s.A).Resize(2);