Add diode model to rectifier demo (ngspice-32 fix)
Patch by Holger Vogt Fixes https://gitlab.com/kicad/code/kicad/issues/4453
This commit is contained in:
Johannes Maibaum
Wayne Stambaugh
parent
9d78aa604f
commit
48150389b1
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*generic diode model
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.model 1N4148 D
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@ -1,101 +1,101 @@
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EESchema-LIBRARY Version 2.4
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#encoding utf-8
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#
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#
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# C
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# rectifier_schlib_C
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#
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#
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DEF C C 0 10 N Y 1 F N
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DEF rectifier_schlib_C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F0 "C" 25 100 50 H V L CNN
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F1 "C" 25 -100 50 H V L CNN
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F1 "rectifier_schlib_C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H V C CNN
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F2 "" 38 -150 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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$FPLIST
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C?
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C?
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C_????_*
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C_????_*
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C_????
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C_????
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SMD*_c
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SMD*_c
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Capacitor*
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Capacitor*
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Capacitors_ThroughHole:C_Radial_D10_L13_P5
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Capacitors_ThroughHole:C_Radial_D10_L13_P5
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Capacitors_SMD:C_0805
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Capacitors_SMD:C_0805
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Capacitors_SMD:C_1206
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Capacitors_SMD:C_1206
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$ENDFPLIST
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$ENDFPLIST
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DRAW
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 40 40 1 1 P
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X ~ 1 0 150 110 D 40 40 1 1 P
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X ~ 2 0 -150 110 U 40 40 1 1 P
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X ~ 2 0 -150 110 U 40 40 1 1 P
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ENDDRAW
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ENDDRAW
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ENDDEF
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ENDDEF
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#
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#
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# D
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# rectifier_schlib_D
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#
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#
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DEF D D 0 40 N N 1 F N
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DEF rectifier_schlib_D D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F0 "D" 0 100 50 H V C CNN
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F1 "D" 0 -100 50 H V C CNN
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F1 "rectifier_schlib_D" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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$FPLIST
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Diode_*
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Diode_*
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D-Pak_TO252AA
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D-Pak_TO252AA
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*SingleDiode
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*SingleDiode
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*_Diode_*
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*_Diode_*
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*SingleDiode*
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*SingleDiode*
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$ENDFPLIST
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$ENDFPLIST
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DRAW
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DRAW
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P 2 0 1 6 -50 50 -50 -50 N
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P 2 0 1 6 -50 50 -50 -50 N
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P 3 0 1 0 50 50 -50 0 50 -50 F
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P 3 0 1 0 50 50 -50 0 50 -50 F
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X K 1 -150 0 100 R 50 50 1 1 P
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDRAW
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ENDDEF
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ENDDEF
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#
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#
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# GND
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# rectifier_schlib_GND
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#
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#
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DEF GND #PWR 0 0 Y Y 1 F P
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DEF rectifier_schlib_GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -150 50 H I C CNN
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F0 "#PWR" 0 -150 50 H I C CNN
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F1 "GND" 0 -123 30 H V C CNN
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F1 "rectifier_schlib_GND" 0 -123 30 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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DRAW
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 20 30 1 1 W N
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X GND 1 0 0 0 D 20 30 1 1 W N
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ENDDRAW
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ENDDRAW
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ENDDEF
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ENDDEF
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#
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#
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# R
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# rectifier_schlib_R
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#
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#
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DEF R R 0 0 N Y 1 F N
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DEF rectifier_schlib_R R 0 0 N Y 1 F N
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F0 "R" 80 0 50 V V C CNN
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F0 "R" 80 0 50 V V C CNN
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F1 "R" 0 0 50 V V C CNN
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F1 "rectifier_schlib_R" 0 0 50 V V C CNN
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F2 "" -70 0 50 V V C CNN
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F2 "" -70 0 50 V V C CNN
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F3 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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$FPLIST
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R_*
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R_*
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Resistor_*
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Resistor_*
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$ENDFPLIST
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$ENDFPLIST
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DRAW
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DRAW
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S -40 -100 40 100 0 1 10 N
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S -40 -100 40 100 0 1 10 N
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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ENDDRAW
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ENDDRAW
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ENDDEF
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ENDDEF
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#
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#
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# VSOURCE
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# rectifier_schlib_VSOURCE
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#
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#
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DEF ~VSOURCE V 0 40 Y Y 1 F N
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DEF rectifier_schlib_VSOURCE V 0 40 Y Y 1 F N
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F0 "V" 200 200 50 H V C CNN
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F0 "V" 200 200 50 H V C CNN
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F1 "VSOURCE" 250 100 50 H I C CNN
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F1 "rectifier_schlib_VSOURCE" 250 100 50 H I C CNN
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F2 "" 0 0 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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F4 "Value" 0 0 60 H I C CNN "Fieldname"
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F4 "Value" 0 0 60 H I C CNN "Fieldname"
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F5 "V" 0 0 60 H I C CNN "Spice_Primitive"
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F5 "V" 0 0 60 H I C CNN "Spice_Primitive"
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F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence"
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F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence"
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DRAW
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DRAW
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C 0 0 100 0 1 0 N
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C 0 0 100 0 1 0 N
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P 2 0 1 0 0 -75 0 75 N
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P 2 0 1 0 0 -75 0 75 N
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P 4 0 1 0 0 75 -25 25 25 25 0 75 F
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P 4 0 1 0 0 75 -25 25 25 25 0 75 F
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X ~ 1 0 200 100 D 50 50 1 1 I
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X ~ 1 0 200 100 D 50 50 1 1 I
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X ~ 2 0 -200 100 U 50 50 1 1 I
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X ~ 2 0 -200 100 U 50 50 1 1 I
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ENDDRAW
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ENDDRAW
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ENDDEF
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ENDDEF
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#
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#
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#End Library
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#End Library
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@ -1,129 +1,137 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:rectifier-cache
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EELAYER 30 0
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EELAYER 26 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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encoding utf-8
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encoding utf-8
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Sheet 1 1
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Sheet 1 1
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Title ""
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Title ""
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Date ""
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Date ""
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Rev ""
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Rev ""
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Comp ""
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Comp ""
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Comment1 ""
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Comment1 ""
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Comment2 ""
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Comment2 ""
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Comment3 ""
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Comment3 ""
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Comment4 ""
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Comment4 ""
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$EndDescr
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$EndDescr
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$Comp
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$Comp
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L rectifier_schlib:VSOURCE V1
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L rectifier_schlib:VSOURCE V1
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U 1 1 57336052
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U 1 1 57336052
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P 4400 4050
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P 4400 4050
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F 0 "V1" H 4528 4096 50 0000 L CNN
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F 0 "V1" H 4528 4096 50 0000 L CNN
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F 1 "SINE(0 1.5 1k 0 0 0 0)" H 4528 4005 50 0000 L CNN
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F 1 "SINE(0 1.5 1k 0 0 0 0)" H 4528 4005 50 0000 L CNN
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F 2 "" H 4400 4050 50 0000 C CNN
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F 2 "" H 4400 4050 50 0000 C CNN
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F 3 "" H 4400 4050 50 0000 C CNN
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F 3 "" H 4400 4050 50 0000 C CNN
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F 4 "Value" H 4400 4050 60 0001 C CNN "Fieldname"
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F 4 "Value" H 4400 4050 60 0001 C CNN "Fieldname"
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F 5 "V" H 4400 4050 60 0001 C CNN "Spice_Primitive"
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F 5 "V" H 4400 4050 60 0001 C CNN "Spice_Primitive"
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F 6 "1 2" H 4100 4250 60 0001 C CNN "Spice_Node_Sequence"
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F 6 "1 2" H 4100 4250 60 0001 C CNN "Spice_Node_Sequence"
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1 4400 4050
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1 4400 4050
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-1 0 0 1
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-1 0 0 1
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$EndComp
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$EndComp
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$Comp
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$Comp
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L rectifier_schlib:GND #PWR01
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L rectifier_schlib:GND #PWR01
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U 1 1 573360D3
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U 1 1 573360D3
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P 4400 4350
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P 4400 4350
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F 0 "#PWR01" H 4400 4100 50 0001 C CNN
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F 0 "#PWR01" H 4400 4100 50 0001 C CNN
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F 1 "GND" H 4405 4177 50 0000 C CNN
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F 1 "GND" H 4405 4177 50 0000 C CNN
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F 2 "" H 4400 4350 50 0000 C CNN
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F 2 "" H 4400 4350 50 0000 C CNN
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F 3 "" H 4400 4350 50 0000 C CNN
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F 3 "" H 4400 4350 50 0000 C CNN
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1 4400 4350
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1 4400 4350
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1 0 0 -1
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1 0 0 -1
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$EndComp
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$EndComp
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$Comp
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$Comp
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L rectifier_schlib:R R1
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L rectifier_schlib:R R1
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U 1 1 573360F5
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U 1 1 573360F5
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P 4650 3700
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P 4650 3700
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F 0 "R1" V 4443 3700 50 0000 C CNN
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F 0 "R1" V 4443 3700 50 0000 C CNN
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F 1 "1k" V 4534 3700 50 0000 C CNN
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F 1 "1k" V 4534 3700 50 0000 C CNN
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F 2 "" V 4580 3700 50 0000 C CNN
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F 2 "" V 4580 3700 50 0000 C CNN
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F 3 "" H 4650 3700 50 0000 C CNN
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F 3 "" H 4650 3700 50 0000 C CNN
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F 4 "Value" H 4650 3700 60 0001 C CNN "Fieldname"
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F 4 "Value" H 4650 3700 60 0001 C CNN "Fieldname"
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F 5 "1 2" H 4650 3700 60 0001 C CNN "SpiceMapping"
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F 5 "1 2" H 4650 3700 60 0001 C CNN "SpiceMapping"
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F 6 "R" V 4650 3700 60 0001 C CNN "Spice_Primitive"
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F 6 "R" V 4650 3700 60 0001 C CNN "Spice_Primitive"
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1 4650 3700
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1 4650 3700
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0 1 1 0
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0 1 1 0
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$EndComp
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$EndComp
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$Comp
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$Comp
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L rectifier_schlib:D D1
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L rectifier_schlib:D D1
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U 1 1 573361B8
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U 1 1 573361B8
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P 5100 3700
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P 5100 3700
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F 0 "D1" H 5100 3485 50 0000 C CNN
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F 0 "D1" H 5100 3485 50 0000 C CNN
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F 1 "1N4148" H 5100 3576 50 0000 C CNN
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F 1 "1N4148" H 5100 3576 50 0000 C CNN
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F 2 "" H 5100 3700 50 0000 C CNN
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F 2 "" H 5100 3700 50 0000 C CNN
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F 3 "" H 5100 3700 50 0000 C CNN
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F 3 "" H 5100 3700 50 0000 C CNN
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F 4 "Value" H 5100 3700 60 0001 C CNN "Fieldname"
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F 4 "Value" H 5100 3700 60 0001 C CNN "Fieldname"
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F 5 "D" H 5100 3700 60 0001 C CNN "Spice_Primitive"
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F 5 "D" H 5100 3700 60 0001 C CNN "Spice_Primitive"
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F 6 "2 1" H 5100 3700 60 0001 C CNN "Spice_Node_Sequence"
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F 6 "2 1" H 5100 3700 60 0001 C CNN "Spice_Node_Sequence"
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F 7 "1N4148" H 5100 3700 50 0001 C CNN "Spice_Model"
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1 5100 3700
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F 8 "Y" H 5100 3700 50 0001 C CNN "Spice_Netlist_Enabled"
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-1 0 0 1
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F 9 "diode.mod" H 5100 3700 50 0001 C CNN "Spice_Lib_File"
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$EndComp
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1 5100 3700
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$Comp
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-1 0 0 1
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L rectifier_schlib:C C1
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$EndComp
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U 1 1 5733628F
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$Comp
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P 5400 4000
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L rectifier_schlib:C C1
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F 0 "C1" H 5515 4046 50 0000 L CNN
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U 1 1 5733628F
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F 1 "100n" H 5515 3955 50 0000 L CNN
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P 5400 4000
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F 2 "" H 5438 3850 50 0000 C CNN
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F 0 "C1" H 5515 4046 50 0000 L CNN
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F 3 "" H 5400 4000 50 0000 C CNN
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F 1 "100n" H 5515 3955 50 0000 L CNN
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F 4 "Value" H 5400 4000 60 0001 C CNN "Fieldname"
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F 2 "" H 5438 3850 50 0000 C CNN
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F 5 "C" H 5400 4000 60 0001 C CNN "Spice_Primitive"
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F 3 "" H 5400 4000 50 0000 C CNN
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F 6 "1 2" H 5400 4000 60 0001 C CNN "SpiceMapping"
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F 4 "Value" H 5400 4000 60 0001 C CNN "Fieldname"
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1 5400 4000
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F 5 "C" H 5400 4000 60 0001 C CNN "Spice_Primitive"
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1 0 0 -1
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F 6 "1 2" H 5400 4000 60 0001 C CNN "SpiceMapping"
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$EndComp
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1 5400 4000
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$Comp
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1 0 0 -1
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L rectifier_schlib:R R2
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$EndComp
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U 1 1 573362F7
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$Comp
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P 5750 4000
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L rectifier_schlib:R R2
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F 0 "R2" H 5680 3954 50 0000 R CNN
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U 1 1 573362F7
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F 1 "100k" H 5680 4045 50 0000 R CNN
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P 5750 4000
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F 2 "" V 5680 4000 50 0000 C CNN
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F 0 "R2" H 5680 3954 50 0000 R CNN
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F 3 "" H 5750 4000 50 0000 C CNN
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F 1 "100k" H 5680 4045 50 0000 R CNN
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F 4 "Value" H 5750 4000 60 0001 C CNN "Fieldname"
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F 2 "" V 5680 4000 50 0000 C CNN
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F 5 "1 2" H 5750 4000 60 0001 C CNN "SpiceMapping"
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F 3 "" H 5750 4000 50 0000 C CNN
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F 6 "R" V 5750 4000 60 0001 C CNN "Spice_Primitive"
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F 4 "Value" H 5750 4000 60 0001 C CNN "Fieldname"
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1 5750 4000
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F 5 "1 2" H 5750 4000 60 0001 C CNN "SpiceMapping"
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-1 0 0 1
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F 6 "R" V 5750 4000 60 0001 C CNN "Spice_Primitive"
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$EndComp
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1 5750 4000
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Text Notes 4300 4900 0 60 ~ 0
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-1 0 0 1
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.tran 1u 10m\n
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$EndComp
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Wire Wire Line
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Text Notes 4300 4900 0 60 ~ 0
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.tran 1u 10m\n
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Wire Wire Line
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Wire Wire Line
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4400 4350 4400 4300
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Connection ~ 4400 4300
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Wire Wire Line
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Wire Wire Line
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4400 4300 5400 4300
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Connection ~ 4400 4300
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Wire Wire Line
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Wire Wire Line
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5750 3700 5750 3850
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5250 3700 5400 3700
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Wire Wire Line
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Wire Wire Line
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5400 3850 5400 3700
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5750 3700 5750 3850
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Connection ~ 5400 3700
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Wire Wire Line
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Wire Wire Line
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5400 3850 5400 3700
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5400 4300 5400 4150
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Connection ~ 5400 3700
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Wire Wire Line
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Wire Wire Line
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5750 4300 5750 4150
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5400 4300 5400 4150
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Connection ~ 5400 4300
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Wire Wire Line
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Wire Wire Line
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5750 4300 5750 4150
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Connection ~ 5400 4300
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Wire Wire Line
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Wire Wire Line
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4400 3850 4400 3700
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Wire Wire Line
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Wire Wire Line
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4400 3700 4500 3700
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Text Label 4400 3700 2 60 ~ 0
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Wire Wire Line
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signal_in
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Text Label 5750 3700 0 60 ~ 0
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Text Label 4400 3700 2 60 ~ 0
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rect_out
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signal_in
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Text Notes 4300 5000 0 60 ~ 0
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Text Label 5750 3700 0 60 ~ 0
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*.ac dec 10 1 1Meg\n
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rect_out
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$EndSCHEMATC
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Text Notes 4300 5000 0 60 ~ 0
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*.ac dec 10 1 1Meg\n
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Wire Wire Line
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4400 4300 4400 4250
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Wire Wire Line
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5400 3700 5750 3700
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Wire Wire Line
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5400 4300 5750 4300
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$EndSCHEMATC
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||||||
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