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fixed a problem when loading a module from lib having some pads with an old netname

This commit is contained in:
charras 2009-06-05 15:57:41 +00:00
parent e8e6f1a77f
commit 483359b39a
8 changed files with 73 additions and 64 deletions
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35
pcbnew/block.cpp
View File

@ -302,7 +302,7 @@ int WinEDA_PcbFrame::HandleBlockEnd( wxDC* DC )
/* Routine de gestion de la commande BLOCK END
* returne :
* 0 si aucun compos ant selectionne
* 0 si aucun composant selectionne
* 1 sinon
* -1 si commande terminée et composants trouvés (block delete, block save)
*/
@ -573,14 +573,7 @@ void WinEDA_BasePcbFrame::Block_Delete( wxDC* DC )
}
DrawPanel->Refresh( TRUE );
if( g_Show_Ratsnest )
Compile_Ratsnest( DC, TRUE );
else
{
m_Pcb->m_Status_Pcb = 0; /* we need (later) a full ratnest computation */
m_Pcb->Build_Pads_Full_List();
}
Compile_Ratsnest( DC, TRUE );
}
@ -740,8 +733,7 @@ void WinEDA_BasePcbFrame::Block_Rotate( wxDC* DC )
}
DrawPanel->Refresh( TRUE );
if( g_Show_Ratsnest )
Compile_Ratsnest( DC, TRUE );
Compile_Ratsnest( DC, TRUE );
}
@ -928,8 +920,7 @@ void WinEDA_BasePcbFrame::Block_Invert( wxDC* DC )
}
DrawPanel->Refresh( TRUE );
if( g_Show_Ratsnest )
Compile_Ratsnest( DC, TRUE );
Compile_Ratsnest( DC, TRUE );
}
@ -1074,8 +1065,7 @@ void WinEDA_BasePcbFrame::Block_Move( wxDC* DC )
}
DrawPanel->Refresh( TRUE );
if( g_Show_Ratsnest )
Compile_Ratsnest( DC, TRUE );
Compile_Ratsnest( DC, TRUE );
}
@ -1125,7 +1115,7 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
m_Pcb->m_Modules.PushFront( new_module );
GetScreen()->m_Curseur = module->m_Pos + MoveVector;
Place_Module( new_module, DC );
Place_Module( new_module, NULL );
}
GetScreen()->m_Curseur = oldpos;
@ -1150,8 +1140,6 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
new_track->m_Start += MoveVector;
new_track->m_End += MoveVector;
new_track->Draw( DrawPanel, DC, GR_OR ); // reaffichage
}
track = next_track;
}
@ -1170,8 +1158,6 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
new_segzone->m_Start += MoveVector;
new_segzone->m_End += MoveVector;
new_segzone->Draw( DrawPanel, DC, GR_OR );
}
}
@ -1185,7 +1171,6 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
new_zone->m_TimeStamp = GetTimeStamp();
new_zone->Move( MoveVector );
m_Pcb->Add(new_zone);
new_zone->Draw( DrawPanel, DC, GR_OR );
}
}
}
@ -1217,7 +1202,6 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
new_drawsegment->m_Start += MoveVector;
new_drawsegment->m_End += MoveVector;
new_drawsegment->Draw( DrawPanel, DC, GR_OR );
}
break;
@ -1237,7 +1221,6 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
/* Redessin du Texte */
new_pcbtext->m_Pos += MoveVector;
new_pcbtext->Draw( DrawPanel, DC, GR_OR );
}
break;
@ -1256,7 +1239,6 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
m_Pcb->Add( new_mire );
new_mire->m_Pos += MoveVector;
new_mire->Draw( DrawPanel, DC, GR_OR );
}
break;
@ -1275,7 +1257,6 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
m_Pcb->Add( new_cotation );
new_cotation->Move( MoveVector );
new_cotation->Draw( DrawPanel, DC, GR_OR );
}
break;
@ -1283,4 +1264,8 @@ void WinEDA_BasePcbFrame::Block_Duplicate( wxDC* DC )
break;
}
}
DrawPanel->Refresh( TRUE );
Compile_Ratsnest( DC, TRUE );
}

3
pcbnew/class_board.cpp
View File

@ -229,6 +229,9 @@ void BOARD::Add( BOARD_ITEM* aBoardItem, int aControl )
else
m_Modules.PushFront( (MODULE*) aBoardItem );
aBoardItem->SetParent( this );
// Because the list of pads has changed, reset the status
// This indicate the list of pad and nets must be recalculated before use
m_Status_Pcb = 0;
break;
case TYPE_COTATION:

25
pcbnew/class_netinfo.h
View File

@ -14,6 +14,15 @@ class NETINFO_ITEM;
/* Class RATSNEST_ITEM: describes a ratsnest line: a straight line connecting 2 pads */
/*****************************/
/* flags for a RATSNEST_ITEM */
/*****************************/
#define CH_VISIBLE 1 /* affichage permanent demande */
#define CH_UNROUTABLE 2 /* non route par l'autorouteur */
#define CH_ROUTE_REQ 4 /* doit etre route par l'autorouteur */
#define CH_ACTIF 8 /* chevelu non encore routé */
#define LOCAL_RATSNEST_ITEM 0x8000 /* indique un chevelu reliant 2 pins d'un meme
* module pour le calcul des chevelus relatifs a 1 seul module */
class RATSNEST_ITEM
{
@ -21,10 +30,13 @@ private:
int m_NetCode; // netcode ( = 1.. n , 0 is the value used for not connected items)
public:
int m_Status; // etat: voir defines précédents (CH_ ...)
int m_Status; // State: see previous defines (CH_ ...)
D_PAD* m_PadStart; // pointer to the starting pad
D_PAD* m_PadEnd; // pointer to ending pad
int m_Lenght; // lenght of the line
int m_Lenght; // lenght of the line (temporary used in some calculations)
/* constructor */
RATSNEST_ITEM();
/**
* Function GetNet
@ -176,15 +188,6 @@ public:
};
/*****************************/
/* flags for a RATSNEST_ITEM */
/*****************************/
#define CH_VISIBLE 1 /* affichage permanent demande */
#define CH_UNROUTABLE 2 /* non route par l'autorouteur */
#define CH_ROUTE_REQ 4 /* doit etre route par l'autorouteur */
#define CH_ACTIF 8 /* chevelu non encore routé */
#define LOCAL_RATSNEST_ITEM 0x8000 /* indique un chevelu reliant 2 pins d'un meme
* module pour le calcul des chevelus relatifs a 1 seul module */
/****************************************************************/

37
pcbnew/class_netinfo_item.cpp
View File

@ -17,10 +17,10 @@
NETINFO_ITEM::NETINFO_ITEM( BOARD_ITEM* aParent )
{
SetNet( 0 );
m_NbNodes = m_NbLink = m_NbNoconn = 0;
m_NbNodes = m_NbLink = m_NbNoconn = 0;
m_ForceWidth = 0;
m_RatsnestStart = 0; // debut de liste ratsnests du net
m_RatsnestEnd = 0; // fin de liste ratsnests du net
m_RatsnestStart = 0; // debut de liste ratsnests du net
m_RatsnestEnd = 0; // fin de liste ratsnests du net
}
@ -31,10 +31,10 @@ NETINFO_ITEM::~NETINFO_ITEM()
}
/*********************************************************/
int NETINFO_ITEM:: ReadDescr( FILE* File, int* LineNum )
/*********************************************************/
/* Routine de lecture de 1 descr Equipotentielle.
* retourne 0 si OK
* 1 si lecture incomplete
@ -73,6 +73,7 @@ int NETINFO_ITEM:: ReadDescr( FILE* File, int* LineNum )
/**************************************/
bool NETINFO_ITEM::Save( FILE* aFile ) const
/**************************************/
/** Note: the old name of class NETINFO_ITEM was EQUIPOT
* so in Save (and read) functions, for compatibility, we use EQUIPOT as keyword
*/
@ -95,11 +96,12 @@ out:
return success;
}
/**
* Function SetNetname
* @param const wxString : the new netname
*/
void NETINFO_ITEM::SetNetname( const wxString & aNetname )
void NETINFO_ITEM::SetNetname( const wxString& aNetname )
{
m_Netname = aNetname;
m_ShortNetname = m_Netname.AfterLast( '/' );
@ -120,14 +122,14 @@ void NETINFO_ITEM::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int aDrawMode, const
* Is virtual from EDA_BaseStruct.
* @param frame A WinEDA_DrawFrame in which to print status information.
*/
void NETINFO_ITEM::DisplayInfo( WinEDA_DrawFrame* frame )
void NETINFO_ITEM::DisplayInfo( WinEDA_DrawFrame* frame )
{
int count;
EDA_BaseStruct* Struct;
wxString txt;
MODULE* module;
D_PAD* pad;
double lengthnet = 0;
double lengthnet = 0;
frame->MsgPanel->EraseMsgBox();
@ -136,8 +138,8 @@ void NETINFO_ITEM::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int aDrawMode, const
txt.Printf( wxT( "%d" ), GetNet() );
Affiche_1_Parametre( frame, 30, _( "Net Code" ), txt, RED );
count = 0;
module = ((WinEDA_BasePcbFrame*)frame)->GetBoard()->m_Modules;
count = 0;
module = ( (WinEDA_BasePcbFrame*) frame )->GetBoard()->m_Modules;
for( ; module != 0; module = module->Next() )
{
for( pad = module->m_Pads; pad != 0; pad = pad->Next() )
@ -150,8 +152,8 @@ void NETINFO_ITEM::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int aDrawMode, const
txt.Printf( wxT( "%d" ), count );
Affiche_1_Parametre( frame, 40, _( "Pads" ), txt, DARKGREEN );
count = 0;
Struct = ((WinEDA_BasePcbFrame*)frame)->GetBoard()->m_Track;
count = 0;
Struct = ( (WinEDA_BasePcbFrame*) frame )->GetBoard()->m_Track;
for( ; Struct != NULL; Struct = Struct->Next() )
{
if( Struct->Type() == TYPE_VIA )
@ -159,7 +161,7 @@ void NETINFO_ITEM::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int aDrawMode, const
count++;
if( Struct->Type() == TYPE_TRACK )
if( ( (TRACK*) Struct )->GetNet() == GetNet() )
lengthnet += ( (TRACK*) Struct )->GetLength();
lengthnet += ( (TRACK*) Struct )->GetLength();
}
txt.Printf( wxT( "%d" ), count );
@ -174,6 +176,16 @@ void NETINFO_ITEM::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int aDrawMode, const
/* class RATSNEST_ITEM */
/***********************/
RATSNEST_ITEM::RATSNEST_ITEM()
{
m_NetCode = 0; // netcode ( = 1.. n , 0 is the value used for not connected items)
m_Status = 0; // state
m_PadStart = NULL; // pointer to the starting pad
m_PadEnd = NULL; // pointer to ending pad
m_Lenght = 0; // lenght of the line (temporary used in some calculations)
}
/** function Draw
* Draws a line (a ratsnest) from the starting pad to the ending pad
*/
@ -182,4 +194,3 @@ void RATSNEST_ITEM::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int aDrawMode, cons
GRLine( &panel->m_ClipBox, DC, m_PadStart->m_Pos - aOffset,
m_PadEnd->m_Pos - aOffset, 0, g_DesignSettings.m_RatsnestColor );
}

2
pcbnew/class_netinfolist.cpp
View File

@ -92,9 +92,9 @@ void NETINFO_LIST::BuildListOfNets()
/* Build the PAD list, sorted by net */
m_Parent->Build_Pads_Full_List();
int netcode = 0;
/* Build netnames list, and create a netcode for each netname */
D_PAD* last_pad = NULL;
int netcode = 0;
for( unsigned ii = 0; ii < m_Parent->m_Pads.size(); ii++ )
{
pad = m_Parent->m_Pads[ii];

9
pcbnew/loadcmp.cpp
View File

@ -162,7 +162,14 @@ MODULE* WinEDA_BasePcbFrame::Load_Module_From_Library( const wxString& library,
module->m_TimeStamp = GetTimeStamp();
GetBoard()->m_Status_Pcb = 0;
module->SetPosition( curspos );
GetBoard()->Build_Pads_Full_List();
/* TODO: call RecalculateAllTracksNetcode() only if some pads pads have
* a netname.
* If all pads are "not connected (usually the caes in module libraries,
* rebuild only the pad and list of nets ( faster)
*/
// GetBoard()->m_Pcb->m_NetInfo->BuildListOfNets();
RecalculateAllTracksNetcode( );
if ( DC )
module->Draw( DrawPanel, DC, GR_OR );
}

11
pcbnew/ratsnest.cpp
View File

@ -107,8 +107,11 @@ void WinEDA_BasePcbFrame::Compile_Ratsnest( wxDC* DC, bool display_status_pcb )
GetBoard()->m_Status_Pcb = 0; /* we want a full ratnest computation, from the scratch */
GetBoard()->Build_Pads_Full_List(); /* Create the sorted pad list */
MsgPanel->EraseMsgBox();
MsgPanel->EraseMsgBox();
// Rebuild the full pads and net info list
RecalculateAllTracksNetcode();
if( display_status_pcb )
{
@ -116,9 +119,6 @@ void WinEDA_BasePcbFrame::Compile_Ratsnest( wxDC* DC, bool display_status_pcb )
Affiche_1_Parametre( this, 1, wxT( "pads" ), msg, RED );
}
//Rebuild the net info list
RecalculateAllTracksNetcode();
if( display_status_pcb )
{
msg.Printf( wxT( " %d" ), m_Pcb->m_NetInfo->GetCount() );
@ -775,6 +775,7 @@ void WinEDA_BasePcbFrame::build_ratsnest_module( wxDC* DC, MODULE* Module )
if( (GetBoard()->m_Status_Pcb & LISTE_PAD_OK) == 0 )
{
GetBoard()->m_Status_Pcb = 0;
GetBoard()->Build_Pads_Full_List();
}

15
pcbnew/xchgmod.cpp
View File

@ -309,8 +309,7 @@ void WinEDA_ExchangeModuleFrame::Change_Module( wxCommandEvent& event )
if( Change_1_Module( m_CurrentModule, newmodulename, TRUE ) )
{
m_Parent->GetBoard()->m_Status_Pcb = 0;
m_Parent->GetBoard()->Build_Pads_Full_List();
m_Parent->Compile_Ratsnest( m_DC, true );
}
}
@ -394,8 +393,7 @@ void WinEDA_ExchangeModuleFrame::Change_ModuleId( wxCommandEvent& event )
if( change )
{
m_Parent->GetBoard()->m_Status_Pcb = 0;
m_Parent->GetBoard()->Build_Pads_Full_List();
m_Parent->Compile_Ratsnest( m_DC, true );
}
}
@ -445,8 +443,7 @@ void WinEDA_ExchangeModuleFrame::Change_ModuleAll( wxCommandEvent& event )
if( change )
{
m_Parent->GetBoard()->m_Status_Pcb = 0;
m_Parent->GetBoard()->Build_Pads_Full_List();
m_Parent->Compile_Ratsnest( m_DC, true );
}
}
@ -500,12 +497,14 @@ MODULE* WinEDA_ExchangeModuleFrame::Change_1_Module( MODULE* Module,
m_WinMsg->WriteText( wxT( "Ok\n" ) );
/* Effacement a l'ecran de l'ancien module */
Module->Draw( m_Parent->DrawPanel, m_DC, GR_XOR );
if ( m_DC )
Module->Draw( m_Parent->DrawPanel, m_DC, GR_XOR );
m_Parent->Exchange_Module( this, Module, NewModule );
/* Affichage du nouveau module */
NewModule->Draw( m_Parent->DrawPanel, m_DC, GR_OR );
if ( m_DC )
NewModule->Draw( m_Parent->DrawPanel, m_DC, GR_OR );
Maj_ListeCmp( NewModule->m_Reference->m_Text,
oldnamecmp,