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Minor BOARD_DESIGN_SETTINGS refactoring. 

Removed SetCurrentClassName() (it was not used anywhere and less safe than SetCurrentClass()).
Added BOARD_DESIGN_SETTIGNS::GetDefault() to make some pieces of shorter and clearer.
This commit is contained in:
Maciej Suminski 2014-05-15 10:51:08 +02:00
parent b2a5b2f329
commit 4fcaf4c586
11 changed files with 28 additions and 26 deletions
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18
include/class_board_design_settings.h
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@ -102,18 +102,22 @@ public:
BOARD_DESIGN_SETTINGS();
/**
* Function SetCurrentNetClassName
* sets the current net class name to \a aName.
*
* @param aName is a reference to a wxString object containing the current net class name.
* Function GetDefault
* @return the default netclass.
*/
void SetCurrentNetClassName( const wxString& aName ) { m_currentNetClassName = aName; }
inline NETCLASS* GetDefault() const
{
return m_NetClasses.GetDefault();
}
/**
* Function GetCurrentNetClassName
* @return the current net class name.
*/
const wxString& GetCurrentNetClassName() const { return m_currentNetClassName; }
const wxString& GetCurrentNetClassName() const
{
return m_currentNetClassName;
}
/**
* Function SetCurrentNetClass
@ -275,8 +279,6 @@ public:
return m_customViaSize.m_Drill;
}
// TODO microvia methods should go here
/**
* Function UseCustomTrackViaSize
* Enables/disables custom track/via size settings. If enabled, values set with

2
pcbnew/autorouter/routing_matrix.cpp
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@ -201,7 +201,7 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag )
LAYER_MSK layerMask;
// use the default NETCLASS?
NETCLASS* nc = aPcb->GetDesignSettings().m_NetClasses.GetDefault();
NETCLASS* nc = aPcb->GetDesignSettings().GetDefault();
int trackWidth = nc->GetTrackWidth();
int clearance = nc->GetClearance();

2
pcbnew/autorouter/solve.cpp
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@ -280,7 +280,7 @@ int PCB_EDIT_FRAME::Solve( wxDC* DC, int aLayersCount )
m_canvas->SetAbortRequest( false );
s_Clearance = GetBoard()->GetDesignSettings().m_NetClasses.GetDefault()->GetClearance();
s_Clearance = GetBoard()->GetDesignSettings().GetDefault()->GetClearance();
// Prepare the undo command info
s_ItemsListPicker.ClearListAndDeleteItems(); // Should not be necessary, but...

2
pcbnew/class_board.cpp
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@ -91,7 +91,7 @@ BOARD::BOARD() :
m_Layer[layer].m_Type = LT_UNDEFINED;
}
NETCLASS* defaultClass = m_designSettings.m_NetClasses.GetDefault();
NETCLASS* defaultClass = m_designSettings.GetDefault();
defaultClass->SetDescription( _( "This is the default net class." ) );
// Initialize default values in default netclass.

4
pcbnew/class_board_connected_item.cpp
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@ -144,7 +144,7 @@ NETCLASS* BOARD_CONNECTED_ITEM::GetNetClass() const
if( netclass )
return netclass;
else
return board->GetDesignSettings().m_NetClasses.GetDefault();
return board->GetDesignSettings().GetDefault();
}
@ -158,7 +158,7 @@ wxString BOARD_CONNECTED_ITEM::GetNetClassName() const
else
{
BOARD* board = GetBoard();
name = board->GetDesignSettings().m_NetClasses.GetDefault()->GetName();
name = NETCLASS::Default;
}
return name;

2
pcbnew/eagle_plugin.cpp
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@ -1146,7 +1146,7 @@ BOARD* EAGLE_PLUGIN::Load( const wxString& aFileName, BOARD* aAppendToMe, const
if( m_rules->mdWireWire )
{
NETCLASS* defaultNetclass = designSettings.m_NetClasses.GetDefault();
NETCLASS* defaultNetclass = designSettings.GetDefault();
int clearance = KiROUND( m_rules->mdWireWire );
if( clearance < defaultNetclass->GetClearance() )

2
pcbnew/files.cpp
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@ -678,7 +678,7 @@ bool PCB_EDIT_FRAME::SavePcbFile( const wxString& aFileName, bool aCreateBackupF
// Select default Netclass before writing file.
// Useful to save default values in headers
GetDesignSettings().SetCurrentNetClass( GetDesignSettings().m_NetClasses.GetDefault()->GetName() );
GetDesignSettings().SetCurrentNetClass( NETCLASS::Default );
try
{

12
pcbnew/kicad_plugin.cpp
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@ -572,7 +572,7 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const
FMTIU( dsnSettings.m_TrackWidthList[ii] ).c_str() );
m_out->Print( aNestLevel+1, "(trace_clearance %s)\n",
FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetClearance() ).c_str() );
FMTIU( dsnSettings.GetDefault()->GetClearance() ).c_str() );
// ZONE_SETTINGS
m_out->Print( aNestLevel+1, "(zone_clearance %s)\n",
@ -590,9 +590,9 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const
// Save current default via size, for compatibility with older Pcbnew version;
m_out->Print( aNestLevel+1, "(via_size %s)\n",
FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetViaDiameter() ).c_str() );
FMTIU( dsnSettings.GetDefault()->GetViaDiameter() ).c_str() );
m_out->Print( aNestLevel+1, "(via_drill %s)\n",
FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetViaDrill() ).c_str() );
FMTIU( dsnSettings.GetDefault()->GetViaDrill() ).c_str() );
m_out->Print( aNestLevel+1, "(via_min_size %s)\n",
FMTIU( dsnSettings.m_ViasMinSize ).c_str() );
m_out->Print( aNestLevel+1, "(via_min_drill %s)\n",
@ -610,9 +610,9 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const
m_out->Print( aNestLevel+1, "(blind_buried_vias_allowed yes)\n" );
m_out->Print( aNestLevel+1, "(uvia_size %s)\n",
FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetuViaDiameter() ).c_str() );
FMTIU( dsnSettings.GetDefault()->GetuViaDiameter() ).c_str() );
m_out->Print( aNestLevel+1, "(uvia_drill %s)\n",
FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetuViaDrill() ).c_str() );
FMTIU( dsnSettings.GetDefault()->GetuViaDrill() ).c_str() );
m_out->Print( aNestLevel+1, "(uvias_allowed %s)\n",
( dsnSettings.m_MicroViasAllowed ) ? "yes" : "no" );
m_out->Print( aNestLevel+1, "(uvia_min_size %s)\n",
@ -683,7 +683,7 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const
m_out->Print( 0, "\n" );
// Save the default net class first.
NETCLASS defaultNC = *dsnSettings.m_NetClasses.GetDefault();
NETCLASS defaultNC = *dsnSettings.GetDefault();
filterNetClass( *aBoard, defaultNC ); // Remove empty nets (from a copy of a netclass)
defaultNC.Format( m_out, aNestLevel, m_ctl );

6
pcbnew/legacy_plugin.cpp
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@ -632,7 +632,7 @@ void LEGACY_PLUGIN::loadSHEET()
void LEGACY_PLUGIN::loadSETUP()
{
NETCLASS* netclass_default = m_board->GetDesignSettings().m_NetClasses.GetDefault();
NETCLASS* netclass_default = m_board->GetDesignSettings().GetDefault();
// TODO Orson: is it really necessary to first operate on a copy and then apply it?
// would not it be better to use reference here and apply all the changes instantly?
BOARD_DESIGN_SETTINGS bds = m_board->GetDesignSettings();
@ -897,7 +897,7 @@ void LEGACY_PLUGIN::loadSETUP()
// at all, the global defaults should go into a preferences
// file instead so they are there to start new board
// projects.
m_board->GetDesignSettings().m_NetClasses.GetDefault()->SetParams( m_board->GetDesignSettings() );
m_board->GetDesignSettings().GetDefault()->SetParams( m_board->GetDesignSettings() );
return; // preferred exit
}
@ -2985,7 +2985,7 @@ void LEGACY_PLUGIN::saveSHEET( const BOARD* aBoard ) const
void LEGACY_PLUGIN::saveSETUP( const BOARD* aBoard ) const
{
const BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings();
NETCLASS* netclass_default = bds.m_NetClasses.GetDefault();
NETCLASS* netclass_default = bds.GetDefault();
fprintf( m_fp, "$SETUP\n" );

2
pcbnew/pcb_parser.cpp
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@ -808,7 +808,7 @@ void PCB_PARSER::parseSetup() throw( IO_ERROR, PARSE_ERROR )
wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as setup." ) );
T token;
NETCLASS* defaultNetClass = m_board->GetDesignSettings().m_NetClasses.GetDefault();
NETCLASS* defaultNetClass = m_board->GetDesignSettings().GetDefault();
// TODO Orson: is it really necessary to first operate on a copy and then apply it?
// would not it be better to use reference here and apply all the changes instantly?
BOARD_DESIGN_SETTINGS designSettings = m_board->GetDesignSettings();

2
pcbnew/router/router_tool.cpp
View File

@ -279,7 +279,7 @@ void ROUTER_TOOL::getNetclassDimensions( int aNetCode, int& aWidth,
}
if( !netClass )
netClass = bds.m_NetClasses.GetDefault();
netClass = bds.GetDefault();
aWidth = netClass->GetTrackWidth();
aViaDiameter = netClass->GetViaDiameter();