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Currently translated at 100.0% (9170 of 9170 strings)

Translation: KiCad EDA/v8
Translate-URL: https://hosted.weblate.org/projects/kicad/v8/zh_Hans/
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@ -36,8 +36,8 @@ msgstr ""
"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n" "Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
"Report-Msgid-Bugs-To: \n" "Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-04-14 14:22-0700\n" "POT-Creation-Date: 2024-04-14 14:22-0700\n"
"PO-Revision-Date: 2024-04-16 08:02+0000\n" "PO-Revision-Date: 2024-04-17 14:21+0000\n"
"Last-Translator: Hubert Hu <qinghan.hu@gmail.com>\n" "Last-Translator: taotieren <admin@taotieren.com>\n"
"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/" "Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
"kicad/v8/zh_Hans/>\n" "kicad/v8/zh_Hans/>\n"
"Language: zh_CN\n" "Language: zh_CN\n"
@ -21572,11 +21572,11 @@ msgstr "%s 具有类型为 '%s %s' 的仿真模型, 只能调整RLC无源元件"
#: eeschema/widgets/tuner_slider_base.cpp:43 #: eeschema/widgets/tuner_slider_base.cpp:43
msgid "Limit to E24 series values." msgid "Limit to E24 series values."
msgstr "限制为 E24 系列值" msgstr "限制为 E24 系列值。"
#: eeschema/widgets/tuner_slider_base.cpp:53 #: eeschema/widgets/tuner_slider_base.cpp:53
msgid "Limit to E48 series values." msgid "Limit to E48 series values."
msgstr "限制为 E48 系列值" msgstr "限制为 E48 系列值。"
#: eeschema/widgets/tuner_slider_base.cpp:61 #: eeschema/widgets/tuner_slider_base.cpp:61
msgid "Limit to E96 series values" msgid "Limit to E96 series values"
@ -35718,7 +35718,6 @@ msgid "Check rule syntax"
msgstr "检查规则语法" msgstr "检查规则语法"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 #: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid "" msgid ""
"### Top-level Clauses\n" "### Top-level Clauses\n"
"\n" "\n"
@ -36194,132 +36193,175 @@ msgstr ""
"\n" "\n"
"### Constraints (约束) \n" "### Constraints (约束) \n"
"\n" "\n"
"| 约束类型 | 变量类" "| 约束类型 | 变量类型 "
"型 " " | 描述 "
"| 描" " "
"述 " " "
"|\n" " "
"|---------------------------|------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n" " "
"| `annular_width` | min/opt/" " "
"max " " |\n"
"| 检查过孔的孔环宽度" "|---------------------------|------------------------------------------------"
"<br> " "------------------------------------------------------------------------|----"
"|\n" "-----------------------------------------------------------------------------"
"| `clearance` | " "-----------------------------------------------------------------------------"
"min " "-----------------------------------------------------------------------------"
"| 定义不同网络铜箔对象的 **电气** 间隙。 (如果您想定义不考虑网络的对象的间" "-----------------------------------------------------------------------------"
"隙，请查看 `physical_clearance` 约束类型。<br><br>如果允许铜箔对象重叠(碰" "-----------------------------------------------------------------------------"
"撞)，可以创建一个 `clearance` 约束，并将 `min` 值设为小于零 (例如, `-1`)。" "----------------------------------------------------|\n"
"<br> " "| `annular_width` | min/opt/max "
"|\n" " | 检"
"| `courtyard_clearance` | " "查过孔的孔环宽度<br> "
"min " " "
"| 检查封装 Courtyard 之间的间隙，如果任何两个封装之间的距离小于 min 的值，则" " "
"会产生错误。如果封装没有 Courtyard，则该约束不会产生错误。" " "
"<br> " " "
"|\n" " |\n"
"| `diff_pair_gap` | min/opt/" "| `assertion` | \"&lt;expression>\" "
"max " " | "
"| 检查差分对中耦合走线之间的间隙。 耦合走线是相互平行的线段。 差分对间隙约束" "检查给定的表达式。<br> "
"不对差分对的非耦合部分 (例如，元件的扇出部分) 进行测试。" " "
"<br> " " "
"|\n" " "
"| `diff_pair_uncoupled` | " " "
"max " " |\n"
"| 检查差分对正负走线非耦合部分的间距 (例如，差分对从元件扇出，或绕过某一物体 " "| `clearance` | min "
"(如通孔) 的非耦合部分) 。" " | "
"<br> " "定义不同网络铜箔对象的 **电气** 间隙。 (如果您想定义不考虑网络的对象的间隙，"
"|\n" "请查看 `physical_clearance` 约束类型。<br><br>如果允许铜箔对象重叠(碰撞)，"
"| `disallow` | " "可以创建一个 `clearance` 约束，并将 `min` 值设为小于零 (例如, `-1`)。<br> "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> " " "
"| 指定一个或多个对象类型不被允许, 使用空格分割。 例如, `(constraint " " |\n"
"disallow track)` 或 `(constraint disallow track via pad)`。 如果这个类型的对" "| `courtyard_clearance` | min "
"象满足规则条件，就会产生一个 DRC 错误。<br><br>该约束类型与 keepout 规则区域" " | "
"基本相同，但可以创建更具体的 keepout 约束。" "检查封装 Courtyard 之间的间隙，如果任何两个封装之间的距离小于 `min` "
"的值，则会产生错误。如果封装没有 Courtyard，则该约束不会产生错误。<br> "
" "
" "
" |\n"
"| `diff_pair_gap` | min/opt/max "
" | "
"检查差分对中耦合走线之间的间隙。 耦合走线是相互平行的线段。 "
"差分对间隙约束不对差分对的非耦合部分 (例如，元件的扇出部分) 进行测试。<br> "
" "
" "
" |\n"
"| `diff_pair_uncoupled` | max "
" | "
"检查差分对正负走线非耦合部分的间距 (例如，差分对从元件扇出，或绕过某一物体 "
"(如通孔) 的非耦合部分) 。<br> "
" "
" |"
"\n"
"| `disallow` | `track`<br>`via`<br>`micro_via`<br>`buried_via`"
"<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> | "
"指定一个或多个对象类型不被允许, 使用空格分割。 例如, `(constraint disallow "
"track)` 或 `(constraint disallow track via pad)`。 "
"如果这个类型的对象满足规则条件，就会产生一个 DRC 错误。<br><br>该约束类型与 "
"keepout 规则区域基本相同，但可以创建更具体的 keepout 约束。"
"<br> |\n" "<br> |\n"
"| `edge_clearance` | min/opt/" "| `edge_clearance` | min/opt/max "
"max " " | "
"| 检查对象与板边的间隙。<br><br>这也可以看作是 \"铣削公差\"，因为电路板边缘将" "检查对象与板边的间隙。<br><br>这也可以看作是 \"铣削公差\"，"
"包括 `Edge.Cuts` 层上的所有图形对象以及任何 *椭圆* 焊盘孔。 (钻孔公差请查看 " "因为电路板边缘将包括 `Edge.Cuts` 层上的所有图形对象以及任何 *椭圆* 焊盘孔。 "
"`physical_hole_clearance` 约束类" "(钻孔公差请查看 `physical_hole_clearance` 约束类型)<br> "
"型)<br> " " "
"|\n" " |\n"
"| `length` | min/" "| `length` | min/max "
"max " " | "
"| 检查符合规则条件的网络的总走线长度，如果网络的长度低于限制条件的 `min` 最小" "检查符合规则条件的网络的总走线长度，如果网络的长度低于限制条件的 `min` "
"值 (如果指定) 或高于 `max` 最大值 (如果指定) ，则生成错误。" "最小值 (如果指定) 或高于 `max` 最大值 (如果指定) ，则生成错误。<br> "
"<br> " " "
"|\n" " "
"| `hole` | min/" " |\n"
"max " "| `hole` | min/max "
"| 检查焊盘或过孔中钻孔的大小 (直径) 。 对于椭圆形孔，较小的直径将与 `min` 最" " | "
"小值 (如果指定) 对比，较大的直径将与 `max` 最大值 (如果指定) 对比。" "检查焊盘或过孔中钻孔的大小 (直径) 。 对于椭圆形孔，较小的直径将与 `min` "
"<br> " "最小值 (如果指定) 对比，较大的直径将与 `max` 最大值 (如果指定) 对比。<br> "
"|\n" " "
"| `hole_clearance` | " " "
"min " " |\n"
"| 检查焊盘或过孔中的钻孔与不同网络的铜箔对象之间的间隙。 间隙是从孔的直径而不" "| `hole_clearance` | min "
"是孔的中心测量的。" " | "
"<br> " "检查焊盘或过孔中的钻孔与不同网络的铜箔对象之间的间隙。 "
"|\n" "间隙是从孔的直径而不是孔的中心测量的。<br> "
"| `hole_to_hole` | " " "
"min " " "
"| 检查焊盘和过孔中机械钻孔之间的间隙。 间隙在孔边缘之间测量，而不是从孔的中心" " |"
"测量。<br><br>该约束类型完全是为了保护钻头。 不检查 **激光钻孔** (微孔) 与其" "\n"
"他非机械钻孔之间的间隙，也不检查 **铣削孔** (椭圆形) 与其他非机械钻孔之间的间" "| `hole_to_hole` | min "
"隙。<br> |\n" " | "
"| `physical_clearance` | " "检查焊盘和过孔中机械钻孔之间的间隙。 间隙在孔边缘之间测量，而不是从孔的中心测"
"min " "量。<br><br>该约束类型完全是为了保护钻头。 不检查 **激光钻孔** (微孔) "
"| 检查给定层 (包括非铜层) 上两个对象之间的间隙。<br><br>虽然这可以执行比 " "与其他非机械钻孔之间的间隙，也不检查 **铣削孔** (椭圆形) "
"`clearance` 更通用的检查，但速度要慢得多。 尽可能使用 `clearance` 约束。" "与其他非机械钻孔之间的间隙。<br> |\n"
"<br> " "| `physical_clearance` | min "
"|\n" " | "
"| `physical_hole_clearance` | " "检查给定层 (包括非铜层) 上两个对象之间的间隙。<br><br>虽然这可以执行比 "
"min " "`clearance` 更通用的检查，但速度要慢得多。 尽可能使用 `clearance` 约束。<br> "
"| 检查焊盘或过孔中的钻孔与另一个对象之间的间隙，无论它们是否属于同一网络。 间" " "
"隙是从孔的边缘而不是中心测量的。<br><br>这也可以被认为是“钻孔公差”，因为它只" " "
"包括 **圆** 孔 (有关铣削公差，请参阅 `edge_clearance`) 。" " |\n"
"<br> " "| `physical_hole_clearance` | min "
"|\n" " | "
"| `silk_clearance` | min/opt/" "检查焊盘或过孔中的钻孔与另一个对象之间的间隙，无论它们是否属于同一网络。 "
"max " "间隙是从孔的边缘而不是中心测量的。<br><br>这也可以被认为是“钻孔公差”，"
"| 检查丝印层上的对象与其他对象之间的间隙。" "因为它只包括 **圆** 孔 (有关铣削公差，请参阅 `edge_clearance`) 。<br> "
"<br> " " "
"|\n" " |\n"
"| `skew` | " "| `silk_clearance` | min/opt/max "
"max " " | "
"| 检查所有符合规则条件的网络的 skew，即符合规则的每个网络的长度与网络总长的平" "检查丝印层上的对象与其他对象之间的间隙。<br> "
"均值之间的差值。 如果该平均值与任何一个网络的长度之间的差的绝对值高于约束 " " "
"`max` 最大值，则会产生错误。" " "
"<br> " " "
"|\n" " "
"| `thermal_relief_gap` | " " |\n"
"min " "| `skew` | max "
"| 指定在热焊盘连接方式下，焊盘与敷铜区域之间的最小间隙。" " | "
"<br> " "检查所有符合规则条件的网络的 "
"|\n" "skew，即符合规则的每个网络的长度与网络总长的平均值之间的差值。 "
"| `thermal_spoke_width` | " "如果该平均值与任何一个网络的长度之间的差的绝对值高于约束 `max` "
"opt " "最大值，则会产生错误。<br> "
"| 指定在热焊盘连接方式下，连接焊盘与敷铜的辐条的宽度。" " |\n"
"<br> " "| `thermal_relief_gap` | min "
"|\n" " | "
"| `track_width` | min/opt/" "指定在热焊盘连接方式下，焊盘与敷铜区域之间的最小间隙。<br> "
"max " " "
"| 检查走线和圆弧走线的宽度。 对于宽度低于 `min` 最小值 (如果指定) 或高于 " " "
"`max` 最大值 (如果指定) 的走线线段，都会生成错误。" " "
"<br> " " "
"|\n" " |\n"
"| `via_count` | " "| `thermal_spoke_width` | opt "
"max " " | "
"| 计算每个与规则条件匹配的网络的过孔数量。 如果该数字超过匹配网络上的约束 " "指定在热焊盘连接方式下，连接焊盘与敷铜的辐条的宽度。<br> "
"`max` 最大值，则将为该网络生成错误。" " "
"<br> " " "
"|\n" " "
"| `zone_connection` | " " "
"`solid`<br>`thermal_reliefs`<br>`none` " " |\n"
"| 指定焊盘与敷铜区域之间的连接方式。" "| `track_width` | min/opt/max "
"<br> " " | "
"|\n" "检查走线和圆弧走线的宽度。 对于宽度低于 `min` 最小值 (如果指定) 或高于 `max` "
"最大值 (如果指定) 的走线线段，都会生成错误。<br> "
" "
" "
" |\n"
"| `via_count` | max "
" | "
"计算每个与规则条件匹配的网络的过孔数量。 如果该数字超过匹配网络上的约束 `max`"
" 最大值，则将为该网络生成错误。<br> "
" "
" "
" |\n"
"| `zone_connection` | `solid`<br>`thermal_reliefs`<br>`none` "
" | "
"指定焊盘与敷铜区域之间的连接方式。<br> "
" "
" "
" "
" "
" |\n"
"\n" "\n"
"\n" "\n"
"### Items (对象) \n" "### Items (对象) \n"
@ -36373,8 +36415,8 @@ msgstr ""
"### Notes (注意事项) \n" "### Notes (注意事项) \n"
"\n" "\n"
"版本语句必须是第一个语句。 \n" "版本语句必须是第一个语句。 \n"
"它表示文件的语法版本，以便未来的规则解析器可以执行自动更新。 它应该设置" "它表示文件的语法版本，以便未来的规则解析器可以执行自动更新。 "
"为“1”。\n" "它应该设置为“1”。\n"
"\n" "\n"
"规则应按具体情况排序。 \n" "规则应按具体情况排序。 \n"
"后面的规则优先于前面的规则； 一旦找到后面匹配的规则，就不会检查之前的规则。\n" "后面的规则优先于前面的规则； 一旦找到后面匹配的规则，就不会检查之前的规则。\n"
@ -36406,8 +36448,8 @@ msgstr ""
" A.enclosedByArea('<zone_name>')\n" " A.enclosedByArea('<zone_name>')\n"
"若 `A` 完全落在指定区域的边框内，则为 True。\n" "若 `A` 完全落在指定区域的边框内，则为 True。\n"
"\n" "\n"
"注意: 调用该函数比 `intersectsArea()`更费时。尽可能使用 " "注意: 调用该函数比 `intersectsArea()`更费时。尽可能使用 `intersectsArea()`。"
"`intersectsArea()`。\n" "\n"
"<br><br>\n" "<br><br>\n"
"\n" "\n"
" A.getField('<field_name>')\n" " A.getField('<field_name>')\n"
@ -36419,10 +36461,11 @@ msgstr ""
"<br><br>\n" "<br><br>\n"
"\n" "\n"
" A.inDiffPair('<net_name>')\n" " A.inDiffPair('<net_name>')\n"
"若 `A` 含有指定差分对的网络，则为 True。 <网络名> 是指定差分对的基础名称。例" "若 `A` 含有指定差分对的网络，则为 True。 <网络名> "
"如， inDiffPair('CLK') matches items in the CLK_P and CLK_N nets. True \n" "是指定差分对的基础名称。例如， inDiffPair('CLK') matches items in the CLK_P "
"`<net_name>` 是差分对的基准名称。 例如, `inDiffPair('/CLK')` 可以匹配网络对" "and CLK_N nets. True \n"
"象 `/CLK_P` 及 `/CLK_N`。\n" "`<net_name>` 是差分对的基准名称。 例如, `inDiffPair('/CLK')` "
"可以匹配网络对象 `/CLK_P` 及 `/CLK_N`。\n"
"<br><br>\n" "<br><br>\n"
"\n" "\n"
" AB.isCoupledDiffPair()\n" " AB.isCoupledDiffPair()\n"
@ -36434,8 +36477,12 @@ msgstr ""
"包含嵌套的分组成员。\n" "包含嵌套的分组成员。\n"
"<br><br>\n" "<br><br>\n"
"\n" "\n"
" A.memberOfFootprint('<footprint_reference>')\n" " A.memberOfFootprint('<footprint_reference>|<footprint_id>')\n"
"若 `A` 是给定参考位号匹配的封装的成员，则为 True。位号可以包含通配符。\n" "若 `A` 是给定参考位号或封装 ID 匹配的封装的成员，则为 "
"True。参数可以包含通配符。\n"
"\n"
"注意：如果需要与封装ID 匹配，参数中必须包含 ':'。\n"
"\n"
"<br><br>\n" "<br><br>\n"
"\n" "\n"
" A.memberOfSheet('<sheet_path>')\n" " A.memberOfSheet('<sheet_path>')\n"
@ -36472,13 +36519,13 @@ msgstr ""
"\n" "\n"
" (rule \"Distance between Vias of Different Nets\"\n" " (rule \"Distance between Vias of Different Nets\"\n"
" (constraint hole_to_hole (min 0.254mm))\n" " (constraint hole_to_hole (min 0.254mm))\n"
" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B." " (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net\"))"
"Net\"))\n" "\n"
"\n" "\n"
" (rule \"Clearance between Pads of Different Nets\"\n" " (rule \"Clearance between Pads of Different Nets\"\n"
" (constraint clearance (min 3.0mm))\n" " (constraint clearance (min 3.0mm))\n"
" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B." " (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net\"))"
"Net\"))\n" "\n"
"\n" "\n"
"\n" "\n"
" (rule \"Via Hole to Track Clearance\"\n" " (rule \"Via Hole to Track Clearance\"\n"
@ -38160,7 +38207,7 @@ msgstr "(层 %s; %d 条引线与孤岛相连)"
#: pcbnew/drc/drc_test_provider_zone_connections.cpp:229 #: pcbnew/drc/drc_test_provider_zone_connections.cpp:229
#, c-format #, c-format
msgid "(layer %s; %s min spoke count %d; actual %d)" msgid "(layer %s; %s min spoke count %d; actual %d)"
msgstr "(层 %s 最小引线数量 %d; 实际 %d)" msgstr "(层 %s; %s 最小引线数量 %d; 实际 %d)"
#: pcbnew/drc/drc_test_provider_zone_connections.cpp:254 #: pcbnew/drc/drc_test_provider_zone_connections.cpp:254
msgid "Checking thermal reliefs..." msgid "Checking thermal reliefs..."
@ -38374,17 +38421,16 @@ msgid "Current Board will be closed. Continue?"
msgstr "当前电路板将关闭。是否继续?" msgstr "当前电路板将关闭。是否继续?"
#: pcbnew/files.cpp:479 #: pcbnew/files.cpp:479
#, fuzzy
msgid "" msgid ""
"If the zones on this board are refilled the Copper Edge Clearance setting " "If the zones on this board are refilled the Copper Edge Clearance setting "
"will be used (see Board Setup > Design Rules > Constraints).\n" "will be used (see Board Setup > Design Rules > Constraints).\n"
" This may result in different fills from previous KiCad versions which used " " This may result in different fills from previous KiCad versions which used "
"the line thicknesses of the board boundary on the Edge Cuts layer." "the line thicknesses of the board boundary on the Edge Cuts layer."
msgstr "" msgstr ""
"如果重新填充此电路板上的覆铜, 则将应用铜边缘间距设置 (参见电路板配置 > 设计规" "如果重新填充此电路板上的覆铜, 则将应用铜边缘间距设置 (参见电路板配置 > "
"则 > 限制)。\n" "设计规则 > 约束)。\n"
"老版本的 KiCad 会将电路板边缘 (Edge Cuts 层) 的线宽作为铜间距, 因此新的填充结" "老版本的 KiCad 会将电路板边缘 (Edge Cuts 层) 的线宽作为铜间距, "
"果可能与老版本的填充结果不同。" "因此新的填充结果可能与老版本的填充结果不同。"
#: pcbnew/files.cpp:525 #: pcbnew/files.cpp:525
#, c-format #, c-format
@ -41817,7 +41863,7 @@ msgstr "%2$s 上的封装文本 '%1$s'"
#: pcbnew/pcb_text.cpp:390 #: pcbnew/pcb_text.cpp:390
#, c-format #, c-format
msgid "PCB Text '%s' on %s" msgid "PCB Text '%s' on %s"
msgstr "2$s 上的 PCB文本 '%1$s'" msgstr "%2$s 上的 PCB文本 '%1$s'"
#: pcbnew/pcb_textbox.cpp:468 #: pcbnew/pcb_textbox.cpp:468
#, c-format #, c-format
@ -45056,7 +45102,7 @@ msgstr "切换弧线编辑模式为保持端点, 或保持另一点的方向"
#: pcbnew/tools/pcb_actions.cpp:1989 #: pcbnew/tools/pcb_actions.cpp:1989
msgid "Position Relative To..." msgid "Position Relative To..."
msgstr "相对...的位置" msgstr "位置相对于..."
#: pcbnew/tools/pcb_actions.cpp:1990 #: pcbnew/tools/pcb_actions.cpp:1990
msgid "Positions the selected item(s) by an exact amount relative to another" msgid "Positions the selected item(s) by an exact amount relative to another"