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drc: sane default rules for via diameters/diff pair widths/diff pair gaps (required by the P&S)

This commit is contained in:
Tomasz Wlostowski 2020-10-08 23:57:53 +02:00
parent 5e4fb46aef
commit 5c2c66dd07
2 changed files with 13 additions and 0 deletions
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11
pcbnew/drc/drc_engine.cpp
View File

@ -100,10 +100,12 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT widthConstraint( DRC_CONSTRAINT_TYPE_TRACK_WIDTH );
widthConstraint.Value().SetMin( bds.m_TrackMinWidth );
widthConstraint.Value().SetOpt( bds.GetDefault()->GetTrackWidth() );
rule->AddConstraint( widthConstraint );
DRC_CONSTRAINT drillConstraint( DRC_CONSTRAINT_TYPE_HOLE_SIZE );
drillConstraint.Value().SetMin( bds.m_MinThroughDrill );
drillConstraint.Value().SetOpt( bds.GetDefault()->GetViaDrill() );
rule->AddConstraint( drillConstraint );
DRC_CONSTRAINT annulusConstraint( DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH );
@ -112,6 +114,7 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT diameterConstraint( DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
diameterConstraint.Value().SetMin( bds.m_ViasMinSize );
diameterConstraint.Value().SetOpt( bds.GetDefault()->GetViaDiameter() );
rule->AddConstraint( diameterConstraint );
DRC_CONSTRAINT edgeClearanceConstraint( DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE );
@ -134,6 +137,12 @@ void DRC_ENGINE::loadImplicitRules()
silkToSilkClearanceConstraint.Value().SetMin( 0 );
rule->AddConstraint( silkToSilkClearanceConstraint );
DRC_CONSTRAINT diffPairGapConstraint( DRC_CONSTRAINT_TYPE_DIFF_PAIR_GAP );
diffPairGapConstraint.Value().SetMin( bds.GetDefault()->GetClearance() );
diffPairGapConstraint.Value().SetOpt( bds.GetDefault()->GetClearance() );
rule->AddConstraint( diffPairGapConstraint );
// 2) micro-via specific defaults (new DRC doesn't treat microvias in any special way)
DRC_RULE* uViaRule = createImplicitRule( _( "board setup micro-via constraints" ));
@ -142,10 +151,12 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT uViaDrillConstraint( DRC_CONSTRAINT_TYPE_HOLE_SIZE );
uViaDrillConstraint.Value().SetMin( bds.m_MicroViasMinDrill );
uViaDrillConstraint.Value().SetOpt( bds.GetDefault()->GetuViaDrill() );
uViaRule->AddConstraint( uViaDrillConstraint );
DRC_CONSTRAINT uViaDiameterConstraint( DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
uViaDiameterConstraint.Value().SetMin( bds.m_MicroViasMinSize );
uViaDiameterConstraint.Value().SetOpt( bds.GetDefault()->GetuViaDiameter() );
uViaRule->AddConstraint( uViaDiameterConstraint );
if( !bds.m_MicroViasAllowed )

2
pcbnew/drc/drc_engine.h
View File

@ -177,6 +177,8 @@ public:
DRC_TEST_PROVIDER* GetTestProvider( const wxString& name ) const;
static int IsNetADiffPair( BOARD* aBoard, int aNet, int& aNetP, int& aNetN );
private:
void addRule( DRC_RULE* rule )
{