drc: ignore silk2pad/silk2silk violations for hidden text objects
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@ -28,6 +28,7 @@
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#include <class_module.h>
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#include <class_module.h>
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#include <class_pad.h>
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#include <class_pad.h>
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#include <class_zone.h>
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#include <class_zone.h>
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#include <class_pcb_text.h>
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DRC_TEST_PROVIDER::DRC_TEST_PROVIDER() :
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DRC_TEST_PROVIDER::DRC_TEST_PROVIDER() :
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m_drcEngine( nullptr )
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m_drcEngine( nullptr )
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@ -280,3 +281,22 @@ int DRC_TEST_PROVIDER::forEachGeometryItem( const std::vector<KICAD_T>& aTypes,
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return n;
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return n;
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}
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}
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bool DRC_TEST_PROVIDER::isInvisibleText( const BOARD_ITEM* aItem ) const
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{
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if( auto text = dyn_cast<const TEXTE_MODULE*>( aItem ) )
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{
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if( !text->IsVisible() )
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return true;
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}
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if( auto text = dyn_cast<const TEXTE_PCB*>( aItem ) )
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{
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if( !text->IsVisible() )
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return true;
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}
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return false;
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}
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@ -120,6 +120,8 @@ protected:
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virtual void accountCheck( const DRC_RULE* ruleToTest );
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virtual void accountCheck( const DRC_RULE* ruleToTest );
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virtual void accountCheck( const DRC_CONSTRAINT& constraintToTest );
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virtual void accountCheck( const DRC_CONSTRAINT& constraintToTest );
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bool isInvisibleText( const BOARD_ITEM* aItem ) const;
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EDA_UNITS userUnits() const;
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EDA_UNITS userUnits() const;
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DRC_ENGINE* m_drcEngine;
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DRC_ENGINE* m_drcEngine;
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std::unordered_map<const DRC_RULE*, int> m_stats;
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std::unordered_map<const DRC_RULE*, int> m_stats;
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@ -29,6 +29,10 @@
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#include <drc/drc_rule.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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#include <drc/drc_test_provider.h>
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#include <drc/drc_length_report.h>
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#include <drc/drc_length_report.h>
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#include <drc/drc_rtree.h>
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#include <geometry/shape.h>
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#include <geometry/shape_segment.h>
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#include <connectivity/connectivity_data.h>
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#include <connectivity/connectivity_data.h>
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#include <connectivity/from_to_cache.h>
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#include <connectivity/from_to_cache.h>
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@ -265,7 +269,7 @@ struct DIFF_PAIR_KEY
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int totalLengthP;
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int totalLengthP;
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};
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};
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static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp )
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static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp, DRC_RTREE& aTree )
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{
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{
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for( BOARD_CONNECTED_ITEM* itemP : aDp.itemsP )
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for( BOARD_CONNECTED_ITEM* itemP : aDp.itemsP )
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@ -295,6 +299,16 @@ static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp )
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if( coupled )
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if( coupled )
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{
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{
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SHAPE_SEGMENT checkSegStart( cpair.coupledP.A, cpair.coupledN.A );
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SHAPE_SEGMENT checkSegEnd( cpair.coupledP.B, cpair.coupledN.B );
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// check if there's anyting in between the segments suspected to be coupled. If
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// there's nothing, assume they are really coupled.
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if( !aTree.CheckColliding( &checkSegStart, sp->GetLayer() )
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&& !aTree.CheckColliding( &checkSegEnd, sp->GetLayer() ) )
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{
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cpair.parentP = sp;
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cpair.parentP = sp;
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cpair.parentN = sn;
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cpair.parentN = sn;
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@ -304,6 +318,7 @@ static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp )
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}
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}
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}
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}
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}
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}
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}
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bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
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bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
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@ -353,6 +368,20 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
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LSET::AllCuMask(), evaluateDpConstraints );
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LSET::AllCuMask(), evaluateDpConstraints );
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DRC_RTREE copperTree;
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auto addToTree =
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[&copperTree]( BOARD_ITEM *item ) -> bool
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{
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copperTree.insert( item );
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return true;
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};
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int numItems =
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forEachGeometryItem( { PCB_TRACE_T, PCB_VIA_T, PCB_PAD_T, PCB_ZONE_AREA_T, PCB_ARC_T },
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LSET::AllCuMask(), addToTree );
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reportAux( wxString::Format( _("DPs evaluated:") ) );
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reportAux( wxString::Format( _("DPs evaluated:") ) );
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for( auto& it : dpRuleMatches )
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for( auto& it : dpRuleMatches )
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@ -368,7 +397,7 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
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reportAux( wxString::Format( "Rule '%s', DP: (+) %s - (-) %s", it.first.parentRule->m_Name, nameP, nameN ) );
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reportAux( wxString::Format( "Rule '%s', DP: (+) %s - (-) %s", it.first.parentRule->m_Name, nameP, nameN ) );
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extractDiffPairCoupledItems( it.second );
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extractDiffPairCoupledItems( it.second, copperTree );
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it.second.totalCoupled = 0;
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it.second.totalCoupled = 0;
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it.second.totalLengthN = 0;
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it.second.totalLengthN = 0;
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@ -135,6 +135,12 @@ bool test::DRC_TEST_PROVIDER_SILK_TO_PAD::Run()
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int actual;
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int actual;
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VECTOR2I pos;
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VECTOR2I pos;
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if( isInvisibleText( aRefItem->parent ) )
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return true;
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if( isInvisibleText( aTestItem->parent ) )
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return true;
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accountCheck( constraint );
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accountCheck( constraint );
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if( !aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual, &pos ) )
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if( !aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual, &pos ) )
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@ -132,21 +132,11 @@ bool DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
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MODULE *parentModRef = nullptr;
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MODULE *parentModRef = nullptr;
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MODULE *parentModTest = nullptr;
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MODULE *parentModTest = nullptr;
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if( typeRef == PCB_MODULE_TEXT_T )
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if ( isInvisibleText( aRefItem->parent ) )
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{
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auto textRef = static_cast<TEXTE_MODULE*>( aRefItem->parent );
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if( !textRef->IsVisible( ) )
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return true;
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return true;
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}
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if( typeTest == PCB_MODULE_TEXT_T )
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if ( isInvisibleText( aTestItem->parent ) )
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{
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auto textTest = static_cast<TEXTE_MODULE*>( aTestItem->parent );
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if( !textTest->IsVisible( ) )
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return true;
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return true;
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}
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if( typeRef == PCB_MODULE_EDGE_T || typeRef == PCB_MODULE_TEXT_T )
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if( typeRef == PCB_MODULE_EDGE_T || typeRef == PCB_MODULE_TEXT_T )
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{
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{
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