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DRC connectivity check

This commit is contained in:
Tomasz Włostowski 2017-03-22 16:47:15 +01:00
parent edf1aac357
commit 6008abaad9
8 changed files with 150 additions and 143 deletions
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4
pcbnew/class_drc_item.cpp
View File

@ -39,8 +39,8 @@ wxString DRC_ITEM::GetErrorText() const
{
switch( m_ErrorCode )
{
case DRCE_UNCONNECTED_PADS:
return wxString( _( "Unconnected pads" ) );
case DRCE_UNCONNECTED_ITEMS:
return wxString( _( "Unconnected items" ) );
case DRCE_TRACK_NEAR_THROUGH_HOLE:
return wxString( _( "Track near thru-hole" ) );
case DRCE_TRACK_NEAR_PAD:

15
pcbnew/connectivity.cpp
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@ -514,3 +514,18 @@ const std::vector<VECTOR2I> CONNECTIVITY_DATA::NearestUnconnectedTargets(
return rv;
}
void CONNECTIVITY_DATA::GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges) const
{
for ( auto rnNet : m_nets )
{
if ( rnNet )
{
for( auto edge : rnNet->GetEdges() )
{
aEdges.push_back( edge );
}
}
}
}

3
pcbnew/connectivity.h
View File

@ -38,6 +38,7 @@
class CN_ITEM;
class CN_CLUSTER;
class CN_CONNECTIVITY_ALGO;
class CN_EDGE;
class BOARD;
class BOARD_CONNECTED_ITEM;
class BOARD_ITEM;
@ -167,6 +168,8 @@ public:
const std::vector<D_PAD*> GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem ) const;
void GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges ) const;
/**
* Function ClearDynamicRatsnest()
* Erases the temporary dynamic ratsnest (i.e. the ratsnest lines that)

59
pcbnew/drc.cpp
View File

@ -41,8 +41,9 @@
#include <class_draw_panel_gal.h>
#include <view/view.h>
#include <geometry/seg.h>
#include <ratsnest_data.h>
#include <connectivity.h>
#include <connectivity_algo.h>
#include <tool/tool_manager.h>
#include <tools/pcb_actions.h>
@ -546,55 +547,31 @@ void DRC::testTracks( wxWindow *aActiveWindow, bool aShowProgressBar )
void DRC::testUnconnected()
{
std::vector<CN_DISJOINT_NET_ENTRY> report;
auto connectivity = m_pcb->GetConnectivity();
connectivity->CheckConnectivity( report );
connectivity->Clear();
connectivity->Build(m_pcb); // just in case. This really needs to be reliable.
connectivity->RecalculateRatsnest();
for( auto ent : report )
std::vector<CN_EDGE> edges;
connectivity->GetUnconnectedEdges( edges );
for( const auto& edge : edges )
{
/* DRC_ITEM* uncItem = new DRC_ITEM( DRCE_UNCONNECTED_PADS,
msg,
padEnd->GetSelectMenuText(),
padStart->GetPosition(), padEnd->GetPosition() );*/
}
wxString t_src = edge.GetSourceNode()->Parent()->GetSelectMenuText();
wxString t_dst = edge.GetTargetNode()->Parent()->GetSelectMenuText();
auto src = edge.GetSourcePos();
auto dst = edge.GetTargetPos();
#if 0
if( (m_pcb->m_Status_Pcb & LISTE_RATSNEST_ITEM_OK) == 0 )
{
wxClientDC dc( m_pcbEditorFrame->GetCanvas() );
m_pcbEditorFrame->Compile_Ratsnest( &dc, true );
}
if( m_pcb->GetRatsnestsCount() == 0 )
return;
wxString msg;
for( unsigned ii = 0; ii < m_pcb->GetRatsnestsCount(); ++ii )
{
RATSNEST_ITEM& rat = m_pcb->m_FullRatsnest[ii];
if( (rat.m_Status & CH_ACTIF) == 0 )
continue;
D_PAD* padStart = rat.m_PadStart;
D_PAD* padEnd = rat.m_PadEnd;
msg = padStart->GetSelectMenuText() + wxT( " net " ) + padStart->GetNetname();
DRC_ITEM* uncItem = new DRC_ITEM( DRCE_UNCONNECTED_PADS,
msg,
padEnd->GetSelectMenuText(),
padStart->GetPosition(), padEnd->GetPosition() );
DRC_ITEM* uncItem = new DRC_ITEM( DRCE_UNCONNECTED_ITEMS,
t_src,
t_dst,
wxPoint( src.x, src.y ), wxPoint(dst.x, dst.y) );
m_unconnected.push_back( uncItem );
}
#endif
}
}

2
pcbnew/drc_stuff.h
View File

@ -38,7 +38,7 @@
/// DRC error codes:
#define DRCE_ 1 // not used yet
#define DRCE_UNCONNECTED_PADS 2 ///< pads are unconnected
#define DRCE_UNCONNECTED_ITEMS 2 ///< items are unconnected
#define DRCE_TRACK_NEAR_THROUGH_HOLE 3 ///< thru hole is too close to track
#define DRCE_TRACK_NEAR_PAD 4 ///< pad too close to track
#define DRCE_TRACK_NEAR_VIA 5 ///< track too close to via

94
pcbnew/editrack-part2.cpp
View File

@ -217,97 +217,3 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
return true;
}
void PCB_EDIT_FRAME::Show_1_Ratsnest( EDA_ITEM* item, wxDC* DC )
{
if( GetBoard()->IsElementVisible( LAYER_RATSNEST ) )
return;
Compile_Ratsnest( DC, true );
#if 0
if( item )
{
if( item->Type() == PCB_PAD_T )
{
pt_pad = (D_PAD*) item;
Module = pt_pad->GetParent();
}
if( pt_pad ) // Displaying the ratsnest of the corresponding net.
{
SetMsgPanel( pt_pad );
for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
{
RATSNEST_ITEM* net = &GetBoard()->m_FullRatsnest[ii];
if( net->GetNet() == pt_pad->GetNetCode() )
{
if( ( net->m_Status & CH_VISIBLE ) != 0 )
continue;
net->m_Status |= CH_VISIBLE;
if( ( net->m_Status & CH_ACTIF ) == 0 )
continue;
net->Draw( m_canvas, DC, GR_XOR, wxPoint( 0, 0 ) );
}
}
}
else
{
if( item->Type() == PCB_MODULE_TEXT_T )
{
if( item->GetParent() && ( item->GetParent()->Type() == PCB_MODULE_T ) )
Module = static_cast<MODULE*>( item->GetParent() );
}
else if( item->Type() == PCB_MODULE_T )
{
Module = static_cast<MODULE*>( item );
}
if( Module )
{
SetMsgPanel( Module );
pt_pad = Module->Pads();
for( ; pt_pad != NULL; pt_pad = pt_pad->Next() )
{
for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
{
RATSNEST_ITEM* net = &GetBoard()->m_FullRatsnest[ii];
if( ( net->m_PadStart == pt_pad ) || ( net->m_PadEnd == pt_pad ) )
{
if( net->m_Status & CH_VISIBLE )
continue;
net->m_Status |= CH_VISIBLE;
if( (net->m_Status & CH_ACTIF) == 0 )
continue;
net->Draw( m_canvas, DC, GR_XOR, wxPoint( 0, 0 ) );
}
}
}
pt_pad = NULL;
}
}
}
// Erase if no pad or module has been selected.
if( ( pt_pad == NULL ) && ( Module == NULL ) )
{
DrawGeneralRatsnest( DC );
for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
GetBoard()->m_FullRatsnest[ii].m_Status &= ~CH_VISIBLE;
}
#endif
}

114
pcbnew/ratsnest.cpp
View File

@ -44,6 +44,8 @@
#include <connectivity.h>
#include <ratsnest_data.h>
#include <wxPcbStruct.h>
/**
* Function Compile_Ratsnest
* Create the entire board ratsnest.
@ -105,9 +107,16 @@ void PCB_BASE_FRAME::DrawGeneralRatsnest( wxDC* aDC, int aNetcode )
{
for ( const auto& edge : net->GetEdges() )
{
auto s = edge.GetSourcePos();
auto d = edge.GetTargetPos();
GRLine( m_canvas->GetClipBox(), aDC, wxPoint(s.x, s.y), wxPoint(d.x, d.y), 0, color );
if ( edge.IsVisible() )
{
auto s = edge.GetSourcePos();
auto d = edge.GetTargetPos();
auto sn = edge.GetSourceNode();
auto dn = edge.GetTargetNode();
if ( !sn->GetNoLine() && !dn->GetNoLine() )
GRLine( m_canvas->GetClipBox(), aDC, wxPoint(s.x, s.y), wxPoint(d.x, d.y), 0, color );
}
}
}
}
@ -229,3 +238,102 @@ void MODULE::DrawOutlinesWhenMoving( EDA_DRAW_PANEL* panel, wxDC* DC,
frame->TraceModuleRatsNest( DC );
}
}
void PCB_EDIT_FRAME::Show_1_Ratsnest( EDA_ITEM* item, wxDC* DC )
{
if( GetBoard()->IsElementVisible(RATSNEST_VISIBLE) )
return;
Compile_Ratsnest( DC, true );
printf("show1r: %p\n", item);
auto connectivity = GetBoard()->GetConnectivity();
// FIXME
#if 0
if( item )
{
if( item->Type() == PCB_PAD_T )
{
pt_pad = (D_PAD*) item;
Module = pt_pad->GetParent();
}
if( pt_pad ) // Displaying the ratsnest of the corresponding net.
{
SetMsgPanel( pt_pad );
for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
{
RATSNEST_ITEM* net = &GetBoard()->m_FullRatsnest[ii];
if( net->GetNet() == pt_pad->GetNetCode() )
{
if( ( net->m_Status & CH_VISIBLE ) != 0 )
continue;
net->m_Status |= CH_VISIBLE;
if( ( net->m_Status & CH_ACTIF ) == 0 )
continue;
net->Draw( m_canvas, DC, GR_XOR, wxPoint( 0, 0 ) );
}
}
}
else
{
if( item->Type() == PCB_MODULE_TEXT_T )
{
if( item->GetParent() && ( item->GetParent()->Type() == PCB_MODULE_T ) )
Module = static_cast<MODULE*>( item->GetParent() );
}
else if( item->Type() == PCB_MODULE_T )
{
Module = static_cast<MODULE*>( item );
}
if( Module )
{
SetMsgPanel( Module );
pt_pad = Module->Pads();
for( ; pt_pad != NULL; pt_pad = pt_pad->Next() )
{
for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
{
RATSNEST_ITEM* net = &GetBoard()->m_FullRatsnest[ii];
if( ( net->m_PadStart == pt_pad ) || ( net->m_PadEnd == pt_pad ) )
{
if( net->m_Status & CH_VISIBLE )
continue;
net->m_Status |= CH_VISIBLE;
if( (net->m_Status & CH_ACTIF) == 0 )
continue;
net->Draw( m_canvas, DC, GR_XOR, wxPoint( 0, 0 ) );
}
}
}
pt_pad = NULL;
}
}
}
// Erase if no pad or module has been selected.
if( ( pt_pad == NULL ) && ( Module == NULL ) )
{
DrawGeneralRatsnest( DC );
for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
GetBoard()->m_FullRatsnest[ii].m_Status &= ~CH_VISIBLE;
}
#endif
}

2
pcbnew/zones_convert_brd_items_to_polygons_with_Boost.cpp
View File

@ -437,8 +437,6 @@ void ZONE_CONTAINER::AddClearanceAreasPolygonsToPolysList_NG( BOARD* aPcb )
SHAPE_POLY_SET solidAreas = *m_smoothedPoly;
printf("VC %d\n", solidAreas.VertexCount());
solidAreas.Inflate( -outline_half_thickness, segsPerCircle );
solidAreas.Simplify( POLY_CALC_MODE );