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Translated using Weblate (Chinese (Simplified)) 

Currently translated at 99.9% (6989 of 6990 strings)

Translation: KiCad EDA/master source
Translate-URL: https://hosted.weblate.org/projects/kicad/master-source/zh_Hans/
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taotieren 2021-06-18 13:12:15 +00:00 committed by Hosted Weblate
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commit 8b27f37ca3
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translation/pofiles/zh_CN.po
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@ -10,8 +10,8 @@ msgstr ""
"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2021-06-10 13:22-0700\n"
"PO-Revision-Date: 2021-06-18 13:11+0000\n"
"Last-Translator: Rigo Ligo <rigoligo03@gmail.com>\n"
"PO-Revision-Date: 2021-06-18 13:12+0000\n"
"Last-Translator: taotieren <admin@taotieren.com>\n"
"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
"kicad/master-source/zh_Hans/>\n"
"Language: zh_CN\n"
@ -27743,7 +27743,7 @@ msgstr ""
"\n"
" * buried_via （埋孔）\n"
" * graphic （图形）\n"
" * hole （孔）\n"
" * hole （通孔）\n"
" * micro_via （微孔）\n"
" * pad （焊盘）\n"
" * text （文字）\n"
@ -28867,10 +28867,8 @@ msgid ""
"This may result in different fills from previous KiCad versions which used "
"the line thicknesses of the board boundary on the Edge Cuts layer."
msgstr ""
"如果此电路板上的覆铜被重新填充，将应用铜边缘间隙设置 （见电路板配置 > 设计规"
"则 >限制）。\n"
"这可能导致来自先前 KiCad 版本的不同填充，这些版本会将电路板边缘的线路厚度用"
"于 Edge Cuts 层。"
"如果此电路板上的覆铜被重新填充，将应用铜边缘间隙设置 （见电路板配置 > 设计规则 >限制）。\n"
"这可能导致来自先前 KiCad 版本的不同填充，这些版本会将电路板边缘的线粗细用于 Edge Cuts 层。"
#: pcbnew/files.cpp:548
msgid "Edge Clearance Warning"
@ -32418,11 +32416,11 @@ msgstr "层名称"
#: pcbnew/tools/drawing_stackup_table_tool.cpp:265
msgid "Thickness (mm)"
msgstr "厚度 (mm)"
msgstr "粗细 (mm)"
#: pcbnew/tools/drawing_stackup_table_tool.cpp:268
msgid "Thickness (mils)"
msgstr "厚度 (mils)"
msgstr "粗细 (mils)"
#: pcbnew/tools/drawing_stackup_table_tool.cpp:281
msgid "Loss Tangent"