Check for zone-zone overlap
Instead of just checking for the zone outline, we adjust to check the full fill area of the zones for intersection and overlaps
This commit is contained in:
Seth Hillbrand
parent
2689037bde
commit
954b265839
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@ -364,6 +364,14 @@ public:
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return A + ( B - A ) / 2;
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}
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bool operator<( const SEG& aSeg ) const
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{
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if( A == aSeg.A )
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return B < aSeg.B;
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return A < aSeg.A;
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}
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private:
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bool ccw( const VECTOR2I& aA, const VECTOR2I& aB, const VECTOR2I &aC ) const;
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@ -837,6 +837,11 @@ public:
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return ( t1.m_Pos != t2.m_Pos || t1.m_Size != t2.m_Size );
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}
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const bool IsValid() const
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{
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return m_init;
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}
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private:
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Vec m_Pos; // Rectangle Origin
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Vec m_Size; // Rectangle Size
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@ -28,6 +28,7 @@
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#include <pcb_shape.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <thread_pool.h>
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#include <zone.h>
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#include <geometry/seg.h>
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@ -41,6 +42,8 @@
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#include <drc/drc_test_provider_clearance_base.h>
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#include <pcb_dimension.h>
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#include <future>
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/*
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Copper clearance test. Checks all copper items (pads, vias, tracks, drawings, zones) for their
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electrical clearance.
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@ -1028,19 +1031,81 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
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bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
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bool testIntersects = !m_drcEngine->IsErrorLimitExceeded( DRCE_ZONES_INTERSECT );
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SHAPE_POLY_SET buffer;
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SHAPE_POLY_SET* boardOutline = nullptr;
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DRC_CONSTRAINT constraint;
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int zone2zoneClearance;
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bool cancelled = false;
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std::vector<std::map<PCB_LAYER_ID, std::vector<SEG>>> poly_segments;
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if( m_board->GetBoardPolygonOutlines( buffer ) )
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boardOutline = &buffer;
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poly_segments.resize( m_board->m_DRCCopperZones.size() );
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// Contains the index for zoneA, zoneB, the conflict point, the actual clearance, the required clearance, and the layer
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using report_data = std::tuple<int, int, VECTOR2I, int, int, PCB_LAYER_ID>;
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const int invalid_zone = -1;
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std::vector<std::future<report_data>> futures;
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thread_pool& tp = GetKiCadThreadPool();
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auto checkZones = [testClearance, testIntersects, &poly_segments, &cancelled, invalid_zone]
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( int zoneA, int zoneB,
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int zone2zoneClearance, PCB_LAYER_ID layer ) -> report_data
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{
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// Iterate through all the segments of refSmoothedPoly
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std::map<VECTOR2I, int> conflictPoints;
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std::vector<SEG>& refSegments = poly_segments[zoneA][layer];
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std::vector<SEG>& testSegments = poly_segments[zoneB][layer];
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bool reported = false;
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auto invalid_result = std::make_tuple( invalid_zone, invalid_zone, VECTOR2I(), 0, 0, F_Cu );
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for( SEG& refSegment : refSegments )
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{
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int ax1 = refSegment.A.x;
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int ay1 = refSegment.A.y;
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int ax2 = refSegment.B.x;
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int ay2 = refSegment.B.y;
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// Iterate through all the segments in smoothed_polys[ia2]
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for( SEG& testSegment : testSegments )
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{
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// Build test segment
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VECTOR2I pt;
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int bx1 = testSegment.A.x;
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int by1 = testSegment.A.y;
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int bx2 = testSegment.B.x;
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int by2 = testSegment.B.y;
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// We have ensured that the A segment starts before the B segment, so if the
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// A segment ends before the B segment starts, we can skip to the next A
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if( ax2 < bx1 )
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break;
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int d = GetClearanceBetweenSegments( bx1, by1, bx2, by2, 0,
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ax1, ay1, ax2, ay2, 0,
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zone2zoneClearance, &pt.x, &pt.y );
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if( d < zone2zoneClearance )
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{
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if( d == 0 && testIntersects )
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reported = true;
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else if( testClearance )
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reported = true;
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if( reported )
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return std::make_tuple( zoneA, zoneB, pt, d, zone2zoneClearance, layer );
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}
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if( cancelled )
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return invalid_result;
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}
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}
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return invalid_result;
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};
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for( int layer_id = F_Cu; layer_id <= B_Cu; ++layer_id )
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{
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PCB_LAYER_ID layer = static_cast<PCB_LAYER_ID>( layer_id );
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std::vector<SHAPE_POLY_SET> smoothed_polys;
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smoothed_polys.resize( m_board->m_DRCCopperZones.size() );
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int zone2zoneClearance;
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// Skip over layers not used on the current board
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if( !m_board->IsLayerEnabled( layer ) )
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@ -1050,12 +1115,30 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
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{
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if( m_board->m_DRCCopperZones[ii]->IsOnLayer( layer ) )
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{
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m_board->m_DRCCopperZones[ii]->BuildSmoothedPoly( smoothed_polys[ii], layer,
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boardOutline );
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SHAPE_POLY_SET poly =
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*m_board->m_DRCCopperZones[ii]->GetFilledPolysList( layer );
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std::vector<SEG>& poly_segs = poly_segments[ii][layer];
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poly.Fracture( SHAPE_POLY_SET::PM_FAST );
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poly.BuildBBoxCaches();
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poly_segs.reserve( poly.FullPointCount() );
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for( auto it = poly.IterateSegmentsWithHoles(); it; it++ )
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{
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SEG seg = *it;
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if( seg.A.x > seg.B.x )
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seg.Reverse();
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poly_segs.push_back( seg );
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}
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std::sort( poly_segs.begin(), poly_segs.end() );
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}
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}
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// iterate through all areas
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std::vector<std::pair<int, int>> zonePairs;
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for( size_t ia = 0; ia < m_board->m_DRCCopperZones.size(); ia++ )
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{
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if( !reportProgress( layer_id * m_board->m_DRCCopperZones.size() + ia,
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@ -1081,100 +1164,62 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
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if( zoneA->GetNetCode() == zoneB->GetNetCode() && zoneA->GetNetCode() >= 0 )
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continue;
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// test for different priorities
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if( zoneA->GetAssignedPriority() != zoneB->GetAssignedPriority() )
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continue;
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// rule areas may overlap at will
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if( zoneA->GetIsRuleArea() || zoneB->GetIsRuleArea() )
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continue;
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// Examine a candidate zone: compare zoneB to zoneA
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SHAPE_POLY_SET* polyA = m_board->m_DRCCopperZones[ia]->GetFill( layer );
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SHAPE_POLY_SET* polyB = m_board->m_DRCCopperZones[ia2]->GetFill( layer );
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if( !polyA->BBoxFromCaches().Intersects( polyB->BBoxFromCaches() ) )
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continue;
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// Get clearance used in zone to zone test.
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constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, zoneA, zoneB, layer );
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zone2zoneClearance = constraint.GetValue().Min();
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if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
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if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || zone2zoneClearance <= 0 )
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continue;
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if( testIntersects )
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futures.push_back( tp.submit( checkZones, ia, ia2, zone2zoneClearance, layer ) );
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}
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}
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}
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for( auto& task : futures )
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{
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if( !task.valid() )
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continue;
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std::future_status result;
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while( true )
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{
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result = task.wait_for( std::chrono::milliseconds( 200 ) );
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if( m_drcEngine->IsCancelled() )
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{
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cancelled = true;
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break;
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}
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if( result == std::future_status::ready )
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{
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report_data data = task.get();
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int zoneA_id = std::get<0>( data );
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int zoneB_id = std::get<1>( data );
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VECTOR2I pt = std::get<2>( data );
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int actual = std::get<3>( data );
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int required = std::get<4>( data );
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PCB_LAYER_ID layer = std::get<5>( data );
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if( zoneA_id != invalid_zone )
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{
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// test for some corners of zoneA inside zoneB
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for( auto it = smoothed_polys[ia].IterateWithHoles(); it; it++ )
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{
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VECTOR2I currentVertex = *it;
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ZONE* zoneA = m_board->m_DRCCopperZones[zoneA_id];
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ZONE* zoneB = m_board->m_DRCCopperZones[zoneB_id];
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if( smoothed_polys[ia2].Contains( currentVertex ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
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drce->SetItems( zoneA, zoneB );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, currentVertex, layer );
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}
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}
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// test for some corners of zoneB inside zoneA
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for( auto it = smoothed_polys[ia2].IterateWithHoles(); it; it++ )
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{
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VECTOR2I currentVertex = *it;
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if( smoothed_polys[ia].Contains( currentVertex ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
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drce->SetItems( zoneB, zoneA );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, currentVertex, layer );
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}
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}
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}
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// Iterate through all the segments of refSmoothedPoly
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std::map<VECTOR2I, int> conflictPoints;
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for( auto refIt = smoothed_polys[ia].IterateSegmentsWithHoles(); refIt; refIt++ )
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{
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// Build ref segment
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SEG refSegment = *refIt;
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// Iterate through all the segments in smoothed_polys[ia2]
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for( auto it = smoothed_polys[ia2].IterateSegmentsWithHoles(); it; it++ )
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{
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// Build test segment
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SEG testSegment = *it;
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VECTOR2I pt;
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int ax1, ay1, ax2, ay2;
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ax1 = refSegment.A.x;
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ay1 = refSegment.A.y;
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ax2 = refSegment.B.x;
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ay2 = refSegment.B.y;
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int bx1, by1, bx2, by2;
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bx1 = testSegment.A.x;
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by1 = testSegment.A.y;
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bx2 = testSegment.B.x;
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by2 = testSegment.B.y;
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int d = GetClearanceBetweenSegments( bx1, by1, bx2, by2, 0,
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ax1, ay1, ax2, ay2, 0,
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zone2zoneClearance, &pt.x, &pt.y );
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if( d < zone2zoneClearance )
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{
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if( conflictPoints.count( pt ) )
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conflictPoints[ pt ] = std::min( conflictPoints[ pt ], d );
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else
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conflictPoints[ pt ] = d;
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}
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}
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}
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for( const std::pair<const VECTOR2I, int>& conflict : conflictPoints )
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{
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int actual = conflict.second;
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constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, zoneA, zoneB, layer );
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std::shared_ptr<DRC_ITEM> drce;
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if( actual <= 0 && testIntersects )
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@ -1186,7 +1231,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
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drce = DRC_ITEM::Create( DRCE_CLEARANCE );
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wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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zone2zoneClearance,
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required,
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std::max( actual, 0 ) );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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@ -1197,13 +1242,13 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
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drce->SetItems( zoneA, zoneB );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, conflict.first, layer );
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reportViolation( drce, pt, layer );
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}
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}
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if( m_drcEngine->IsCancelled() )
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return;
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break;
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}
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}
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}
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}
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@ -0,0 +1,524 @@
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(kicad_pcb (version 20230620) (generator pcbnew)
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(general
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(thickness 1.6)
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)
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(paper "A4")
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(layers
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(0 "F.Cu" signal)
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(31 "B.Cu" signal)
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(32 "B.Adhes" user "B.Adhesive")
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(33 "F.Adhes" user "F.Adhesive")
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(34 "B.Paste" user)
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(35 "F.Paste" user)
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(36 "B.SilkS" user "B.Silkscreen")
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(37 "F.SilkS" user "F.Silkscreen")
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(38 "B.Mask" user)
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(39 "F.Mask" user)
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(40 "Dwgs.User" user "User.Drawings")
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(41 "Cmts.User" user "User.Comments")
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(42 "Eco1.User" user "User.Eco1")
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(43 "Eco2.User" user "User.Eco2")
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(44 "Edge.Cuts" user)
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(45 "Margin" user)
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(46 "B.CrtYd" user "B.Courtyard")
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(47 "F.CrtYd" user "F.Courtyard")
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(48 "B.Fab" user)
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(49 "F.Fab" user)
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(50 "User.1" user)
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(51 "User.2" user)
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(52 "User.3" user)
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(53 "User.4" user)
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(54 "User.5" user)
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(55 "User.6" user)
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(56 "User.7" user)
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(57 "User.8" user)
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(58 "User.9" user)
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)
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(setup
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(pad_to_mask_clearance 0)
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(pcbplotparams
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(layerselection 0x00010fc_ffffffff)
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(plot_on_all_layers_selection 0x0000000_00000000)
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(disableapertmacros false)
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(usegerberextensions false)
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(usegerberattributes true)
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(usegerberadvancedattributes true)
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(creategerberjobfile true)
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(dashed_line_dash_ratio 12.000000)
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(dashed_line_gap_ratio 3.000000)
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(svgprecision 4)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15.000000)
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||||
(pdf_front_fp_property_popups true)
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(pdf_back_fp_property_popups true)
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||||
(dxfpolygonmode true)
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(dxfimperialunits true)
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(dxfusepcbnewfont true)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(sketchpadsonfab false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory "")
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)
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)
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(net 0 "")
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(net 1 "A")
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(net 2 "B")
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(footprint "TestPoint:TestPoint_Pad_1.0x1.0mm" (layer "F.Cu")
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(tstamp 0662cfad-e2af-4a28-8e06-54487b2d060f)
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(at 126.383886 85.958221)
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(descr "SMD rectangular pad as test Point, square 1.0mm side length")
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(tags "test point SMD pad rectangle square")
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(property "Reference" "REF**" (at 0 -1.448 0 unlocked) (layer "F.SilkS") (tstamp a9c377d9-d9a8-4957-9ef2-653acbec4dad)
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(effects (font (size 1 1) (thickness 0.1)))
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)
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(property "Value" "TestPoint_Pad_1.0x1.0mm" (at 0 1.55 0 unlocked) (layer "F.Fab") (tstamp 8722d65f-d023-4ca1-9653-ede49a60bc5e)
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(effects (font (size 1 1) (thickness 0.15)))
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||||
)
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||||
(property "Footprint" "TestPoint:TestPoint_Pad_1.0x1.0mm" (at 0 0 0 unlocked) (layer "F.Fab") hide (tstamp 1f52001b-ae94-49e9-b2b5-6673a1b966af)
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||||
(effects (font (size 1 1) (thickness 0.15)))
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||||
)
|
||||
(property "Datasheet" "" (at 0 0 0 unlocked) (layer "F.Fab") hide (tstamp 2cc1d293-3904-4185-9d78-14af283b2a39)
|
||||
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(xy 133.673258 81.122396)
|
||||
(xy 133.684464 81.173907)
|
||||
(xy 133.684464 90.472051)
|
||||
(xy 133.664779 90.53909)
|
||||
(xy 133.611975 90.584845)
|
||||
(xy 133.560464 90.596051)
|
||||
(xy 120.813064 90.596051)
|
||||
(xy 120.746025 90.576366)
|
||||
(xy 120.70027 90.523562)
|
||||
(xy 120.689064 90.472051)
|
||||
(xy 120.689064 85.554594)
|
||||
(xy 127.622292 85.554594)
|
||||
(xy 127.622292 85.852438)
|
||||
(xy 127.628693 85.911966)
|
||||
(xy 127.628695 85.911973)
|
||||
(xy 127.678937 86.04668)
|
||||
(xy 127.678941 86.046687)
|
||||
(xy 127.765101 86.161781)
|
||||
(xy 127.765104 86.161784)
|
||||
(xy 127.880198 86.247944)
|
||||
(xy 127.880205 86.247948)
|
||||
(xy 128.014912 86.29819)
|
||||
(xy 128.014919 86.298192)
|
||||
(xy 128.074447 86.304593)
|
||||
(xy 128.074464 86.304594)
|
||||
(xy 128.372292 86.304594)
|
||||
(xy 128.372292 85.554594)
|
||||
(xy 128.872292 85.554594)
|
||||
(xy 128.872292 86.304594)
|
||||
(xy 129.17012 86.304594)
|
||||
(xy 129.170136 86.304593)
|
||||
(xy 129.229664 86.298192)
|
||||
(xy 129.229671 86.29819)
|
||||
(xy 129.364378 86.247948)
|
||||
(xy 129.364385 86.247944)
|
||||
(xy 129.479479 86.161784)
|
||||
(xy 129.479482 86.161781)
|
||||
(xy 129.565642 86.046687)
|
||||
(xy 129.565646 86.04668)
|
||||
(xy 129.615888 85.911973)
|
||||
(xy 129.61589 85.911966)
|
||||
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|
||||
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|
||||
(xy 129.622292 85.554594)
|
||||
(xy 128.872292 85.554594)
|
||||
(xy 128.372292 85.554594)
|
||||
(xy 127.622292 85.554594)
|
||||
(xy 120.689064 85.554594)
|
||||
(xy 120.689064 85.054594)
|
||||
(xy 127.622292 85.054594)
|
||||
(xy 128.372292 85.054594)
|
||||
(xy 128.372292 84.304594)
|
||||
(xy 128.872292 84.304594)
|
||||
(xy 128.872292 85.054594)
|
||||
(xy 129.622292 85.054594)
|
||||
(xy 129.622292 84.756766)
|
||||
(xy 129.622291 84.756749)
|
||||
(xy 129.61589 84.697221)
|
||||
(xy 129.615888 84.697214)
|
||||
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|
||||
(xy 129.565642 84.5625)
|
||||
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|
||||
(xy 129.479479 84.447403)
|
||||
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|
||||
(xy 129.364378 84.361239)
|
||||
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|
||||
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|
||||
(xy 129.170136 84.304594)
|
||||
(xy 128.872292 84.304594)
|
||||
(xy 128.372292 84.304594)
|
||||
(xy 128.074447 84.304594)
|
||||
(xy 128.014919 84.310995)
|
||||
(xy 128.014912 84.310997)
|
||||
(xy 127.880205 84.361239)
|
||||
(xy 127.880198 84.361243)
|
||||
(xy 127.765104 84.447403)
|
||||
(xy 127.765101 84.447406)
|
||||
(xy 127.678941 84.5625)
|
||||
(xy 127.678937 84.562507)
|
||||
(xy 127.628695 84.697214)
|
||||
(xy 127.628693 84.697221)
|
||||
(xy 127.622292 84.756749)
|
||||
(xy 127.622292 85.054594)
|
||||
(xy 120.689064 85.054594)
|
||||
(xy 120.689064 81.173907)
|
||||
(xy 120.708749 81.106868)
|
||||
(xy 120.761553 81.061113)
|
||||
(xy 120.813064 81.049907)
|
||||
(xy 133.560464 81.049907)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.0,
|
||||
"height": 1.0,
|
||||
"width": 1.0
|
||||
},
|
||||
"silk_line_width": 0.09999999999999999,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.09999999999999999,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.0,
|
||||
"min_via_annular_width": 0.09999999999999999,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_onpadsmd": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_ontrackend": false,
|
||||
"td_onviapad": true
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [],
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "intersectingzones.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
|
|
@ -187,3 +187,63 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressionsNoFill, DRC_REGRESSION_TEST_FIXTURE )
|
||||
{
|
||||
// These documents at one time failed to catch DRC errors that they should have but only
|
||||
// when the zones were filled. In other words, refilling the zone will fix the error, but
|
||||
// DRC should have caught it regardless
|
||||
|
||||
std::vector< std::pair<wxString, int> > tests =
|
||||
{
|
||||
{ "intersectingzones", 1 } // zones are too close to each other
|
||||
};
|
||||
|
||||
for( const std::pair<wxString, int>& entry : tests )
|
||||
{
|
||||
KI_TEST::LoadBoard( m_settingsManager, entry.first, m_board );
|
||||
|
||||
std::vector<DRC_ITEM> violations;
|
||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||
|
||||
// Disable DRC tests not useful in this testcase
|
||||
bds.m_DRCSeverities[ DRCE_COPPER_SLIVER ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||
bds.m_DRCSeverities[ DRCE_LIB_FOOTPRINT_ISSUES ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||
bds.m_DRCSeverities[ DRCE_LIB_FOOTPRINT_MISMATCH ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||
|
||||
bds.m_DRCEngine->SetViolationHandler(
|
||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, VECTOR2I aPos, int aLayer )
|
||||
{
|
||||
PCB_MARKER temp( aItem, aPos );
|
||||
|
||||
if( bds.m_DrcExclusions.find( temp.Serialize() ) == bds.m_DrcExclusions.end() )
|
||||
violations.push_back( *aItem );
|
||||
} );
|
||||
|
||||
bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||
|
||||
if( violations.size() == entry.second )
|
||||
{
|
||||
BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning
|
||||
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", entry.first ) );
|
||||
}
|
||||
else
|
||||
{
|
||||
BOOST_CHECK_EQUAL( violations.size(), entry.second );
|
||||
|
||||
UNITS_PROVIDER unitsProvider( pcbIUScale, EDA_UNITS::INCHES );
|
||||
|
||||
std::map<KIID, EDA_ITEM*> itemMap;
|
||||
m_board->FillItemMap( itemMap );
|
||||
|
||||
for( const DRC_ITEM& item : violations )
|
||||
{
|
||||
BOOST_TEST_MESSAGE( item.ShowReport( &unitsProvider, RPT_SEVERITY_ERROR,
|
||||
itemMap ) );
|
||||
}
|
||||
|
||||
BOOST_ERROR( wxString::Format( "DRC regression: %s, failed", entry.first ) );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue