Test the via types to the design rules
Fixes: lp:1741695 * https://bugs.launchpad.net/kicad/+bug/1741695
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@ -71,6 +71,10 @@ wxString DRC_ITEM::GetErrorText() const
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return wxString( _( "Via hole > diameter" ) );
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case DRCE_MICRO_VIA_INCORRECT_LAYER_PAIR:
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return wxString( _( "Micro Via: incorrect layer pairs (not adjacent)" ) );
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case DRCE_MICRO_VIA_NOT_ALLOWED:
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return wxString( _( "Micro Via: not allowed" ) );
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case DRCE_BURIED_VIA_NOT_ALLOWED:
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return wxString( _( "Buried Via: not allowed" ) );
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case COPPERAREA_INSIDE_COPPERAREA:
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return wxString( _( "Copper area inside copper area" ) );
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case COPPERAREA_CLOSE_TO_COPPERAREA:
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@ -202,11 +202,31 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
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return false;
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}
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// test if the type of via is allowed due to design rules
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if( ( refvia->GetViaType() == VIA_MICROVIA ) &&
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( m_pcb->GetDesignSettings().m_MicroViasAllowed == false ) )
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{
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m_currentMarker = fillMarker( refvia, NULL,
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DRCE_MICRO_VIA_NOT_ALLOWED, m_currentMarker );
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return false;
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}
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// test if the type of via is allowed due to design rules
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if( ( refvia->GetViaType() == VIA_BLIND_BURIED ) &&
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( m_pcb->GetDesignSettings().m_BlindBuriedViaAllowed == false ) )
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{
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m_currentMarker = fillMarker( refvia, NULL,
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DRCE_BURIED_VIA_NOT_ALLOWED, m_currentMarker );
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return false;
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}
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// For microvias: test if they are blind vias and only between 2 layers
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// because they are used for very small drill size and are drill by laser
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// and **only one layer** can be drilled
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if( refvia->GetViaType() == VIA_MICROVIA )
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{
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PCB_LAYER_ID layer1, layer2;
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bool err = true;
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@ -227,6 +247,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
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return false;
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}
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}
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}
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else // This is a track segment
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{
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@ -36,6 +36,10 @@
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#define BAD_DRC 1
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// DRC error codes could be defined by an enum.
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// however a #define is used because error code value is displayed in DRC messages,
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// and using #define that shows each numerical value helps for debug.
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/// DRC error codes:
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#define DRCE_ 1 // not used yet
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#define DRCE_UNCONNECTED_ITEMS 2 ///< items are unconnected
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@ -83,7 +87,9 @@
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#define DRCE_OVERLAPPING_FOOTPRINTS 44 ///< footprint courtyards overlap
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#define DRCE_MISSING_COURTYARD_IN_FOOTPRINT 45 ///< footprint has no courtyard defined
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#define DRCE_MALFORMED_COURTYARD_IN_FOOTPRINT 46 ///< footprint has a courtyard but malformed
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///< (not convetrible to polygon)
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///< (not convertible to a closed polygon with holes)
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#define DRCE_MICRO_VIA_NOT_ALLOWED 47 ///< micro vias are not allowed
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#define DRCE_BURIED_VIA_NOT_ALLOWED 48 ///< buried vias are not allowed
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class EDA_DRAW_PANEL;
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