Implement PTH/NPTH/courtyard collision tests.
Fixes https://gitlab.com/kicad/code/kicad/issues/9081
This commit is contained in:
Jeff Young
parent
1fe4aaa64f
commit
a397e85589
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@ -25,6 +25,8 @@
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#include <drc/drc_engine.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_rule.h>
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#include <pad.h>
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#include <geometry/shape_segment.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include <footprint.h>
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#include <footprint.h>
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@ -34,6 +36,8 @@
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- DRCE_OVERLAPPING_FOOTPRINTS
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- DRCE_OVERLAPPING_FOOTPRINTS
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- DRCE_MISSING_COURTYARD
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- DRCE_MISSING_COURTYARD
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- DRCE_MALFORMED_COURTYARD
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- DRCE_MALFORMED_COURTYARD
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- DRCE_PTH_IN_COURTYARD,
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- DRCE_NPTH_IN_COURTYARD,
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TODO: do an actual clearance check instead of polygon intersection. Treat closed outlines
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TODO: do an actual clearance check instead of polygon intersection. Treat closed outlines
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as filled and allow open curves in the courtyard.
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as filled and allow open curves in the courtyard.
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@ -145,9 +149,6 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
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{
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{
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const int delta = 100; // This is the number of tests between 2 calls to the progress bar
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const int delta = 100; // This is the number of tests between 2 calls to the progress bar
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS) )
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return true; // continue with other tests
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if( !reportPhase( _( "Checking footprints for overlapping courtyards..." ) ) )
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if( !reportPhase( _( "Checking footprints for overlapping courtyards..." ) ) )
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return false; // DRC cancelled
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return false; // DRC cancelled
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@ -158,15 +159,24 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
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if( !reportProgress( ii++, m_board->Footprints().size(), delta ) )
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if( !reportProgress( ii++, m_board->Footprints().size(), delta ) )
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return false; // DRC cancelled
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return false; // DRC cancelled
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS) )
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS)
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break;
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&& m_drcEngine->IsErrorLimitExceeded( DRCE_PTH_IN_COURTYARD )
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&& m_drcEngine->IsErrorLimitExceeded( DRCE_NPTH_IN_COURTYARD ) )
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{
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return true; // continue with other tests
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}
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FOOTPRINT* fpA = *itA;
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FOOTPRINT* fpA = *itA;
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const SHAPE_POLY_SET& frontA = fpA->GetPolyCourtyard( F_CrtYd );
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const SHAPE_POLY_SET& frontA = fpA->GetPolyCourtyard( F_CrtYd );
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const SHAPE_POLY_SET& backA = fpA->GetPolyCourtyard( B_CrtYd );
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const SHAPE_POLY_SET& backA = fpA->GetPolyCourtyard( B_CrtYd );
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if( frontA.OutlineCount() == 0 && backA.OutlineCount() == 0 )
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if( frontA.OutlineCount() == 0 && backA.OutlineCount() == 0
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continue; // No courtyards defined
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&& m_drcEngine->IsErrorLimitExceeded( DRCE_PTH_IN_COURTYARD )
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&& m_drcEngine->IsErrorLimitExceeded( DRCE_NPTH_IN_COURTYARD ) )
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{
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// No courtyards defined and no hole testing against other footprint's courtyards
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continue;
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}
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BOX2I frontBBox = frontA.BBoxFromCaches();
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BOX2I frontBBox = frontA.BBoxFromCaches();
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BOX2I backBBox = backA.BBoxFromCaches();
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BOX2I backBBox = backA.BBoxFromCaches();
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@ -174,9 +184,12 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
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frontBBox.Inflate( m_largestClearance );
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frontBBox.Inflate( m_largestClearance );
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backBBox.Inflate( m_largestClearance );
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backBBox.Inflate( m_largestClearance );
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EDA_RECT fpABBox = fpA->GetBoundingBox();
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for( auto itB = itA + 1; itB != m_board->Footprints().end(); itB++ )
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for( auto itB = itA + 1; itB != m_board->Footprints().end(); itB++ )
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{
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{
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FOOTPRINT* fpB = *itB;
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FOOTPRINT* fpB = *itB;
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EDA_RECT fpBBBox = fpB->GetBoundingBox();
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const SHAPE_POLY_SET& frontB = fpB->GetPolyCourtyard( F_CrtYd );
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const SHAPE_POLY_SET& frontB = fpB->GetPolyCourtyard( F_CrtYd );
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const SHAPE_POLY_SET& backB = fpB->GetPolyCourtyard( B_CrtYd );
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const SHAPE_POLY_SET& backB = fpB->GetPolyCourtyard( B_CrtYd );
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DRC_CONSTRAINT constraint;
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DRC_CONSTRAINT constraint;
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@ -237,6 +250,48 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances()
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reportViolation( drce, (wxPoint) pos );
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reportViolation( drce, (wxPoint) pos );
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}
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}
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}
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}
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auto testPadAgainstCourtyards =
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[&]( const PAD* pad, const FOOTPRINT* footprint )
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{
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int errorCode = 0;
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if( pad->GetAttribute() == PAD_ATTRIB::PTH )
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errorCode = DRCE_PTH_IN_COURTYARD;
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else if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
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errorCode = DRCE_NPTH_IN_COURTYARD;
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else
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return;
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if( m_drcEngine->IsErrorLimitExceeded( errorCode ) )
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return;
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const SHAPE_SEGMENT* hole = pad->GetEffectiveHoleShape();
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const SHAPE_POLY_SET& front = footprint->GetPolyCourtyard( F_CrtYd );
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const SHAPE_POLY_SET& back = footprint->GetPolyCourtyard( B_CrtYd );
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if( ( front.OutlineCount() > 0 && front.Collide( hole, 0 ) )
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|| ( back.OutlineCount() > 0 && back.Collide( hole, 0 ) ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( errorCode );
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drce->SetItems( pad, footprint );
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reportViolation( drce, pad->GetPosition() );
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}
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};
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if( ( frontA.OutlineCount() > 0 && frontA.BBoxFromCaches().Intersects( fpBBBox ) )
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|| ( backA.OutlineCount() > 0 && backA.BBoxFromCaches().Intersects( fpBBBox ) ) )
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{
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for( const PAD* padB : fpB->Pads() )
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testPadAgainstCourtyards( padB, fpA );
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}
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if( ( frontB.OutlineCount() > 0 && frontB.BBoxFromCaches().Intersects( fpABBox ) )
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|| ( backB.OutlineCount() > 0 && backB.BBoxFromCaches().Intersects( fpABBox ) ) )
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{
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for( const PAD* padA : fpA->Pads() )
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testPadAgainstCourtyards( padA, fpB );
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}
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}
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}
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}
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}
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@ -0,0 +1,215 @@
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(kicad_pcb (version 20210824) (generator pcbnew)
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(general
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(thickness 1.6)
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)
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(paper "A4")
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(layers
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(0 "F.Cu" signal)
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(31 "B.Cu" signal)
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(32 "B.Adhes" user "B.Adhesive")
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(33 "F.Adhes" user "F.Adhesive")
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(34 "B.Paste" user)
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(35 "F.Paste" user)
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(36 "B.SilkS" user "B.Silkscreen")
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(37 "F.SilkS" user "F.Silkscreen")
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(38 "B.Mask" user)
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(39 "F.Mask" user)
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(40 "Dwgs.User" user "User.Drawings")
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(41 "Cmts.User" user "User.Comments")
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(42 "Eco1.User" user "User.Eco1")
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(43 "Eco2.User" user "User.Eco2")
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(44 "Edge.Cuts" user)
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(45 "Margin" user)
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(46 "B.CrtYd" user "B.Courtyard")
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(47 "F.CrtYd" user "F.Courtyard")
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(48 "B.Fab" user)
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(49 "F.Fab" user)
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(50 "User.1" user)
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(51 "User.2" user)
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(52 "User.3" user)
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(53 "User.4" user)
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(54 "User.5" user)
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(55 "User.6" user)
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(56 "User.7" user)
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(57 "User.8" user)
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(58 "User.9" user)
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)
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(setup
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(stackup
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(layer "F.SilkS" (type "Top Silk Screen"))
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(layer "F.Paste" (type "Top Solder Paste"))
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(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
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(layer "F.Cu" (type "copper") (thickness 0.035))
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(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
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(layer "B.Cu" (type "copper") (thickness 0.035))
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(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
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(layer "B.Paste" (type "Bottom Solder Paste"))
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(layer "B.SilkS" (type "Bottom Silk Screen"))
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(copper_finish "None")
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(dielectric_constraints no)
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)
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(pad_to_mask_clearance 0)
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(pcbplotparams
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(layerselection 0x00010fc_ffffffff)
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(disableapertmacros false)
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(usegerberextensions false)
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(usegerberattributes true)
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(usegerberadvancedattributes true)
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(creategerberjobfile true)
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(svguseinch false)
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(svgprecision 6)
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(excludeedgelayer true)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15.000000)
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(dxfpolygonmode true)
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(dxfimperialunits true)
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(dxfusepcbnewfont true)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(sketchpadsonfab false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory "")
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)
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)
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(net 0 "")
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(net 1 "unconnected-(J1-Pad1)")
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(net 2 "unconnected-(J1-Pad2)")
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(net 3 "Net-(J1-Pad3)")
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(net 4 "unconnected-(J1-Pad4)")
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(net 5 "unconnected-(J1-Pad5)")
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(net 6 "Net-(J1-Pad6)")
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(net 7 "unconnected-(J1-Pad7)")
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(net 8 "unconnected-(J1-Pad8)")
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(footprint "Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical" (layer "F.Cu")
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(tedit 59FED5CC) (tstamp f942499e-6e89-458d-96f7-b17de56e7805)
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(at 133.87 100.395)
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(descr "Through hole straight pin header, 1x08, 2.54mm pitch, single row")
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(tags "Through hole pin header THT 1x08 2.54mm single row")
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(property "Sheetfile" "asdf_DRC_THThole_5.99.kicad_sch")
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(property "Sheetname" "")
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||||||
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(path "/10d9fe7c-1470-4087-b5e0-7fc4e0ea6dcc")
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||||||
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(attr through_hole)
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(fp_text reference "J1" (at 0 -2.33) (layer "F.SilkS")
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||||||
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(effects (font (size 1 1) (thickness 0.15)))
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||||||
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(tstamp abddb9f1-e8f1-45e1-9018-331fe9da67d7)
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)
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||||||
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(fp_text value "Conn_01x08" (at 0 20.11) (layer "F.Fab")
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||||||
|
(effects (font (size 1 1) (thickness 0.15)))
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||||||
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(tstamp f1da5067-9a8e-4918-b22b-6e92d8080b49)
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)
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||||||
|
(fp_text user "${REFERENCE}" (at 0 8.89 90) (layer "F.Fab")
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||||||
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(effects (font (size 1 1) (thickness 0.15)))
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||||||
|
(tstamp 988fbed7-2acf-4203-b243-e17951632c6f)
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)
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||||||
|
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer "F.SilkS") (width 0.12) (tstamp 308c4ce8-ac74-4b13-9dac-ba9f88ec9623))
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||||||
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(fp_line (start -1.33 1.27) (end -1.33 19.11) (layer "F.SilkS") (width 0.12) (tstamp 5385afbc-f099-466a-b564-bc19e404d27c))
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||||||
|
(fp_line (start 1.33 1.27) (end 1.33 19.11) (layer "F.SilkS") (width 0.12) (tstamp 6a514254-8ce8-4715-9582-619bad3ceaa1))
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||||||
|
(fp_line (start -1.33 19.11) (end 1.33 19.11) (layer "F.SilkS") (width 0.12) (tstamp b4ce60c4-bb1b-43df-adb0-f56112bcea07))
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||||||
|
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer "F.SilkS") (width 0.12) (tstamp dd34df30-1b0b-41e6-9b3a-9bcee81ce5b3))
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||||||
|
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer "F.SilkS") (width 0.12) (tstamp f07f7e83-06b1-454b-9ce1-69f925a12bb5))
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||||||
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(fp_line (start 1.8 19.55) (end 1.8 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp 01fc8f3d-08da-491d-bd47-02ca97a27197))
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||||||
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(fp_line (start -1.8 19.55) (end 1.8 19.55) (layer "F.CrtYd") (width 0.05) (tstamp 29035e40-5d75-423b-8cfd-bbe1f552a44e))
|
||||||
|
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp cfb9f145-2d5d-46aa-b6a1-4c4b224391b3))
|
||||||
|
(fp_line (start -1.8 -1.8) (end -1.8 19.55) (layer "F.CrtYd") (width 0.05) (tstamp dce14071-229c-4686-b95a-52b73a31b5bd))
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||||||
|
(fp_line (start 1.27 19.05) (end -1.27 19.05) (layer "F.Fab") (width 0.1) (tstamp 13e7305b-06d1-44bd-ac40-1cdc9036b511))
|
||||||
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(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer "F.Fab") (width 0.1) (tstamp 24a3216b-141c-41a1-b16d-8c24ac4e3961))
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||||||
|
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer "F.Fab") (width 0.1) (tstamp 681e4038-5284-466a-9c13-6ab67b25fc23))
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||||||
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(fp_line (start -1.27 19.05) (end -1.27 -0.635) (layer "F.Fab") (width 0.1) (tstamp 70cad101-1312-4d40-a56c-4fc77a8f6e91))
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||||||
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(fp_line (start 1.27 -1.27) (end 1.27 19.05) (layer "F.Fab") (width 0.1) (tstamp 7f7f3567-cd01-4a12-aab2-eaf6b6652bf4))
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||||||
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(pad "1" thru_hole rect locked (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||||
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(net 1 "unconnected-(J1-Pad1)") (pinfunction "Pin_1") (pintype "passive+no_connect") (tstamp 66e2a15f-475a-473d-911d-4cbf29bed935))
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||||||
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(pad "2" thru_hole oval locked (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||||
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(net 2 "unconnected-(J1-Pad2)") (pinfunction "Pin_2") (pintype "passive+no_connect") (tstamp f00656a3-c63d-4945-950c-98b6eb364dd3))
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||||||
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(pad "3" thru_hole oval locked (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||||
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(net 3 "Net-(J1-Pad3)") (pinfunction "Pin_3") (pintype "passive") (tstamp 335bf42e-0bd8-4d93-811e-88428674ac40))
|
||||||
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(pad "4" thru_hole oval locked (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||||
|
(net 4 "unconnected-(J1-Pad4)") (pinfunction "Pin_4") (pintype "passive+no_connect") (tstamp a86070f5-e288-414d-8ab1-f3c0dd3a7e97))
|
||||||
|
(pad "5" thru_hole oval locked (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||||
|
(net 5 "unconnected-(J1-Pad5)") (pinfunction "Pin_5") (pintype "passive+no_connect") (tstamp 691c2f09-0a78-40a0-b609-fcb3aca7d156))
|
||||||
|
(pad "6" thru_hole oval locked (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||||
|
(net 6 "Net-(J1-Pad6)") (pinfunction "Pin_6") (pintype "passive") (tstamp 48025f67-e6da-4fe1-9e0b-54d232312e9f))
|
||||||
|
(pad "7" thru_hole oval locked (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||||
|
(net 7 "unconnected-(J1-Pad7)") (pinfunction "Pin_7") (pintype "passive+no_connect") (tstamp 500d306c-d007-4238-9d4a-6cc36d39098e))
|
||||||
|
(pad "8" thru_hole oval locked (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||||
|
(net 8 "unconnected-(J1-Pad8)") (pinfunction "Pin_8") (pintype "passive+no_connect") (tstamp 2393e835-0eb7-46f7-9a1c-f3b1eb2c9dc7))
|
||||||
|
(model "${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x08_P2.54mm_Vertical.wrl"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "Resistor_SMD:R_4020_10251Metric" (layer "B.Cu")
|
||||||
|
(tedit 5F68FEEE) (tstamp ba0edce2-e1c7-4597-861d-911cbd56157e)
|
||||||
|
(at 133.41 106.76 180)
|
||||||
|
(descr "Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator")
|
||||||
|
(tags "resistor")
|
||||||
|
(property "Sheetfile" "asdf_DRC_THThole_5.99.kicad_sch")
|
||||||
|
(property "Sheetname" "")
|
||||||
|
(path "/48f2fbd7-87d9-45c4-ae2d-cb0a73f9651d")
|
||||||
|
(attr smd)
|
||||||
|
(fp_text reference "R1" (at 7.5 4.49) (layer "B.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||||
|
(tstamp b2713db1-b75e-46b4-9d27-1ef8d6894927)
|
||||||
|
)
|
||||||
|
(fp_text value "2k2" (at 0 -3.6) (layer "B.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||||
|
(tstamp d3438eb8-ebcc-47df-b35e-7c547b35ddd0)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 0 0) (layer "B.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||||
|
(tstamp b486d3fd-365b-4c78-8eb4-67bf0a49d27c)
|
||||||
|
)
|
||||||
|
(fp_line (start -3.886252 -2.66) (end 3.886252 -2.66) (layer "B.SilkS") (width 0.12) (tstamp 2b8e5ba7-99af-4594-b33b-abb700a73b44))
|
||||||
|
(fp_line (start -3.886252 2.66) (end 3.886252 2.66) (layer "B.SilkS") (width 0.12) (tstamp 7e2abf26-3709-4f3f-993d-c982036b3ef5))
|
||||||
|
(fp_line (start -5.8 2.9) (end 5.8 2.9) (layer "B.CrtYd") (width 0.05) (tstamp 1e0317f1-6e91-4e2f-bed7-20909212f91b))
|
||||||
|
(fp_line (start 5.8 -2.9) (end -5.8 -2.9) (layer "B.CrtYd") (width 0.05) (tstamp 4a2873de-68ea-4073-9a54-5f8bdd3d427d))
|
||||||
|
(fp_line (start 5.8 2.9) (end 5.8 -2.9) (layer "B.CrtYd") (width 0.05) (tstamp 4cb2cc63-3904-43c1-9f76-a3a94c000740))
|
||||||
|
(fp_line (start -5.8 -2.9) (end -5.8 2.9) (layer "B.CrtYd") (width 0.05) (tstamp aa2aae78-3106-4115-bb72-f2b5dfeed4e5))
|
||||||
|
(fp_line (start 5.1 -2.55) (end -5.1 -2.55) (layer "B.Fab") (width 0.1) (tstamp 097174c7-9aac-4118-9d84-1f0f0429d6c8))
|
||||||
|
(fp_line (start -5.1 2.55) (end 5.1 2.55) (layer "B.Fab") (width 0.1) (tstamp 13be7c0d-72ea-430b-b983-a3eaa6574a4f))
|
||||||
|
(fp_line (start -5.1 -2.55) (end -5.1 2.55) (layer "B.Fab") (width 0.1) (tstamp 6dd20bc6-59b2-4bdf-ba8c-aaf47741f3fe))
|
||||||
|
(fp_line (start 5.1 2.55) (end 5.1 -2.55) (layer "B.Fab") (width 0.1) (tstamp b12dc0c3-d7c3-45dd-a897-1a26cc990510))
|
||||||
|
(pad "1" smd roundrect locked (at -4.8125 0 180) (size 1.475 5.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.169492)
|
||||||
|
(net 3 "Net-(J1-Pad3)") (pintype "passive") (tstamp 3fd16f59-8444-4dd4-9b56-d1b966f0f5ac))
|
||||||
|
(pad "2" smd roundrect locked (at 4.8125 0 180) (size 1.475 5.3) (layers "B.Cu" "B.Paste" "B.Mask") (roundrect_rratio 0.169492)
|
||||||
|
(net 6 "Net-(J1-Pad6)") (pintype "passive") (tstamp 2b13bf58-f783-450d-a6d8-a330c40a1a11))
|
||||||
|
(model "${KISYS3DMOD}/Resistor_SMD.3dshapes/R_4020_10251Metric.wrl"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(gr_line (start 115 95) (end 150 95) (layer "Edge.Cuts") (width 0.1) (tstamp 508789b7-8160-4edf-97b2-2f94d3dc3ecc))
|
||||||
|
(gr_line (start 150 125) (end 115 125) (layer "Edge.Cuts") (width 0.1) (tstamp 62f107c4-9268-467f-a52c-18597dd50b2b))
|
||||||
|
(gr_line (start 115 125) (end 115 95) (layer "Edge.Cuts") (width 0.1) (tstamp bdc07e5d-1ae1-4436-a65d-f3c282bd5e38))
|
||||||
|
(gr_line (start 150 95) (end 150 125) (layer "Edge.Cuts") (width 0.1) (tstamp cb3a7820-b0f4-4754-ad1c-112b2bb9728c))
|
||||||
|
|
||||||
|
(segment (start 135.285 105.475) (end 133.87 105.475) (width 0.25) (layer "B.Cu") (net 3) (tstamp 07e8d662-ffd7-445f-881c-d9612b64d24a))
|
||||||
|
(segment (start 136.57 106.76) (end 135.285 105.475) (width 0.25) (layer "B.Cu") (net 3) (tstamp 08a34781-a86b-44e8-ad5f-e50dc2b94e76))
|
||||||
|
(segment (start 138.2225 106.76) (end 136.57 106.76) (width 0.25) (layer "B.Cu") (net 3) (tstamp 6551195f-0c71-4858-abb3-ff54e00c83e0))
|
||||||
|
(segment (start 130.65 111.93) (end 131.815 113.095) (width 0.25) (layer "B.Cu") (net 6) (tstamp 3d7ce15c-bca4-4619-b22b-d9410c853f16))
|
||||||
|
(segment (start 131.815 113.095) (end 133.87 113.095) (width 0.25) (layer "B.Cu") (net 6) (tstamp c165a1d4-e530-4c0c-bd38-764ec374b425))
|
||||||
|
(segment (start 128.5975 106.76) (end 129.85 106.76) (width 0.25) (layer "B.Cu") (net 6) (tstamp d07b7106-dcb4-4cbb-bf1d-f732f880407f))
|
||||||
|
(segment (start 129.85 106.76) (end 130.65 107.56) (width 0.25) (layer "B.Cu") (net 6) (tstamp e38e2372-182d-4ab1-9a7c-47fc7e2d8f14))
|
||||||
|
(segment (start 130.65 107.56) (end 130.65 111.93) (width 0.25) (layer "B.Cu") (net 6) (tstamp e5037c3d-a2d4-4183-8ba8-ef4d22780edb))
|
||||||
|
|
||||||
|
)
|
||||||
|
|
@ -0,0 +1,434 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.09999999999999999,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.15,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.762,
|
||||||
|
"height": 1.524,
|
||||||
|
"width": 1.524
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.15,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.508
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "error",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "error",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.0,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"solder_mask_clearance": 0.0,
|
||||||
|
"solder_mask_min_width": 0.0,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.0
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.0,
|
||||||
|
"drill": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"erc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_entry_needed": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_reference": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"extra_units": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unannotated": "error",
|
||||||
|
"unit_value_mismatch": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "asdf_DRC_THThole_5.99.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"annotate_start_num": 0,
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_own_page": false,
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"label_size_ratio": 0.375,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.15
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"ngspice": {
|
||||||
|
"fix_include_paths": true,
|
||||||
|
"fix_passive_vals": false,
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"model_mode": 0,
|
||||||
|
"workbook_filename": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"f1329f92-898b-48fb-8d8c-becaafb4793f",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
|
|
@ -111,7 +111,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR
|
||||||
{ "issue7241", 1 },
|
{ "issue7241", 1 },
|
||||||
{ "issue7267", 4 },
|
{ "issue7267", 4 },
|
||||||
{ "issue7325", 2 },
|
{ "issue7325", 2 },
|
||||||
{ "issue8003", 2 } };
|
{ "issue8003", 2 },
|
||||||
|
{ "issue9081", 2 } };
|
||||||
|
|
||||||
for( const std::pair<wxString, int>& entry : tests )
|
for( const std::pair<wxString, int>& entry : tests )
|
||||||
{
|
{
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue