Add diode model to rectifier demo (ngspice-32 fix)
Patch by Holger Vogt Fixes https://gitlab.com/kicad/code/kicad/issues/4453
This commit is contained in:
Johannes Maibaum
parent
42cd6ca4ca
commit
a58d0f8a67
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@ -0,0 +1,2 @@
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*generic diode model
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.model 1N4148 D
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@ -1,101 +1,101 @@
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# C
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#
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DEF C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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C?
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C_????_*
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C_????
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SMD*_c
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Capacitor*
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Capacitors_ThroughHole:C_Radial_D10_L13_P5
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Capacitors_SMD:C_0805
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Capacitors_SMD:C_1206
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$ENDFPLIST
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 40 40 1 1 P
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X ~ 2 0 -150 110 U 40 40 1 1 P
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ENDDRAW
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ENDDEF
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#
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# D
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#
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DEF D D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "D" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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Diode_*
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D-Pak_TO252AA
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*SingleDiode
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*_Diode_*
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*SingleDiode*
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$ENDFPLIST
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DRAW
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P 2 0 1 6 -50 50 -50 -50 N
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P 3 0 1 0 50 50 -50 0 50 -50 F
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GND
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#
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DEF GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -150 50 H I C CNN
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F1 "GND" 0 -123 30 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 20 30 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# R
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#
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DEF R R 0 0 N Y 1 F N
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F0 "R" 80 0 50 V V C CNN
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F1 "R" 0 0 50 V V C CNN
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F2 "" -70 0 50 V V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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R_*
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Resistor_*
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$ENDFPLIST
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DRAW
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S -40 -100 40 100 0 1 10 N
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# VSOURCE
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#
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DEF ~VSOURCE V 0 40 Y Y 1 F N
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F0 "V" 200 200 50 H V C CNN
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F1 "VSOURCE" 250 100 50 H I C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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F4 "Value" 0 0 60 H I C CNN "Fieldname"
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F5 "V" 0 0 60 H I C CNN "Spice_Primitive"
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F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence"
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DRAW
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C 0 0 100 0 1 0 N
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P 2 0 1 0 0 -75 0 75 N
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P 4 0 1 0 0 75 -25 25 25 25 0 75 F
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X ~ 1 0 200 100 D 50 50 1 1 I
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X ~ 2 0 -200 100 U 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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#End Library
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# rectifier_schlib_C
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#
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DEF rectifier_schlib_C C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "rectifier_schlib_C" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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C?
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C_????_*
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C_????
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SMD*_c
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Capacitor*
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Capacitors_ThroughHole:C_Radial_D10_L13_P5
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Capacitors_SMD:C_0805
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Capacitors_SMD:C_1206
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$ENDFPLIST
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DRAW
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P 2 0 1 20 -80 -30 80 -30 N
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P 2 0 1 20 -80 30 80 30 N
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X ~ 1 0 150 110 D 40 40 1 1 P
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X ~ 2 0 -150 110 U 40 40 1 1 P
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ENDDRAW
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ENDDEF
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#
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# rectifier_schlib_D
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#
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DEF rectifier_schlib_D D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "rectifier_schlib_D" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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Diode_*
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D-Pak_TO252AA
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*SingleDiode
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*_Diode_*
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*SingleDiode*
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$ENDFPLIST
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DRAW
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P 2 0 1 6 -50 50 -50 -50 N
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P 3 0 1 0 50 50 -50 0 50 -50 F
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# rectifier_schlib_GND
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#
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DEF rectifier_schlib_GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -150 50 H I C CNN
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F1 "rectifier_schlib_GND" 0 -123 30 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 20 30 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# rectifier_schlib_R
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#
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DEF rectifier_schlib_R R 0 0 N Y 1 F N
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F0 "R" 80 0 50 V V C CNN
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F1 "rectifier_schlib_R" 0 0 50 V V C CNN
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F2 "" -70 0 50 V V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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R_*
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Resistor_*
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$ENDFPLIST
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DRAW
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S -40 -100 40 100 0 1 10 N
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X ~ 1 0 150 50 D 50 50 1 1 P
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X ~ 2 0 -150 50 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# rectifier_schlib_VSOURCE
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#
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DEF rectifier_schlib_VSOURCE V 0 40 Y Y 1 F N
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F0 "V" 200 200 50 H V C CNN
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F1 "rectifier_schlib_VSOURCE" 250 100 50 H I C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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F4 "Value" 0 0 60 H I C CNN "Fieldname"
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F5 "V" 0 0 60 H I C CNN "Spice_Primitive"
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F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence"
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DRAW
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C 0 0 100 0 1 0 N
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P 2 0 1 0 0 -75 0 75 N
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P 4 0 1 0 0 75 -25 25 25 25 0 75 F
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X ~ 1 0 200 100 D 50 50 1 1 I
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X ~ 2 0 -200 100 U 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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#End Library
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@ -1,129 +1,137 @@
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EESchema Schematic File Version 4
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LIBS:rectifier-cache
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EELAYER 26 0
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||||
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||||
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||||
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F 5 "C" H 5400 4000 60 0001 C CNN "Spice_Primitive"
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||||
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F 4 "Value" H 5750 4000 60 0001 C CNN "Fieldname"
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F 5 "1 2" H 5750 4000 60 0001 C CNN "SpiceMapping"
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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5400 4300 5400 4150
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Wire Wire Line
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5750 4300 5750 4150
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Connection ~ 5400 4300
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Wire Wire Line
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4800 3700 4950 3700
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Wire Wire Line
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4400 3850 4400 3700
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Wire Wire Line
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Text Notes 4300 5000 0 60 ~ 0
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*.ac dec 10 1 1Meg\n
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||||
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Comp ""
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||||
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||||
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||||
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||||
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Wire Wire Line
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||||
Wire Wire Line
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||||
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5750 3700 5750 3850
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Wire Wire Line
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5400 3850 5400 3700
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Wire Wire Line
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5400 4300 5400 4150
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Wire Wire Line
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5750 4300 5750 4150
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||||
Wire Wire Line
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4800 3700 4950 3700
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Wire Wire Line
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||||
4400 3850 4400 3700
|
||||
Wire Wire Line
|
||||
4400 3700 4500 3700
|
||||
Text Label 4400 3700 2 60 ~ 0
|
||||
signal_in
|
||||
Text Label 5750 3700 0 60 ~ 0
|
||||
rect_out
|
||||
Text Notes 4300 5000 0 60 ~ 0
|
||||
*.ac dec 10 1 1Meg\n
|
||||
Wire Wire Line
|
||||
4400 4300 4400 4250
|
||||
Wire Wire Line
|
||||
5400 3700 5750 3700
|
||||
Wire Wire Line
|
||||
5400 4300 5750 4300
|
||||
$EndSCHEMATC
|
||||
|
|
|
|||
Loading…
Reference in New Issue