Add diode model to rectifier demo (ngspice-32 fix)
Patch by Holger Vogt Fixes https://gitlab.com/kicad/code/kicad/issues/4453
This commit is contained in:
parent
42cd6ca4ca
commit
a58d0f8a67
|
@ -0,0 +1,2 @@
|
|||
*generic diode model
|
||||
.model 1N4148 D
|
|
@ -1,11 +1,11 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# C
|
||||
# rectifier_schlib_C
|
||||
#
|
||||
DEF C C 0 10 N Y 1 F N
|
||||
DEF rectifier_schlib_C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "C" 25 -100 50 H V L CNN
|
||||
F1 "rectifier_schlib_C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
$FPLIST
|
||||
|
@ -26,11 +26,11 @@ X ~ 2 0 -150 110 U 40 40 1 1 P
|
|||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# D
|
||||
# rectifier_schlib_D
|
||||
#
|
||||
DEF D D 0 40 N N 1 F N
|
||||
DEF rectifier_schlib_D D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "D" 0 -100 50 H V C CNN
|
||||
F1 "rectifier_schlib_D" 0 -100 50 H V C CNN
|
||||
F2 "" 0 0 50 H V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
$FPLIST
|
||||
|
@ -48,11 +48,11 @@ X A 2 150 0 100 L 50 50 1 1 P
|
|||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GND
|
||||
# rectifier_schlib_GND
|
||||
#
|
||||
DEF GND #PWR 0 0 Y Y 1 F P
|
||||
DEF rectifier_schlib_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "GND" 0 -123 30 H V C CNN
|
||||
F1 "rectifier_schlib_GND" 0 -123 30 H V C CNN
|
||||
F2 "" 0 0 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
|
@ -61,11 +61,11 @@ X GND 1 0 0 0 D 20 30 1 1 W N
|
|||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# R
|
||||
# rectifier_schlib_R
|
||||
#
|
||||
DEF R R 0 0 N Y 1 F N
|
||||
DEF rectifier_schlib_R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "R" 0 0 50 V V C CNN
|
||||
F1 "rectifier_schlib_R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
$FPLIST
|
||||
|
@ -79,11 +79,11 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
|
|||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# VSOURCE
|
||||
# rectifier_schlib_VSOURCE
|
||||
#
|
||||
DEF ~VSOURCE V 0 40 Y Y 1 F N
|
||||
DEF rectifier_schlib_VSOURCE V 0 40 Y Y 1 F N
|
||||
F0 "V" 200 200 50 H V C CNN
|
||||
F1 "VSOURCE" 250 100 50 H I C CNN
|
||||
F1 "rectifier_schlib_VSOURCE" 250 100 50 H I C CNN
|
||||
F2 "" 0 0 50 H V C CNN
|
||||
F3 "" 0 0 50 H V C CNN
|
||||
F4 "Value" 0 0 60 H I C CNN "Fieldname"
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:rectifier-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
@ -64,6 +63,9 @@ F 3 "" H 5100 3700 50 0000 C CNN
|
|||
F 4 "Value" H 5100 3700 60 0001 C CNN "Fieldname"
|
||||
F 5 "D" H 5100 3700 60 0001 C CNN "Spice_Primitive"
|
||||
F 6 "2 1" H 5100 3700 60 0001 C CNN "Spice_Node_Sequence"
|
||||
F 7 "1N4148" H 5100 3700 50 0001 C CNN "Spice_Model"
|
||||
F 8 "Y" H 5100 3700 50 0001 C CNN "Spice_Netlist_Enabled"
|
||||
F 9 "diode.mod" H 5100 3700 50 0001 C CNN "Spice_Lib_File"
|
||||
1 5100 3700
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
|
@ -98,12 +100,12 @@ $EndComp
|
|||
Text Notes 4300 4900 0 60 ~ 0
|
||||
.tran 1u 10m\n
|
||||
Wire Wire Line
|
||||
4400 4350 4400 4250
|
||||
4400 4350 4400 4300
|
||||
Wire Wire Line
|
||||
4400 4300 5750 4300
|
||||
4400 4300 5400 4300
|
||||
Connection ~ 4400 4300
|
||||
Wire Wire Line
|
||||
5250 3700 5750 3700
|
||||
5250 3700 5400 3700
|
||||
Wire Wire Line
|
||||
5750 3700 5750 3850
|
||||
Wire Wire Line
|
||||
|
@ -126,4 +128,10 @@ Text Label 5750 3700 0 60 ~ 0
|
|||
rect_out
|
||||
Text Notes 4300 5000 0 60 ~ 0
|
||||
*.ac dec 10 1 1Meg\n
|
||||
Wire Wire Line
|
||||
4400 4300 4400 4250
|
||||
Wire Wire Line
|
||||
5400 3700 5750 3700
|
||||
Wire Wire Line
|
||||
5400 4300 5750 4300
|
||||
$EndSCHEMATC
|
||||
|
|
Loading…
Reference in New Issue