haskal
/
kicad
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Better DRC checking when placing vias. 

(cherry picked from commit 369f53bb19)
This commit is contained in:
Jeff Young 2022-02-24 21:01:03 +00:00
parent 4b0177c8fe
commit b00f855c26
1 changed files with 36 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
pcbnew/tools/drawing_tool.cpp
View File

@ -2399,13 +2399,31 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
if( DRC_ENGINE::IsNetTie( aOther ) ) if( DRC_ENGINE::IsNetTie( aOther ) )
return false; return false;
DRC_CONSTRAINT constraint;
if( ( aOther->Type() == PCB_ZONE_T || aOther->Type() == PCB_FP_ZONE_T )
&& static_cast<ZONE*>( aOther )->GetIsRuleArea() )
{
ZONE* zone = static_cast<ZONE*>( aOther );
if( zone->GetDoNotAllowVias() )
return true;
constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, aVia, nullptr,
UNDEFINED_LAYER );
if( constraint.m_DisallowFlags && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
return true;
return false;
}
BOARD_CONNECTED_ITEM* cItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( aOther ); BOARD_CONNECTED_ITEM* cItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( aOther );
if( cItem && cItem->GetNetCode() == aVia->GetNetCode() ) if( cItem && cItem->GetNetCode() == aVia->GetNetCode() )
return false; return false;
DRC_CONSTRAINT constraint; int clearance;
int clearance;
for( PCB_LAYER_ID layer : aOther->GetLayerSet().Seq() ) for( PCB_LAYER_ID layer : aOther->GetLayerSet().Seq() )
{ {
@ -2476,17 +2494,24 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
if( !item ) if( !item )
continue; continue;
if( item->Type() == PCB_ZONE_T || item->Type() == PCB_FP_ZONE_T ) if( ( item->Type() == PCB_ZONE_T || item->Type() == PCB_FP_ZONE_T )
&& !static_cast<ZONE*>( item )->GetIsRuleArea() )
{
continue; // stitching vias bind to zones, so ignore them continue; // stitching vias bind to zones, so ignore them
}
if( item->Type() == PCB_FOOTPRINT_T || item->Type() == PCB_GROUP_T ) else if( item->Type() == PCB_FOOTPRINT_T || item->Type() == PCB_GROUP_T )
{
continue; // check against children, but not against footprint itself continue; // check against children, but not against footprint itself
}
if( item->Type() == PCB_FP_TEXT_T && !static_cast<FP_TEXT*>( item )->IsVisible() ) else if( item->Type() == PCB_FP_TEXT_T
&& !static_cast<FP_TEXT*>( item )->IsVisible() )
{
continue; // ignore hidden items continue; // ignore hidden items
}
if( checkedItems.count( item ) ) else if( checkedItems.count( item ) )
continue; {
continue; // already checked
}
if( hasDRCViolation( aVia, item ) ) if( hasDRCViolation( aVia, item ) )
return true; return true;
@ -2534,7 +2559,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
std::sort( foundZones.begin(), foundZones.end(), std::sort( foundZones.begin(), foundZones.end(),
[] ( const ZONE* a, const ZONE* b ) [] ( const ZONE* a, const ZONE* b )
{ {
return a->GetLayer() < b->GetLayer(); return a->GetFirstLayer() < b->GetFirstLayer();
} ); } );
// first take the net of the active layer // first take the net of the active layer