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Fix order of initializing tools when loading board 

Also add a few safeguards against invalid situations

Fixes https://gitlab.com/kicad/code/kicad/-/issues/5801
This commit is contained in:
Jon Evans 2020-09-26 14:45:16 -04:00
parent 56ca842ec4
commit b6e4b7bf7d
4 changed files with 48 additions and 45 deletions
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56
pcbnew/class_board.cpp
View File

@ -1335,40 +1335,40 @@ void BOARD::SynchronizeProperties()
void BOARD::SynchronizeNetsAndNetClasses() void BOARD::SynchronizeNetsAndNetClasses()
{ {
if( m_project ) if( !m_project )
return;
NET_SETTINGS* netSettings = m_project->GetProjectFile().m_NetSettings.get();
NETCLASSES& netClasses = netSettings->m_NetClasses;
NETCLASSPTR defaultNetClass = netClasses.GetDefault();
for( NETINFO_ITEM* net : m_NetInfo )
{ {
NET_SETTINGS* netSettings = m_project->GetProjectFile().m_NetSettings.get(); const wxString& netname = net->GetNetname();
NETCLASSES& netClasses = netSettings->m_NetClasses;
NETCLASSPTR defaultNetClass = netClasses.GetDefault();
for( NETINFO_ITEM* net : m_NetInfo ) if( netSettings->m_NetClassAssignments.count( netname ) )
{ {
const wxString& netname = net->GetNetname(); const wxString& classname = netSettings->m_NetClassAssignments[ netname ];
net->SetClass( netClasses.Find( classname ) );
if( netSettings->m_NetClassAssignments.count( netname ) ) }
{ else
const wxString& classname = netSettings->m_NetClassAssignments[ netname ]; {
net->SetClass( netClasses.Find( classname ) ); net->SetClass( defaultNetClass );
}
else
{
net->SetClass( defaultNetClass );
}
} }
BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
// Set initial values for custom track width & via size to match the default
// netclass settings
bds.UseCustomTrackViaSize( false );
bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() );
bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() );
bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() );
} }
BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
// Set initial values for custom track width & via size to match the default
// netclass settings
bds.UseCustomTrackViaSize( false );
bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() );
bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() );
bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() );
InvokeListeners( &BOARD_LISTENER::OnBoardNetSettingsChanged, *this ); InvokeListeners( &BOARD_LISTENER::OnBoardNetSettingsChanged, *this );
} }

31
pcbnew/pcb_base_edit_frame.cpp
View File

@ -142,22 +142,6 @@ void PCB_BASE_EDIT_FRAME::SetBoard( BOARD* aBoard )
PCB_BASE_FRAME::SetBoard( aBoard ); PCB_BASE_FRAME::SetBoard( aBoard );
if( new_board )
{
BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings();
bds.m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard, &bds );
try
{
bds.m_DRCEngine->InitEngine( GetDesignRulesPath() );
}
catch( PARSE_ERROR& pe )
{
// TODO: We could redirect to Board Setup here and report the error. Or we could
// wait till they run DRC or do an Inspect Clearance. Not sure which is better....
}
}
GetCanvas()->GetGAL()->SetGridOrigin( VECTOR2D( aBoard->GetDesignSettings().m_GridOrigin ) ); GetCanvas()->GetGAL()->SetGridOrigin( VECTOR2D( aBoard->GetDesignSettings().m_GridOrigin ) );
// update the tool manager with the new board and its view. // update the tool manager with the new board and its view.
@ -170,7 +154,22 @@ void PCB_BASE_EDIT_FRAME::SetBoard( BOARD* aBoard )
GetCanvas()->GetViewControls(), config(), this ); GetCanvas()->GetViewControls(), config(), this );
if( new_board ) if( new_board )
{
m_toolManager->ResetTools( TOOL_BASE::MODEL_RELOAD ); m_toolManager->ResetTools( TOOL_BASE::MODEL_RELOAD );
BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings();
bds.m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard, &bds );
try
{
bds.m_DRCEngine->InitEngine( GetDesignRulesPath() );
}
catch( PARSE_ERROR& pe )
{
// TODO: We could redirect to Board Setup here and report the error. Or we could
// wait till they run DRC or do an Inspect Clearance. Not sure which is better....
}
}
} }
} }

2
pcbnew/tools/drc_tool.cpp
View File

@ -64,7 +64,7 @@ void DRC_TOOL::Reset( RESET_REASON aReason )
m_drcEngine = m_pcb->GetDesignSettings().m_DRCEngine; m_drcEngine = m_pcb->GetDesignSettings().m_DRCEngine;
} }
if( aReason == MODEL_RELOAD ) if( aReason == MODEL_RELOAD && m_pcb->GetProject() )
{ {
try try
{ {

4
pcbnew/widgets/appearance_controls.cpp
View File

@ -1882,6 +1882,10 @@ void APPEARANCE_CONTROLS::rebuildNets()
COLOR_SETTINGS* theme = m_frame->GetColorSettings(); COLOR_SETTINGS* theme = m_frame->GetColorSettings();
COLOR4D bgColor = theme->GetColor( LAYER_PCB_BACKGROUND ); COLOR4D bgColor = theme->GetColor( LAYER_PCB_BACKGROUND );
// If the board isn't fully loaded, we can't yet rebuild
if( !board->GetProject() )
return;
KIGFX::PCB_RENDER_SETTINGS* rs = static_cast<KIGFX::PCB_RENDER_SETTINGS*>( KIGFX::PCB_RENDER_SETTINGS* rs = static_cast<KIGFX::PCB_RENDER_SETTINGS*>(
m_frame->GetCanvas()->GetView()->GetPainter()->GetSettings() ); m_frame->GetCanvas()->GetView()->GetPainter()->GetSettings() );