Translated using Weblate (Chinese (Simplified))
Currently translated at 100.0% (7191 of 7191 strings) Translation: KiCad EDA/master source Translate-URL: https://hosted.weblate.org/projects/kicad/master-source/zh_Hans/
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taotieren
Hosted Weblate
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@ -16,7 +16,7 @@ msgstr ""
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"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
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"Report-Msgid-Bugs-To: \n"
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"POT-Creation-Date: 2021-11-16 10:40-0800\n"
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"PO-Revision-Date: 2021-11-26 03:21+0000\n"
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"PO-Revision-Date: 2021-11-26 21:26+0000\n"
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"Last-Translator: taotieren <admin@taotieren.com>\n"
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"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
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"kicad/master-source/zh_Hans/>\n"
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@ -20159,7 +20159,6 @@ msgid "Not worth using"
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msgstr "不值得使用"
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#: pcb_calculator/eserie_help.h:2
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#, fuzzy
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msgid ""
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"E-series are defined in IEC 60063.\n"
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"\n"
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@ -20187,22 +20186,23 @@ msgid ""
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"\tR1 | R2 |...| Rn\tresistors in parallel\n"
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"\tR1 + (R2|R3)...\t\tany combination of the above\n"
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msgstr ""
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"在 IEC (国际电工委员会) 60063 中定义的 E 系列是一种被\n"
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"广泛接受的电子元器件首选编号系统。可用值在对数刻度\n"
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"上近似等距。\n"
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"E 系列是在 IEC (国际电工委员会) 60063 中定义的。\n"
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"\n"
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"\tE12: 1.0 1.2 1.5 1.8 2.2 2.7 3.3 3.9 4.7 5.6 6.8 8.2\n"
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"\tE6: 1.0 - 1.5 - 2.2 - 3.3 - 4.7 - 6.8 -\n"
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"\tE3: 1.0 - - - 2.2 - - - 4.7 - - -\n"
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"\tE1: 1.0 - - - - - - - - - - -\n"
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"可用值在对数刻度上近似等距。\n"
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"\n"
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"此计算器查找标准 E 系列元件的组合来\n"
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"创建任意值。您可以输入所需的电阻，范围从0.0025 到 4000 kΩ。\n"
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"给出的解决方案使用多达 4 个元件。\n"
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"\tE24(5%): 1.0 1.1 1.2 1.3 1.5 1.6 1.8 2.0 2.2 2.4 2.7 3.0 3.3 3.6 3.9 4.3 "
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"4.7 5.1 5.6 6.2 6.8 7.5 8.2 9.1\n"
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"\tE12(10%): 1.0 1.2 1.5 1.8 2.2 2.7 3.3 3.9 4.7 5.6 6.8 8.2\n"
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"\tE6(20%): 1.0 - 1.5 - 2.2 - 3.3 - 4.7 - 6.8 -\n"
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"\tE3(50%): 1.0 - - - 2.2 - - - 4.7 - - -\n"
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"\tE1 : 1.0 - - - - - - - - - - -\n"
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"\n"
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"默认情况下，请求值总是被排除在解决方案集之外。也可以指定将最多两个额外的值排"
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"除在解决方案之外，前提是\n"
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"这些组件值不可用。\n"
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"- 这个计算器可以查找标准 E 系列 (在 10 Ω 和 1 MΩ 之间) 的组合以创建任意的数值。\n"
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"- 您可以输入0.0025 到 4000 kΩ之间所需的电阻。\n"
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"- 给出了最多使用 4 个元件的解决方案。\n"
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"\n"
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"所要求的值总是被排除在解决方案集之外。<br>\n"
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"如果出现元件可用性问题，最多可以排除两个额外的值。\n"
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"\n"
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"解决方案依照下列格式提供：\n"
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"\n"
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@ -20265,7 +20265,6 @@ msgstr ""
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"是否要退出并放弃变更？"
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#: pcb_calculator/tracks_width_versus_current_formula.h:2
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#, fuzzy
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msgid ""
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"If you specify the maximum current, then the trace widths will be calculated "
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"to suit.\n"
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@ -20292,21 +20291,21 @@ msgid ""
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msgstr ""
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"如果你指定最大电流，则会计算相应的布线宽度。\n"
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"\n"
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"如果你指定其中一个布线宽度，则将计算它可以处理的最大电流。然后将计算另外的同"
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"样处理此电流的布线宽度。\n"
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"如果你指定其中一个布线宽度，则将计算它可以处理的最大电流。然后将计算另外的同样处理此电流的布线宽度。\n"
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"\n"
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"控制值以粗体显示。\n"
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"\n"
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"计算适用于最大 35A（外部）或 17.5A（内部）的电流、最多 100 摄氏度的气温上升和"
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"最多 400mil（10mm）的宽度。\n"
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"计算适用于最大 35A（外部）或 17.5A（内部）的电流、高达 100 °C的温升和最多 400mil（10mm）的宽度。\n"
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"\n"
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"来自 IPC 2221的该公式，为\n"
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"<center>__I = K * dT<sup>0.44</sup> * (W*H)<sup>0.725</sup>__</center>\n"
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"<center>___I = K ⋅ ΔT<sup>0.44</sup> ⋅ (W ⋅ H)<sup>0."
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"725</sup>___</center> \n"
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"其中： \n"
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"__I__ = 最大电流（单位：安培） \n"
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"__dt__ = 环境温度温升（单位：摄氏度） \n"
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"__W，H__ = 布线的宽度和厚度 （单位：密耳）\n"
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"__K__ = 0.024 用于内部布线，0.048 用于外部布线\n"
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"__I__ = 最大电流（单位：A 安培） \n"
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"__ΔT__ = 环境温度温升（单位：°C 摄氏度） \n"
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"__W__ = 布线的宽度 （单位：mil 密耳）\n"
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"__H__ = 布线的厚度 （单位：mil 密耳）\n"
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"__K__ = 0.024 用于内部布线，0.048 用于外部布线 \n"
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#: pcb_calculator/transline_dlg_funct.cpp:140
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msgid "Dielectric Loss Factor"
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@ -22869,7 +22868,7 @@ msgstr "不运行"
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#: pcbnew/dialogs/dialog_drc_base.cpp:27
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msgid "Refill all zones before performing DRC"
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msgstr "在执行 DRC 之前重新填充所有覆铜"
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msgstr "在执行 DRC 之前重新填充所有敷铜"
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#: pcbnew/dialogs/dialog_drc_base.cpp:30
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msgid "Report all errors for each track"
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@ -23388,7 +23387,7 @@ msgstr "包含过孔 (&V)"
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#: pcbnew/dialogs/dialog_filter_selection_base.cpp:51
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msgid "Include &zones"
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msgstr "包含覆铜 (&Z)"
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msgstr "包含敷铜 (&Z)"
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#: pcbnew/dialogs/dialog_filter_selection_base.h:59
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msgid "Filter Selected Items"
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@ -23745,17 +23744,17 @@ msgstr "注意：添加焊膏间隙（绝对和相对）以确定最终间隙。
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:300
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:703
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msgid "Connection to Copper Zones"
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msgstr "连接到覆铜区"
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msgstr "连接到敷铜区"
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:402
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:302
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msgid "Pad connection to zones:"
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msgstr "焊盘连接到覆铜："
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msgstr "焊盘连接到敷铜："
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:406
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:306
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msgid "Use zone setting"
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msgstr "使用覆铜设置"
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msgstr "使用敷铜设置"
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#: pcbnew/dialogs/dialog_footprint_properties_base.cpp:406
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#: pcbnew/dialogs/dialog_footprint_properties_fp_editor_base.cpp:306
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@ -24223,7 +24222,7 @@ msgstr "删除项"
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#: pcbnew/widgets/appearance_controls.cpp:338
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#: pcbnew/widgets/panel_selection_filter_base.cpp:53
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msgid "Zones"
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msgstr "覆铜"
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msgstr "敷铜"
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#: pcbnew/dialogs/dialog_global_deletion_base.cpp:31
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msgid "Board outlines"
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@ -24907,7 +24906,7 @@ msgstr "程度"
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#: pcbnew/dialogs/dialog_non_copper_zones_properties_base.h:84
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msgid "Non Copper Zones Properties"
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msgstr "非覆铜区属性"
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msgstr "非敷铜区属性"
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#: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:136
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msgid "Ring"
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@ -25490,7 +25489,7 @@ msgstr "防散热导线宽度："
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:746
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msgid "Custom pad shape in zone:"
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msgstr "覆铜中的自定义焊盘形状："
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msgstr "敷铜中的自定义焊盘形状："
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#: pcbnew/dialogs/dialog_pad_properties_base.cpp:750
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msgid "Use pad shape"
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@ -25715,7 +25714,7 @@ msgstr "负片绘制"
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#: pcbnew/dialogs/dialog_plot_base.cpp:149
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msgid "Check zone fills before plotting"
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msgstr "在绘制之前检查覆铜填充"
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msgstr "在绘制之前检查敷铜填充"
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#: pcbnew/dialogs/dialog_plot_base.cpp:169
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msgid "Global solder mask minimum width and/or margin are not set to 0. "
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@ -26391,7 +26390,7 @@ msgstr "禁止敷铜"
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#: pcbnew/dialogs/dialog_rule_area_properties_base.cpp:64
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msgid "Zones will not fill copper into this area"
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msgstr "覆铜时不会将铜填充到该区域以内"
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msgstr "敷铜时不会将铜填充到该区域以内"
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#: pcbnew/dialogs/dialog_rule_area_properties_base.cpp:68
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msgid "Keep out footprints"
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@ -26546,7 +26545,7 @@ msgstr "通过网自动更新"
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msgid ""
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"Automatically change the net of this via when the pads or zones it touches "
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"are changed"
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msgstr "当它接触的焊盘或覆铜更改时自动更改这个过孔的网络"
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msgstr "当它接触的焊盘或敷铜更改时自动更改这个过孔的网络"
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#: pcbnew/dialogs/dialog_track_via_properties_base.cpp:60
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msgid "Start point X:"
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@ -27144,11 +27143,11 @@ msgstr ""
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:86
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#, c-format
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msgid "Note: zone filling can be slow when < %s."
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msgstr "注：< %s 时覆铜填充可能会变慢。"
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msgstr "注：< %s 时敷铜填充可能会变慢。"
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:98
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msgid "Zone fill strategy"
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msgstr "覆铜填充策略"
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msgstr "敷铜填充策略"
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:111
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msgid "Mimic legacy behavior"
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@ -27170,11 +27169,11 @@ msgstr "平滑多边形 (最佳性能)"
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msgid ""
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"Better performance, exact export fidelity, and more complete filling near "
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"higher-priority zones."
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msgstr "更好的性能、精确的导出保真度，以及在较高优先级覆铜附近更完整的填充。"
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msgstr "更好的性能、精确的导出保真度，以及在较高优先级敷铜附近更完整的填充。"
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:134
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msgid "Allow fillets outside zone outline"
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msgstr "允许圆角超出覆铜轮廓"
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msgstr "允许圆角超出敷铜轮廓"
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#: pcbnew/dialogs/panel_setup_constraints_base.cpp:149
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msgid "Length tuning"
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@ -28045,7 +28044,6 @@ msgid "Check rule syntax"
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msgstr "检查规则语法"
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#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
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#, fuzzy
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msgid ""
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"### Top-level Clauses\n"
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"\n"
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@ -28254,83 +28252,121 @@ msgid ""
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" (constraint clearance (min \"1.5mm\"))\n"
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" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
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msgstr ""
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"### Top-level Clauses\n"
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"### 顶层语句\n"
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"\n"
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" 版本语句：(version <版本号>)\n"
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" (version <number>)\n"
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"# 版本语句：(version <版本号>)\n"
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"\n"
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"\n"
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" 规则语句：(rule <规则名> <规则语句> ...)\n"
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" (rule <rule_name> <rule_clause> ...)\n"
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"# 规则语句：(rule <规则名> <规则语句> ...)\n"
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"\n"
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"\n"
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"<br><br>\n"
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"\n"
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"### Rule Clauses\n"
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"### 规则语句\n"
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"\n"
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" 约束语句：(constraint <约束类型> ...)\n"
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" (constraint <constraint_type> ...)\n"
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"# 约束语句：(constraint <约束类型> ...)\n"
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"\n"
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" 条件语句：(condition \"<条件表达式>\")\n"
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" (condition \"<expression>\")\n"
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"# 条件语句：(condition \"<条件表达式>\")\n"
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"\n"
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" 层语句：(layer \"<层名>\")\n"
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" (layer \"<layer_name>\")\n"
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"# 层语句：(layer \"<层名>\")\n"
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"\n"
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"\n"
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"<br><br>\n"
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"\n"
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"### Constraint Types\n"
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"### 约束类型\n"
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"\n"
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" * annular_width （孔铜环宽度）\n"
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" * clearance （间隙）\n"
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" * courtyard_clearance （封装外框之间的间隙）\n"
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" * diff\\_pair\\_gap （差分对间隙）\n"
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" * annular\\_width\n"
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"# （孔铜环宽度）\n"
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" * clearance\n"
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"# （间隙）\n"
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" * courtyard_clearance\n"
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"# （封装外框之间的间隙）\n"
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" * diff\\_pair\\_gap\n"
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"# （差分对间隙）\n"
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" * diff\\_pair\\_uncoupled\n"
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" * disallow （不允许）\n"
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" * edge_clearance （与板边的间隙）\n"
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" * length （长度）\n"
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" * hole （孔）\n"
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" * hole_clearance （与孔的间隙）\n"
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" * silk_clearance （与丝印的间隙）\n"
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" * skew （偏移）\n"
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" * track_width （线宽）\n"
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" * via_count （过孔个数）\n"
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"# （对布线从该对中的另一个极性布线解耦的距离）\n"
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" * disallow\n"
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"# （不允许）\n"
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" * edge\\_clearance\n"
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"# （与板边的间隙）\n"
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" * length\n"
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"# （长度）\n"
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" * hole\n"
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"# （通孔）\n"
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" * hole\\_clearance\n"
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"# （与通孔的间隙）\n"
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" * silk\\_clearance\n"
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"# （与丝印的间隙）\n"
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" * skew\n"
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"# （总偏差）\n"
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" * track\\_width\n"
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"# （布线线宽）\n"
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" * via\\_count\n"
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"# （过孔个数）\n"
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"\n"
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"\n"
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"<br><br>\n"
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"\n"
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"### Item Types\n"
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"### 电路板元素类型\n"
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"\n"
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" * buried_via （埋孔）\n"
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" * graphic （图形）\n"
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" * hole （通孔）\n"
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" * micro_via （微孔）\n"
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" * pad （焊盘）\n"
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" * text （文字）\n"
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" * track （布线）\n"
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" * via （过孔）\n"
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" * zone （区域）\n"
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" * buried_via\n"
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"# （埋孔）\n"
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" * graphic\n"
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"# （图形）\n"
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" * hole\n"
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"# （通孔）\n"
|
||||
" * micro_via\n"
|
||||
"# （微孔）\n"
|
||||
" * pad\n"
|
||||
"# （焊盘）\n"
|
||||
" * text\n"
|
||||
"# （文本）\n"
|
||||
" * track\n"
|
||||
"# （布线）\n"
|
||||
" * via\n"
|
||||
"# （过孔）\n"
|
||||
" * zone\n"
|
||||
"# （敷铜）\n"
|
||||
"\n"
|
||||
"<br>\n"
|
||||
"\n"
|
||||
"### Examples\n"
|
||||
"### 范例\n"
|
||||
"\n"
|
||||
" (version 1)\n"
|
||||
"\n"
|
||||
" (rule 高压间距\n"
|
||||
" (rule HV\n"
|
||||
"# (rule 高压间距\n"
|
||||
" (constraint clearance (min 1.5mm))\n"
|
||||
" (condition \"A.NetClass == 'HV'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule 外层高压间距\n"
|
||||
" (rule HV\n"
|
||||
"# (rule 外层高压间距\n"
|
||||
" (layer outer)\n"
|
||||
" (constraint clearance (min 1.5mm))\n"
|
||||
" (condition \"A.NetClass == 'HV'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule 高压之间间距\n"
|
||||
" (rule HV_HV\n"
|
||||
"# (rule 高压之间间距\n"
|
||||
" # wider clearance between HV tracks\n"
|
||||
" # 高压线路之间间距应该更大\n"
|
||||
" (constraint clearance (min \"1.5mm + 2.0mm\"))\n"
|
||||
" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule 无护罩高压线路\n"
|
||||
" (rule HV_unshielded\n"
|
||||
"# (rule 无护罩高压线路\n"
|
||||
" (constraint clearance (min 2mm))\n"
|
||||
" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n"
|
||||
"<br><br>\n"
|
||||
|
|
@ -28346,12 +28382,14 @@ msgstr ""
|
|||
"使用 Ctrl+/ 来对选中的行添加或取消注释。\n"
|
||||
"<br><br><br>\n"
|
||||
"\n"
|
||||
"### Expression functions\n"
|
||||
"### 表达式函数\n"
|
||||
"\n"
|
||||
"函数的参数均支持简单的通配符（`*` 和 `?`）。\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" A.insideCourtyard('<封装标号>')\n"
|
||||
" A.insideCourtyard('<footprint_refdes>')\n"
|
||||
"# A.insideCourtyard('<封装位号>')\n"
|
||||
"若 `A` 的任何部分落在指定封装的主要外框中，则为真。\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
|
|
@ -28364,14 +28402,15 @@ msgstr ""
|
|||
"<br><br>\n"
|
||||
"\n"
|
||||
" A.insideArea('<zone_name>')\n"
|
||||
"若 `A` 的任何部分落在指定区域中，则为真。\n"
|
||||
"若 `A` 的任何部分落在指定敷铜中，则为真。\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" A.isPlated()\n"
|
||||
"若 `A` 含/是铜孔，则为真。\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" A.inDiffPair('<网络名>')\n"
|
||||
" A.inDiffPair('<net_name>')\n"
|
||||
"# A.inDiffPair('<网络名>')\n"
|
||||
"若 `A` 含有指定差分对的网络，则为真。\n"
|
||||
"`<网络名>` 是指定差分对的基础名称。例如， `inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
|
|
@ -28381,11 +28420,13 @@ msgstr ""
|
|||
"若 `A` 和 `B` 分别具有同一差分对的两个网络，则为真。\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" A.memberOf('<组名>')\n"
|
||||
" A.memberOf('<group_name>')\n"
|
||||
"# A.memberOf('<组名>')\n"
|
||||
"若 `A` 是指定组中的成员，则为真。组内嵌套的组也包括在内。\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" A.existsOnLayer('<层名>')\n"
|
||||
" A.existsOnLayer('<layer_name>')\n"
|
||||
"# A.existsOnLayer('<层名>')\n"
|
||||
"若 `A` 在指定的层中，则为真。层名可以是“电路板设置 >\n"
|
||||
"电路板编辑图层”菜单中指定的名称，也可以是内部最简名称\n"
|
||||
"（如 `F.Cu`）。\n"
|
||||
|
|
@ -28398,62 +28439,76 @@ msgstr ""
|
|||
"\n"
|
||||
"### 更多的范例\n"
|
||||
"\n"
|
||||
" (rule \"禁止铜区\"\n"
|
||||
" (rule \"copper keepout\"\n"
|
||||
"# (rule \"禁止铜区\"\n"
|
||||
" (constraint disallow track via zone)\n"
|
||||
" (condition \"A.insideArea('zone3')\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"BGA 加粗\"\n"
|
||||
" (rule \"BGA neckdown\"\n"
|
||||
"# (rule \"BGA 加粗\"\n"
|
||||
" (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
|
||||
" (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
|
||||
" (condition \"A.insideCourtyard('U3')\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" # prevent silk over tented vias\n"
|
||||
" # 禁止盖油过孔上印字\n"
|
||||
" (rule silk_over_via\n"
|
||||
" (constraint silk_clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"不同网络的过孔的间距\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
"# (rule \"不同网络的过孔的间距\" \n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"不同网络的焊盘的间距\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
"# (rule \"不同网络的焊盘的间距\" \n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"过孔到焊盘的间距\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
"# (rule \"过孔到焊盘的间距\" \n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"焊盘到导线的间距\" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
"# (rule \"焊盘到导线的间距\" \n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"1mm宽开槽周围的间距\"\n"
|
||||
" (rule \"clearance-to-1mm-cutout\"\n"
|
||||
"# (rule \"1mm宽开槽周围的间距\"\n"
|
||||
" (constraint clearance (min 0.8mm))\n"
|
||||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"最大机械孔孔径\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
"# (rule \"最大机械孔孔径\" \n"
|
||||
" (constraint hole (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"最大铜孔孔径\" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"# (rule \"最大铜孔孔径\" \n"
|
||||
" (constraint hole (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" # 给单独的差分对设置最优（opt）间距\n"
|
||||
" (rule \"CLK信号间距\"\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
"# (rule \"差分对信号间距\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" # 给任意差分对周围扩大间距\n"
|
||||
" (rule \"差分对外间距\"\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
"# (rule \"差分对外间距\"\n"
|
||||
" (constraint clearance (min \"1.5mm\"))\n"
|
||||
" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
|
||||
|
||||
|
|
@ -28580,7 +28635,7 @@ msgstr "添加禁布区 '%s'"
|
|||
|
||||
#: pcbnew/drc/drc_engine.cpp:694
|
||||
msgid "Tessellating copper zones..."
|
||||
msgstr "细分覆铜区..."
|
||||
msgstr "细分敷铜区..."
|
||||
|
||||
#: pcbnew/drc/drc_engine.cpp:795 pcbnew/drc/drc_engine.cpp:810
|
||||
#, c-format
|
||||
|
|
@ -28738,11 +28793,11 @@ msgstr "电路板边缘间隙违规"
|
|||
|
||||
#: pcbnew/drc/drc_item.cpp:78
|
||||
msgid "Copper areas intersect"
|
||||
msgstr "覆铜区交叉"
|
||||
msgstr "敷铜区交叉"
|
||||
|
||||
#: pcbnew/drc/drc_item.cpp:82
|
||||
msgid "Copper zone net has no pads"
|
||||
msgstr "覆铜区没有焊盘连接"
|
||||
msgstr "敷铜区没有焊盘连接"
|
||||
|
||||
#: pcbnew/drc/drc_item.cpp:86
|
||||
msgid "Via is not connected or connected on only one layer"
|
||||
|
|
@ -29004,7 +29059,7 @@ msgstr "(%s 最大环形宽度 %s；实际 %s)"
|
|||
|
||||
#: pcbnew/drc/drc_test_provider_connectivity.cpp:75
|
||||
msgid "Checking pad, via and zone connections..."
|
||||
msgstr "正在检查焊盘、过孔和覆铜连接..."
|
||||
msgstr "正在检查焊盘、过孔和敷铜连接..."
|
||||
|
||||
#: pcbnew/drc/drc_test_provider_connectivity.cpp:149
|
||||
msgid "Checking net connections..."
|
||||
|
|
@ -29032,11 +29087,11 @@ msgstr "正在检查焊盘..."
|
|||
|
||||
#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:241
|
||||
msgid "Checking copper zone clearances..."
|
||||
msgstr "正在检查覆铜区间隙..."
|
||||
msgstr "正在检查敷铜区间隙..."
|
||||
|
||||
#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:248
|
||||
msgid "Checking zones..."
|
||||
msgstr "正在检查覆铜..."
|
||||
msgstr "正在检查敷铜..."
|
||||
|
||||
#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:311
|
||||
#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:358
|
||||
|
|
@ -29263,12 +29318,12 @@ msgstr "(%s 最大直径 %s; 实际 %s)"
|
|||
|
||||
#: pcbnew/edit_zone_helpers.cpp:86 pcbnew/edit_zone_helpers.cpp:152
|
||||
msgid "Modify zone properties"
|
||||
msgstr "修改覆铜属性"
|
||||
msgstr "修改敷铜属性"
|
||||
|
||||
#: pcbnew/edit_zone_helpers.cpp:137
|
||||
#, c-format
|
||||
msgid "Refill %d Zones"
|
||||
msgstr "重新填充 %d 覆铜"
|
||||
msgstr "重新填充 %d 敷铜"
|
||||
|
||||
#: pcbnew/exporters/export_d356.cpp:376
|
||||
msgid "Export D-356 Test File"
|
||||
|
|
@ -29438,10 +29493,8 @@ msgid ""
|
|||
"This may result in different fills from previous KiCad versions which used "
|
||||
"the line thicknesses of the board boundary on the Edge Cuts layer."
|
||||
msgstr ""
|
||||
"如果此电路板上的覆铜被重新填充，将应用铜边缘间隙设置 （见电路板配置 > 设计规"
|
||||
"则 >限制）。\n"
|
||||
"这可能导致来自先前 KiCad 版本的不同填充，这些版本会将电路板边缘的线粗细用于 "
|
||||
"Edge Cuts 层。"
|
||||
"如果此电路板上的敷铜被重新填充，将应用铜边缘间隙设置 （见电路板配置 > 设计规则 >限制）。\n"
|
||||
"这可能导致来自先前 KiCad 版本的不同填充，这些版本会将电路板边缘的线粗细用于 Edge Cuts 层。"
|
||||
|
||||
#: pcbnew/files.cpp:549
|
||||
msgid "Edge Clearance Warning"
|
||||
|
|
@ -29675,7 +29728,7 @@ msgstr "封装图像文件名称"
|
|||
|
||||
#: pcbnew/footprint_editor_utils.cpp:220
|
||||
msgid "Edit Zone"
|
||||
msgstr "编辑覆铜"
|
||||
msgstr "编辑敷铜"
|
||||
|
||||
#: pcbnew/footprint_editor_utils.cpp:294
|
||||
#, c-format
|
||||
|
|
@ -30520,32 +30573,32 @@ msgstr "过孔连接到未知网络 (%s)。"
|
|||
#: pcbnew/netlist_reader/board_netlist_updater.cpp:704
|
||||
#, c-format
|
||||
msgid "Reconnect copper zone '%s' from %s to %s."
|
||||
msgstr "将覆铜区 '%s' 从 %s 重新连接到 %s。"
|
||||
msgstr "将敷铜区 '%s' 从 %s 重新连接到 %s。"
|
||||
|
||||
#: pcbnew/netlist_reader/board_netlist_updater.cpp:711
|
||||
#, c-format
|
||||
msgid "Reconnect copper zone from %s to %s."
|
||||
msgstr "将覆铜区 %s 重新连接到 %s。"
|
||||
msgstr "将敷铜区 %s 重新连接到 %s。"
|
||||
|
||||
#: pcbnew/netlist_reader/board_netlist_updater.cpp:732
|
||||
#, c-format
|
||||
msgid "Reconnected copper zone '%s' from %s to %s."
|
||||
msgstr "将覆铜区 '%s' 从 %s 重新连接到了 %s。"
|
||||
msgstr "将敷铜区 '%s' 从 %s 重新连接到了 %s。"
|
||||
|
||||
#: pcbnew/netlist_reader/board_netlist_updater.cpp:739
|
||||
#, c-format
|
||||
msgid "Reconnected copper zone from %s to %s."
|
||||
msgstr "将覆铜区从 %s 重新连接到了 %s。"
|
||||
msgstr "将敷铜区从 %s 重新连接到了 %s。"
|
||||
|
||||
#: pcbnew/netlist_reader/board_netlist_updater.cpp:752
|
||||
#, c-format
|
||||
msgid "Copper zone '%s' has no pads connected."
|
||||
msgstr "覆铜区 '%s' 没有与之连接的焊盘。"
|
||||
msgstr "敷铜区 '%s' 没有与之连接的焊盘。"
|
||||
|
||||
#: pcbnew/netlist_reader/board_netlist_updater.cpp:760
|
||||
#, c-format
|
||||
msgid "Copper zone on layer %s at (%s, %s) has no pads connected."
|
||||
msgstr "坐标 (%s, %s) 层 %s 上的覆铜区没有与之相连的焊盘。"
|
||||
msgstr "坐标 (%s, %s) 层 %s 上的敷铜区没有与之相连的焊盘。"
|
||||
|
||||
#: pcbnew/netlist_reader/board_netlist_updater.cpp:802
|
||||
#, c-format
|
||||
|
|
@ -31631,9 +31684,8 @@ msgid ""
|
|||
"between these two settings. The setting for disjoint copper has been applied "
|
||||
"as the minimum island area of the KiCad Zone."
|
||||
msgstr ""
|
||||
"CADSTAR 模板 '%s' 具有不同的设置，用于\"保留覆铜 - 不相交\"和\"保留覆铜 - 隔"
|
||||
"离\"。KiCad 不区分这两个设置。不相交覆铜的设置已作为 KiCad 覆铜的最小覆铜面积"
|
||||
"应用。"
|
||||
"CADSTAR 模板 '%s' 具有不同的设置，用于\"保留敷铜 - 不相交\"和\"保留敷铜 - 隔离\"。KiCad 不区分这两个设置。"
|
||||
"不相交敷铜的设置已作为 KiCad 敷铜的最小敷铜面积应用。"
|
||||
|
||||
#: pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp:1916
|
||||
#, c-format
|
||||
|
|
@ -31664,9 +31716,7 @@ msgid ""
|
|||
"The CADSTAR layer '%s' is defined as a power plane layer. However no net "
|
||||
"with such name exists. The layer has been loaded but no copper zone was "
|
||||
"created."
|
||||
msgstr ""
|
||||
"CADSTAR 层 '%s' 被定义为电源层。然而，不存在具有该名称的网络。已加载层，但未"
|
||||
"创建覆铜区。"
|
||||
msgstr "CADSTAR 层 '%s' 被定义为电源层。然而，不存在具有该名称的网络。已加载层，但未创建敷铜区。"
|
||||
|
||||
#: pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp:2085
|
||||
msgid ""
|
||||
|
|
@ -31675,9 +31725,8 @@ msgid ""
|
|||
"filled, or as a KiCad Track if the shape was an unfilled outline (open or "
|
||||
"closed)."
|
||||
msgstr ""
|
||||
"CADSTAR 设计包含没有直接 KiCad 等价物的铜元素。如果填充的是实体或图案填充，则"
|
||||
"它们已导入为 KiCad 覆铜；如果形状是未填充的轮廓(开放或闭合)，则它们将导入为 "
|
||||
"KiCad 布线。"
|
||||
"CADSTAR 设计包含没有直接 KiCad 等价物的铜元素。如果填充的是实体或图案填充，则它们已导入为 KiCad "
|
||||
"敷铜；如果形状是未填充的轮廓(开放或闭合)，则它们将导入为 KiCad 布线。"
|
||||
|
||||
#: pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp:2190
|
||||
#, c-format
|
||||
|
|
@ -31913,7 +31962,7 @@ msgstr "无效的令牌计数。预期为 8，但找到了 %zu。"
|
|||
#: pcbnew/plugins/fabmaster/import_fabmaster.cpp:1445
|
||||
#, c-format
|
||||
msgid "Invalid format for record_tag string '%s' in row %zu."
|
||||
msgstr "record_tag 字符串 \"%s\" 的无效格式，位于行 %zu。"
|
||||
msgstr "record_tag 字符串 '%s' 的无效格式位于行 %zu。"
|
||||
|
||||
#: pcbnew/plugins/fabmaster/import_fabmaster.cpp:1416
|
||||
#, c-format
|
||||
|
|
@ -32048,7 +32097,7 @@ msgstr "未知过孔类型 %d"
|
|||
#: pcbnew/plugins/kicad/kicad_plugin.cpp:2080
|
||||
#, c-format
|
||||
msgid "unknown zone corner smoothing type %d"
|
||||
msgstr "未知覆铜角平滑类型 %d"
|
||||
msgstr "未知敷铜角平滑类型 %d"
|
||||
|
||||
#: pcbnew/plugins/kicad/kicad_plugin.cpp:2301
|
||||
msgid "Open cancelled by user."
|
||||
|
|
@ -32241,12 +32290,12 @@ msgid ""
|
|||
"Convert zones to polygon fills?"
|
||||
msgstr ""
|
||||
"不再支持旧段填充模式。\n"
|
||||
"是否将覆铜转换为多边形填充？"
|
||||
"是否将敷铜转换为多边形填充？"
|
||||
|
||||
#: pcbnew/plugins/kicad/pcb_parser.cpp:5078
|
||||
#: pcbnew/plugins/legacy/legacy_plugin.cpp:2486
|
||||
msgid "Legacy Zone Warning"
|
||||
msgstr "旧覆铜警告"
|
||||
msgstr "旧敷铜警告"
|
||||
|
||||
#: pcbnew/plugins/legacy/legacy_plugin.cpp:596
|
||||
#, c-format
|
||||
|
|
@ -33084,7 +33133,7 @@ msgstr "解锁"
|
|||
|
||||
#: pcbnew/tools/board_editor_control.cpp:1457
|
||||
msgid "Duplicate zone"
|
||||
msgstr "复制覆铜"
|
||||
msgstr "复制敷铜"
|
||||
|
||||
#: pcbnew/tools/board_inspection_tool.cpp:59
|
||||
msgid "Net Tools"
|
||||
|
|
@ -33140,13 +33189,13 @@ msgstr "区域连接解像度，用于："
|
|||
#: pcbnew/tools/board_inspection_tool.cpp:397
|
||||
#, c-format
|
||||
msgid "Zone thermal relief: %s."
|
||||
msgstr "覆铜防散热 (花焊盘)：%s。"
|
||||
msgstr "敷铜防散热 (花焊盘)：%s。"
|
||||
|
||||
#: pcbnew/tools/board_inspection_tool.cpp:402
|
||||
#: pcbnew/tools/board_inspection_tool.cpp:421 pcbnew/zone.cpp:341
|
||||
#: pcbnew/zone.cpp:356 pcbnew/zone.cpp:504 pcbnew/zone.cpp:793
|
||||
msgid "zone"
|
||||
msgstr "覆铜"
|
||||
msgstr "敷铜"
|
||||
|
||||
#: pcbnew/tools/board_inspection_tool.cpp:404
|
||||
#, c-format
|
||||
|
|
@ -33156,7 +33205,7 @@ msgstr "被 %s 覆盖；防散热：%s。"
|
|||
#: pcbnew/tools/board_inspection_tool.cpp:414
|
||||
#, c-format
|
||||
msgid "Zone clearance: %s."
|
||||
msgstr "覆铜间隙：%s。"
|
||||
msgstr "敷铜间隙：%s。"
|
||||
|
||||
#: pcbnew/tools/board_inspection_tool.cpp:423
|
||||
#, c-format
|
||||
|
|
@ -33279,7 +33328,7 @@ msgstr "将形状转换为多边形"
|
|||
|
||||
#: pcbnew/tools/convert_tool.cpp:246
|
||||
msgid "Convert shapes to zone"
|
||||
msgstr "将形状转换为覆铜"
|
||||
msgstr "将形状转换为敷铜"
|
||||
|
||||
#: pcbnew/tools/convert_tool.cpp:748
|
||||
msgid "Convert polygons to lines"
|
||||
|
|
@ -33423,7 +33472,7 @@ msgstr "放置过孔"
|
|||
|
||||
#: pcbnew/tools/drc_tool.cpp:151
|
||||
msgid "Refilling all zones..."
|
||||
msgstr "重新填充所有覆铜..."
|
||||
msgstr "重新填充所有敷铜..."
|
||||
|
||||
#: pcbnew/tools/drc_tool.cpp:160
|
||||
msgid "Schematic parity tests require a fully annotated schematic."
|
||||
|
|
@ -33589,7 +33638,7 @@ msgstr "从所选创建区域"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:53
|
||||
msgid "Creates a copper zone from the selection"
|
||||
msgstr "从所选内容创建覆铜区"
|
||||
msgstr "从所选内容创建敷铜区"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:58
|
||||
msgid "Create Rule Area from Selection"
|
||||
|
|
@ -33701,11 +33750,11 @@ msgstr "添加引线标注"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:155
|
||||
msgid "Add Filled Zone"
|
||||
msgstr "添加填充覆铜"
|
||||
msgstr "添加填充敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:155
|
||||
msgid "Add a filled zone"
|
||||
msgstr "添加填充覆铜"
|
||||
msgstr "添加填充敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:161
|
||||
msgid "Add Vias"
|
||||
|
|
@ -33725,19 +33774,19 @@ msgstr "添加规则区域（禁布区）"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:173
|
||||
msgid "Add a Zone Cutout"
|
||||
msgstr "添加挖空覆铜"
|
||||
msgstr "添加挖空敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:173
|
||||
msgid "Add a cutout area of an existing zone"
|
||||
msgstr "添加挖空覆铜"
|
||||
msgstr "添加挖空敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:179
|
||||
msgid "Add a Similar Zone"
|
||||
msgstr "添加相似覆铜"
|
||||
msgstr "添加相似敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:179
|
||||
msgid "Add a zone with the same settings as an existing zone"
|
||||
msgstr "添加与现有覆铜具有相同设置的覆铜"
|
||||
msgstr "添加与现有敷铜具有相同设置的敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:185
|
||||
msgid "Import Graphics..."
|
||||
|
|
@ -34280,19 +34329,19 @@ msgstr "将过孔尺寸更改为上一个预定义尺寸"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:642
|
||||
msgid "Merge Zones"
|
||||
msgstr "合并覆铜"
|
||||
msgstr "合并敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:642
|
||||
msgid "Merge zones"
|
||||
msgstr "合并覆铜"
|
||||
msgstr "合并敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:646
|
||||
msgid "Duplicate Zone onto Layer..."
|
||||
msgstr "重复覆铜到层..."
|
||||
msgstr "重复敷铜到层..."
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:646
|
||||
msgid "Duplicate zone outline onto a different layer"
|
||||
msgstr "复制覆铜轮廓到不同的层上"
|
||||
msgstr "复制敷铜轮廓到不同的层上"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:651
|
||||
msgid "Add Layer Alignment Target"
|
||||
|
|
@ -34539,7 +34588,7 @@ msgstr "绘制区域填充"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:853
|
||||
msgid "Show filled areas of zones"
|
||||
msgstr "显示覆铜的填充区域"
|
||||
msgstr "显示敷铜的填充区域"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:858
|
||||
msgid "Draw Zone Outlines"
|
||||
|
|
@ -34547,7 +34596,7 @@ msgstr "绘制区域轮廓"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:858
|
||||
msgid "Show only zone boundaries"
|
||||
msgstr "仅显示覆铜边界"
|
||||
msgstr "仅显示敷铜边界"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:863
|
||||
msgid "Draw Zone Fill Fracture Borders"
|
||||
|
|
@ -34559,7 +34608,7 @@ msgstr "绘制区域填充三角剖分"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:874
|
||||
msgid "Toggle Zone Display"
|
||||
msgstr "切换覆铜显示"
|
||||
msgstr "切换敷铜显示"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:875
|
||||
msgid "Cycle between showing zone fills and just their outlines"
|
||||
|
|
@ -34894,7 +34943,7 @@ msgstr "按类型从选区删除项目"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1270 pcbnew/tools/zone_filler_tool.cpp:211
|
||||
msgid "Fill Zone"
|
||||
msgstr "填充覆铜"
|
||||
msgstr "填充敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1270
|
||||
msgid "Update copper fill of selected zone(s)"
|
||||
|
|
@ -34902,15 +34951,15 @@ msgstr "更新所选区域的铜填充"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1276 pcbnew/tools/zone_filler_tool.cpp:154
|
||||
msgid "Fill All Zones"
|
||||
msgstr "填充所有覆铜"
|
||||
msgstr "填充所有敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1276
|
||||
msgid "Update copper fill of all zones"
|
||||
msgstr "取消所有区域的覆铜"
|
||||
msgstr "取消所有区域的敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1281 pcbnew/tools/zone_filler_tool.cpp:249
|
||||
msgid "Unfill Zone"
|
||||
msgstr "取消填充覆铜"
|
||||
msgstr "取消填充敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1281
|
||||
msgid "Remove copper fill from selected zone(s)"
|
||||
|
|
@ -34922,7 +34971,7 @@ msgstr "取消填充所有区域"
|
|||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1287
|
||||
msgid "Remove copper fill from all zones"
|
||||
msgstr "从所有区域移除覆铜"
|
||||
msgstr "从所有区域移除敷铜"
|
||||
|
||||
#: pcbnew/tools/pcb_actions.cpp:1295
|
||||
msgid "Place Selected Footprints"
|
||||
|
|
@ -35093,7 +35142,7 @@ msgstr "拖动拐角"
|
|||
|
||||
#: pcbnew/tools/pcb_point_editor.cpp:2051
|
||||
msgid "Add a zone corner"
|
||||
msgstr "添加覆铜拐角"
|
||||
msgstr "添加敷铜拐角"
|
||||
|
||||
#: pcbnew/tools/pcb_point_editor.cpp:2088
|
||||
msgid "Split segment"
|
||||
|
|
@ -35101,7 +35150,7 @@ msgstr "分割线段"
|
|||
|
||||
#: pcbnew/tools/pcb_point_editor.cpp:2159
|
||||
msgid "Remove a zone/polygon corner"
|
||||
msgstr "删除覆铜或多边形的拐角"
|
||||
msgstr "删除敷铜或多边形的拐角"
|
||||
|
||||
#: pcbnew/tools/pcb_selection_tool.cpp:73
|
||||
msgid "Select"
|
||||
|
|
@ -35153,11 +35202,11 @@ msgstr "单击位号项..."
|
|||
|
||||
#: pcbnew/tools/zone_create_helper.cpp:176
|
||||
msgid "Add a zone cutout"
|
||||
msgstr "添加挖空覆铜"
|
||||
msgstr "添加挖空敷铜"
|
||||
|
||||
#: pcbnew/tools/zone_create_helper.cpp:215
|
||||
msgid "Add a zone"
|
||||
msgstr "添加覆铜"
|
||||
msgstr "添加敷铜"
|
||||
|
||||
#: pcbnew/tools/zone_create_helper.cpp:246
|
||||
msgid "Add a graphical polygon"
|
||||
|
|
@ -35165,12 +35214,12 @@ msgstr "添加多边形图形"
|
|||
|
||||
#: pcbnew/tools/zone_filler_tool.cpp:81
|
||||
msgid "Checking Zones"
|
||||
msgstr "检查覆铜"
|
||||
msgstr "检查敷铜"
|
||||
|
||||
#: pcbnew/tools/zone_filler_tool.cpp:89 pcbnew/tools/zone_filler_tool.cpp:162
|
||||
#: pcbnew/tools/zone_filler_tool.cpp:217
|
||||
msgid "Fill Zone(s)"
|
||||
msgstr "填充覆铜"
|
||||
msgstr "填充敷铜"
|
||||
|
||||
#: pcbnew/tools/zone_filler_tool.cpp:131
|
||||
msgid "Show DRC rules"
|
||||
|
|
@ -35182,7 +35231,7 @@ msgstr "规则"
|
|||
|
||||
#: pcbnew/tools/zone_filler_tool.cpp:144
|
||||
msgid "Zone fills may be inaccurate. DRC rules contain errors."
|
||||
msgstr "覆铜填充可能不准确。DRC 规则包含错误。"
|
||||
msgstr "敷铜填充可能不准确。DRC 规则包含错误。"
|
||||
|
||||
#: pcbnew/undo_redo.cpp:537
|
||||
msgid "Incomplete undo/redo operation: some items not found"
|
||||
|
|
@ -35202,7 +35251,7 @@ msgstr "显示所有焊盘"
|
|||
|
||||
#: pcbnew/widgets/appearance_controls.cpp:338
|
||||
msgid "Show copper zones"
|
||||
msgstr "显示覆铜区"
|
||||
msgstr "显示敷铜区"
|
||||
|
||||
#: pcbnew/widgets/appearance_controls.cpp:340
|
||||
msgid "Footprints Front"
|
||||
|
|
@ -35758,11 +35807,11 @@ msgstr "规则区域"
|
|||
|
||||
#: pcbnew/zone.cpp:558
|
||||
msgid "Copper Zone"
|
||||
msgstr "覆铜区"
|
||||
msgstr "敷铜区"
|
||||
|
||||
#: pcbnew/zone.cpp:560
|
||||
msgid "Non-copper Zone"
|
||||
msgstr "非覆铜区"
|
||||
msgstr "非敷铜区"
|
||||
|
||||
#: pcbnew/zone.cpp:565
|
||||
msgid "Cutout"
|
||||
|
|
@ -35782,7 +35831,7 @@ msgstr "无焊盘"
|
|||
|
||||
#: pcbnew/zone.cpp:583
|
||||
msgid "No copper zones"
|
||||
msgstr "无覆铜区"
|
||||
msgstr "无敷铜区"
|
||||
|
||||
#: pcbnew/zone.cpp:586
|
||||
msgid "No footprints"
|
||||
|
|
@ -35825,7 +35874,7 @@ msgstr "%s 上的规则区域挖空"
|
|||
#: pcbnew/zone.cpp:892
|
||||
#, c-format
|
||||
msgid "Zone Cutout on %s"
|
||||
msgstr "%s 上的覆铜挖空"
|
||||
msgstr "%s 上的敷铜挖空"
|
||||
|
||||
#: pcbnew/zone.cpp:897
|
||||
#, c-format
|
||||
|
|
@ -35835,7 +35884,7 @@ msgstr "%s上的规则区域"
|
|||
#: pcbnew/zone.cpp:899
|
||||
#, c-format
|
||||
msgid "Zone %s on %s"
|
||||
msgstr "%s 上的覆铜%s"
|
||||
msgstr "%s 上的敷铜%s"
|
||||
|
||||
#: pcbnew/zone.cpp:1464
|
||||
msgid "Inherited"
|
||||
|
|
@ -35851,7 +35900,7 @@ msgstr "焊盘连接"
|
|||
|
||||
#: pcbnew/zone_filler.cpp:96
|
||||
msgid "Building zone fills..."
|
||||
msgstr "构造覆铜填充..."
|
||||
msgstr "构造敷铜填充..."
|
||||
|
||||
#: pcbnew/zone_filler.cpp:302
|
||||
msgid "Removing isolated copper islands..."
|
||||
|
|
@ -35859,15 +35908,15 @@ msgstr "正在移除孤立的铜岛..."
|
|||
|
||||
#: pcbnew/zone_filler.cpp:415
|
||||
msgid "Zone fills are out-of-date. Refill?"
|
||||
msgstr "覆铜填充已失效，重新填充？"
|
||||
msgstr "敷铜填充已失效，重新填充？"
|
||||
|
||||
#: pcbnew/zone_filler.cpp:417
|
||||
msgid "Refill"
|
||||
msgstr "重新覆铜"
|
||||
msgstr "重新敷铜"
|
||||
|
||||
#: pcbnew/zone_filler.cpp:417
|
||||
msgid "Continue without Refill"
|
||||
msgstr "取消覆铜"
|
||||
msgstr "取消敷铜"
|
||||
|
||||
#: pcbnew/zone_filler.cpp:428
|
||||
msgid "Performing polygon fills..."
|
||||
|
|
|
|||
Loading…
Reference in New Issue