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Update translations 

This fixes the translation strings that were inadvertently changed at
the last moment
This commit is contained in:
Seth Hillbrand 2023-02-10 15:35:34 -08:00
parent fda3feaf3f
commit c53ce01b89
37 changed files with 114 additions and 992 deletions
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11
translation/pofiles/ar.po
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@ -2,7 +2,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2018-07-15 17:07+0200\n"
"Language: ar\n"
"MIME-Version: 1.0\n"
@ -14565,7 +14565,7 @@ msgid "Invalid Ramp"
msgstr ""
#: eeschema/sim/kibis/ibis_parser.cpp:613
msgid "Checking Header... "
msgid "Checking Header..."
msgstr ""
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -30088,12 +30088,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/bg.po
View File

@ -3,7 +3,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 21:07+0000\n"
"Last-Translator: Michał Radziejewicz <radziejewiczmichal@gmail.com>\n"
"Language-Team: Bulgarian <https://hosted.weblate.org/projects/kicad/master-"
@ -16360,7 +16360,7 @@ msgstr "X мащаб:"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Старт на запълване..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -34059,12 +34059,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/ca.po
View File

@ -4,7 +4,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-20 06:51+0000\n"
"Last-Translator: Seth Hillbrand <seth@kipro-pcb.com>\n"
"Language-Team: Catalan <https://hosted.weblate.org/projects/kicad/master-"
@ -15555,7 +15555,7 @@ msgstr "Entrada no vàlida"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "S'estan verificant els pads..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32565,12 +32565,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

12
translation/pofiles/cs.po
View File

@ -17,7 +17,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 07:25+0000\n"
"Last-Translator: Jan Straka <bach@email.cz>\n"
"Language-Team: Czech <https://hosted.weblate.org/projects/kicad/master-"
@ -15342,8 +15342,7 @@ msgid "Invalid Ramp"
msgstr "Neplatný Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Kontroluji hlavičku..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31521,12 +31520,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/da.po
View File

@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-20 06:51+0000\n"
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
"Language-Team: Danish <https://hosted.weblate.org/projects/kicad/master-"
@ -15790,7 +15790,7 @@ msgstr "Ugyldig"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Kontrol af stifter ..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32717,12 +32717,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

13
translation/pofiles/de.po
View File

@ -18,7 +18,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad i18n Deutsch\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-09 11:36+0000\n"
"Last-Translator: Mark Hämmerling <dev@markh.de>\n"
"Language-Team: German <https://hosted.weblate.org/projects/kicad/master-"
@ -15605,8 +15605,7 @@ msgid "Invalid Ramp"
msgstr "Ungültige Rampe"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Prüfe Header ..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31806,7 +31805,6 @@ msgid "Check rule syntax"
msgstr "Regelsyntax überprüfen"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -32128,12 +32126,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Allgemeine Bestimmungen\n"
"\n"

13
translation/pofiles/el.po
View File

@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 21:07+0000\n"
"Last-Translator: Michael Misirlis <MMISIRLIS@gmail.com>\n"
"Language-Team: Greek <https://hosted.weblate.org/projects/kicad/master-"
@ -15568,8 +15568,7 @@ msgid "Invalid Ramp"
msgstr "Μη έγκυρη Ράμπα"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Έλεγχος Επικεφαλίδας..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31765,7 +31764,6 @@ msgid "Check rule syntax"
msgstr "Ελέγξτε τη σύνταξη κανόνων"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -32087,12 +32085,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Κανόνες ανώτατου επιπέδου\n"
"\n"

676
translation/pofiles/en.po
View File

@ -2,7 +2,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2018-07-15 17:07+0200\n"
"Last-Translator: Simon Richter <Simon.Richter@hogyros.de>\n"
"Language-Team: Simon Richter <Simon.Richter@hogyros.de>\n"
@ -10419,8 +10419,8 @@ msgstr "Invalid GND clamp."
msgid "Invalid Ramp"
msgstr "Invalid Ramp"
msgid "Checking Header... "
msgstr "Checking Header... "
msgid "Checking Header..."
msgstr "Checking Header..."
msgid "Missing [IBIS Ver]"
msgstr "Missing [IBIS Ver]"
@ -22315,12 +22315,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Top-level Clauses\n"
"\n"
@ -22642,12 +22637,7 @@ msgstr ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgid "Default properties for new dimension objects:"
msgstr "Default properties for new dimension objects:"
@ -29428,665 +29418,9 @@ msgstr "KiCad Schematic"
msgid "KiCad Printed Circuit Board"
msgstr "KiCad Printed Circuit Board"
#~ msgid "Checking Header..."
#~ msgstr "Checking Header..."
#~ msgid "Reading file "
#~ msgstr "Reading file "
#~ msgid ""
#~ "### Top-level Clauses\n"
#~ "\n"
#~ " (version <number>)\n"
#~ "\n"
#~ " (rule <rule_name> <rule_clause> ...)\n"
#~ "\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Rule Clauses\n"
#~ "\n"
#~ " (constraint <constraint_type> ...)\n"
#~ "\n"
#~ " (condition \"<expression>\")\n"
#~ "\n"
#~ " (layer \"<layer_name>\")\n"
#~ "\n"
#~ " (severity <severity_name>)\n"
#~ "\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Constraint Types\n"
#~ "\n"
#~ " * annular\\_width\n"
#~ " * assertion\n"
#~ " * clearance\n"
#~ " * connection\\_width\n"
#~ " * courtyard_clearance\n"
#~ " * diff\\_pair\\_gap\n"
#~ " * diff\\_pair\\_uncoupled\n"
#~ " * disallow\n"
#~ " * edge\\_clearance\n"
#~ " * length\n"
#~ " * hole\\_clearance\n"
#~ " * hole\\_size\n"
#~ " * min\\_resolved\\_spokes\n"
#~ " * physical\\_clearance\n"
#~ " * physical\\_hole\\_clearance\n"
#~ " * silk\\_clearance\n"
#~ " * skew\n"
#~ " * text\\_height\n"
#~ " * text\\_thickness\n"
#~ " * thermal\\_relief\\_gap\n"
#~ " * thermal\\_spoke\\_width\n"
#~ " * track\\_width\n"
#~ " * via\\_count\n"
#~ " * via\\_diameter\n"
#~ " * zone\\_connection\n"
#~ "\n"
#~ "Note: `clearance` and `hole_clearance` rules are not run against items of "
#~ "the same net; `physical_clearance` and `physical_hole_clearance` rules "
#~ "are.\n"
#~ "<br><br>\n"
#~ "\n"
#~ "### Items\n"
#~ "\n"
#~ " * `A` &nbsp;&nbsp; _the first (or only) item under test_\n"
#~ " * `B` &nbsp;&nbsp; _the second item under test (for binary tests)_\n"
#~ " * `L` &nbsp;&nbsp; _the layer currently under test_\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Item Types\n"
#~ "\n"
#~ " * buried\\_via\n"
#~ " * graphic\n"
#~ " * hole\n"
#~ " * micro\\_via\n"
#~ " * pad\n"
#~ " * text\n"
#~ " * track\n"
#~ " * via\n"
#~ " * zone\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Zone Connections\n"
#~ "\n"
#~ " * solid\n"
#~ " * thermal\\_reliefs\n"
#~ " * none\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Severity Names\n"
#~ "\n"
#~ " * warning\n"
#~ " * error\n"
#~ " * exclusion\n"
#~ " * ignore\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Examples\n"
#~ "\n"
#~ " (version 1)\n"
#~ "\n"
#~ " (rule HV\n"
#~ " (constraint clearance (min 1.5mm))\n"
#~ " (condition \"A.NetClass == 'HV'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule HV\n"
#~ " (layer outer)\n"
#~ " (constraint clearance (min 1.5mm))\n"
#~ " (condition \"A.NetClass == 'HV'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule HV_HV\n"
#~ " # wider clearance between HV tracks\n"
#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n"
#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule HV_unshielded\n"
#~ " (constraint clearance (min 2mm))\n"
#~ " (condition \"A.NetClass == 'HV' && !A."
#~ "enclosedByArea('Shield*')\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule heavy_thermals\n"
#~ " (constraint thermal_spoke_width (min 0.5mm))\n"
#~ " (condition \"A.NetClass == 'HV'\"))\n"
#~ "<br><br>\n"
#~ "\n"
#~ "### Notes\n"
#~ "\n"
#~ "Version clause must be the first clause. It indicates the syntax version "
#~ "of the file so that \n"
#~ "future rules parsers can perform automatic updates. It should be\n"
#~ "set to \"1\".\n"
#~ "\n"
#~ "Rules should be ordered by specificity. Later rules take\n"
#~ "precedence over earlier rules; once a matching rule is found\n"
#~ "no further rules will be checked.\n"
#~ "\n"
#~ "Use Ctrl+/ to comment or uncomment line(s).\n"
#~ "<br><br><br>\n"
#~ "\n"
#~ "### Expression functions\n"
#~ "\n"
#~ "All function parameters support simple wildcards (`*` and `?`).\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsCourtyard('<footprint_refdes>')\n"
#~ "True if any part of `A` lies within the given footprint's principal "
#~ "courtyard.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsFrontCourtyard('<footprint_refdes>')\n"
#~ "True if any part of `A` lies within the given footprint's front "
#~ "courtyard.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsBackCourtyard('<footprint_refdes>')\n"
#~ "True if any part of `A` lies within the given footprint's back "
#~ "courtyard.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsArea('<zone_name>')\n"
#~ "True if any part of `A` lies within the given zone's outline.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.enclosedByArea('<zone_name>')\n"
#~ "True if all of `A` lies within the given zone's outline. \n"
#~ "\n"
#~ "NB: this is potentially a more expensive call than `intersectsArea()`. "
#~ "Use `intersectsArea()` \n"
#~ "where possible.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.isPlated()\n"
#~ "True if `A` has a hole which is plated.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.inDiffPair('<net_name>')\n"
#~ "True if `A` has a net that is part of the specified differential pair.\n"
#~ "`<net_name>` is the base name of the differential pair. For example, "
#~ "`inDiffPair('/CLK')`\n"
#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " AB.isCoupledDiffPair()\n"
#~ "True if `A` and `B` are members of the same diff pair.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.memberOf('<group_name>')\n"
#~ "True if `A` is a member of the given group. Includes nested membership.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.existsOnLayer('<layer_name>')\n"
#~ "True if `A` exists on the given layer. The layer name can be\n"
#~ "either the name assigned in Board Setup > Board Editor Layers or\n"
#~ "the canonical name (ie: `F.Cu`).\n"
#~ "\n"
#~ "NB: this returns true if `A` is on the given layer, independently\n"
#~ "of whether or not the rule is being evaluated for that layer.\n"
#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideCourtyard('<footprint_refdes>') !!!\n"
#~ "Deprecated; use `intersectsCourtyard()` instead.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideFrontCourtyard('<footprint_refdes>') !!!\n"
#~ "Deprecated; use `intersectsFrontCourtyard()` instead.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideBackCourtyard('<footprint_refdes>') !!!\n"
#~ "Deprecated; use `intersectsBackCourtyard()` instead.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideArea('<zone_name>') !!!\n"
#~ "Deprecated; use `intersectsArea()` instead.\n"
#~ "<br><br><br>\n"
#~ "\n"
#~ "### More Examples\n"
#~ "\n"
#~ " (rule \"copper keepout\"\n"
#~ " (constraint disallow track via zone)\n"
#~ " (condition \"A.intersectsArea('zone3')\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"BGA neckdown\"\n"
#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
#~ " (condition \"A.intersectsCourtyard('U3')\"))\n"
#~ "\n"
#~ "\n"
#~ " # prevent silk over tented vias\n"
#~ " (rule silk_over_via\n"
#~ " (constraint silk_clearance (min 0.2mm))\n"
#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"Distance between Vias of Different Nets\"\n"
#~ " (constraint hole_to_hole (min 0.254mm))\n"
#~ " (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B."
#~ "Net\"))\n"
#~ "\n"
#~ " (rule \"Clearance between Pads of Different Nets\"\n"
#~ " (constraint clearance (min 3.0mm))\n"
#~ " (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B."
#~ "Net\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"Via Hole to Track Clearance\"\n"
#~ " (constraint hole_clearance (min 0.254mm))\n"
#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
#~ "\n"
#~ " (rule \"Pad to Track Clearance\"\n"
#~ " (constraint clearance (min 0.2mm))\n"
#~ " (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"clearance-to-1mm-cutout\"\n"
#~ " (constraint clearance (min 0.8mm))\n"
#~ " (condition \"A.Layer == 'Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"Max Drill Hole Size Mechanical\"\n"
#~ " (constraint hole_size (max 6.3mm))\n"
#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
#~ "\n"
#~ " (rule \"Max Drill Hole Size PTH\"\n"
#~ " (constraint hole_size (max 6.35mm))\n"
#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Specify an optimal gap for a particular diff-pair\n"
#~ " (rule \"dp clock gap\"\n"
#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n"
#~ " (condition \"A.inDiffPair('/CLK')\"))\n"
#~ "\n"
#~ " # Specify a larger clearance around any diff-pair\n"
#~ " (rule \"dp clearance\"\n"
#~ " (constraint clearance (min \"1.5mm\"))\n"
#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
#~ "\n"
#~ "\n"
#~ " # Don't use thermal reliefs on heatsink pads\n"
#~ " (rule heat_sink_pad\n"
#~ " (constraint zone_connection solid)\n"
#~ " (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n"
#~ "\n"
#~ " # Require all four thermal relief spokes to connect to parent zone\n"
#~ " (rule fully_spoked_pads\n"
#~ " (constraint min_resolved_spokes 4))\n"
#~ "\n"
#~ " # Set thermal relief gap & spoke width for all zones\n"
#~ " (rule defined_relief\n"
#~ " (constraint thermal_relief_gap (min 10mil))\n"
#~ " (constraint thermal_spoke_width (min 12mil)))\n"
#~ "\n"
#~ " # Override thermal relief gap & spoke width for GND and PWR zones\n"
#~ " (rule defined_relief_pwr\n"
#~ " (constraint thermal_relief_gap (min 10mil))\n"
#~ " (constraint thermal_spoke_width (min 12mil))\n"
#~ " (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Prevent solder wicking from SMD pads\n"
#~ " (rule holes_in_pads\n"
#~ " (constraint physical_hole_clearance (min 0.2mm))\n"
#~ " (condition \"B.Pad_Type == 'SMD'\"))\n"
#~ "\n"
#~ " # Disallow solder mask margin overrides\n"
#~ " (rule \"disallow solder mask margin overrides\"\n"
#~ " (constraint assertion \"A.Soldermask_Margin_Override == 0mm\")\n"
#~ " (condition \"A.Type == 'Pad'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Enforce a mechanical clearance between components and board edge\n"
#~ " (rule front_mechanical_board_edge_clearance\n"
#~ " (layer \"F.Courtyard\")\n"
#~ " (constraint physical_clearance (min 3mm))\n"
#~ " (condition \"B.Layer == 'Edge.Cuts'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Check current-carrying capacity\n"
#~ " (rule high-current\n"
#~ " (constraint track_width (min 1.0mm))\n"
#~ " (constraint connection_width (min 0.8mm))\n"
#~ " (condition \"A.NetClass == 'Power'\"))"
#~ msgstr ""
#~ "### Top-level Clauses\n"
#~ "\n"
#~ " (version <number>)\n"
#~ "\n"
#~ " (rule <rule_name> <rule_clause> ...)\n"
#~ "\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Rule Clauses\n"
#~ "\n"
#~ " (constraint <constraint_type> ...)\n"
#~ "\n"
#~ " (condition \"<expression>\")\n"
#~ "\n"
#~ " (layer \"<layer_name>\")\n"
#~ "\n"
#~ " (severity <severity_name>)\n"
#~ "\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Constraint Types\n"
#~ "\n"
#~ " * annular\\_width\n"
#~ " * assertion\n"
#~ " * clearance\n"
#~ " * connection\\_width\n"
#~ " * courtyard_clearance\n"
#~ " * diff\\_pair\\_gap\n"
#~ " * diff\\_pair\\_uncoupled\n"
#~ " * disallow\n"
#~ " * edge\\_clearance\n"
#~ " * length\n"
#~ " * hole\\_clearance\n"
#~ " * hole\\_size\n"
#~ " * min\\_resolved\\_spokes\n"
#~ " * physical\\_clearance\n"
#~ " * physical\\_hole\\_clearance\n"
#~ " * silk\\_clearance\n"
#~ " * skew\n"
#~ " * text\\_height\n"
#~ " * text\\_thickness\n"
#~ " * thermal\\_relief\\_gap\n"
#~ " * thermal\\_spoke\\_width\n"
#~ " * track\\_width\n"
#~ " * via\\_count\n"
#~ " * via\\_diameter\n"
#~ " * zone\\_connection\n"
#~ "\n"
#~ "Note: `clearance` and `hole_clearance` rules are not run against items of "
#~ "the same net; `physical_clearance` and `physical_hole_clearance` rules "
#~ "are.\n"
#~ "<br><br>\n"
#~ "\n"
#~ "### Items\n"
#~ "\n"
#~ " * `A` &nbsp;&nbsp; _the first (or only) item under test_\n"
#~ " * `B` &nbsp;&nbsp; _the second item under test (for binary tests)_\n"
#~ " * `L` &nbsp;&nbsp; _the layer currently under test_\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Item Types\n"
#~ "\n"
#~ " * buried\\_via\n"
#~ " * graphic\n"
#~ " * hole\n"
#~ " * micro\\_via\n"
#~ " * pad\n"
#~ " * text\n"
#~ " * track\n"
#~ " * via\n"
#~ " * zone\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Zone Connections\n"
#~ "\n"
#~ " * solid\n"
#~ " * thermal\\_reliefs\n"
#~ " * none\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Severity Names\n"
#~ "\n"
#~ " * warning\n"
#~ " * error\n"
#~ " * exclusion\n"
#~ " * ignore\n"
#~ "\n"
#~ "<br>\n"
#~ "\n"
#~ "### Examples\n"
#~ "\n"
#~ " (version 1)\n"
#~ "\n"
#~ " (rule HV\n"
#~ " (constraint clearance (min 1.5mm))\n"
#~ " (condition \"A.NetClass == 'HV'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule HV\n"
#~ " (layer outer)\n"
#~ " (constraint clearance (min 1.5mm))\n"
#~ " (condition \"A.NetClass == 'HV'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule HV_HV\n"
#~ " # wider clearance between HV tracks\n"
#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n"
#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule HV_unshielded\n"
#~ " (constraint clearance (min 2mm))\n"
#~ " (condition \"A.NetClass == 'HV' && !A."
#~ "enclosedByArea('Shield*')\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule heavy_thermals\n"
#~ " (constraint thermal_spoke_width (min 0.5mm))\n"
#~ " (condition \"A.NetClass == 'HV'\"))\n"
#~ "<br><br>\n"
#~ "\n"
#~ "### Notes\n"
#~ "\n"
#~ "Version clause must be the first clause. It indicates the syntax version "
#~ "of the file so that \n"
#~ "future rules parsers can perform automatic updates. It should be\n"
#~ "set to \"1\".\n"
#~ "\n"
#~ "Rules should be ordered by specificity. Later rules take\n"
#~ "precedence over earlier rules; once a matching rule is found\n"
#~ "no further rules will be checked.\n"
#~ "\n"
#~ "Use Ctrl+/ to comment or uncomment line(s).\n"
#~ "<br><br><br>\n"
#~ "\n"
#~ "### Expression functions\n"
#~ "\n"
#~ "All function parameters support simple wildcards (`*` and `?`).\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsCourtyard('<footprint_refdes>')\n"
#~ "True if any part of `A` lies within the given footprint's principal "
#~ "courtyard.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsFrontCourtyard('<footprint_refdes>')\n"
#~ "True if any part of `A` lies within the given footprint's front "
#~ "courtyard.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsBackCourtyard('<footprint_refdes>')\n"
#~ "True if any part of `A` lies within the given footprint's back "
#~ "courtyard.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.intersectsArea('<zone_name>')\n"
#~ "True if any part of `A` lies within the given zone's outline.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.enclosedByArea('<zone_name>')\n"
#~ "True if all of `A` lies within the given zone's outline. \n"
#~ "\n"
#~ "NB: this is potentially a more expensive call than `intersectsArea()`. "
#~ "Use `intersectsArea()` \n"
#~ "where possible.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.isPlated()\n"
#~ "True if `A` has a hole which is plated.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.inDiffPair('<net_name>')\n"
#~ "True if `A` has a net that is part of the specified differential pair.\n"
#~ "`<net_name>` is the base name of the differential pair. For example, "
#~ "`inDiffPair('/CLK')`\n"
#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " AB.isCoupledDiffPair()\n"
#~ "True if `A` and `B` are members of the same diff pair.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.memberOf('<group_name>')\n"
#~ "True if `A` is a member of the given group. Includes nested membership.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " A.existsOnLayer('<layer_name>')\n"
#~ "True if `A` exists on the given layer. The layer name can be\n"
#~ "either the name assigned in Board Setup > Board Editor Layers or\n"
#~ "the canonical name (ie: `F.Cu`).\n"
#~ "\n"
#~ "NB: this returns true if `A` is on the given layer, independently\n"
#~ "of whether or not the rule is being evaluated for that layer.\n"
#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideCourtyard('<footprint_refdes>') !!!\n"
#~ "Deprecated; use `intersectsCourtyard()` instead.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideFrontCourtyard('<footprint_refdes>') !!!\n"
#~ "Deprecated; use `intersectsFrontCourtyard()` instead.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideBackCourtyard('<footprint_refdes>') !!!\n"
#~ "Deprecated; use `intersectsBackCourtyard()` instead.\n"
#~ "<br><br>\n"
#~ "\n"
#~ " !!! A.insideArea('<zone_name>') !!!\n"
#~ "Deprecated; use `intersectsArea()` instead.\n"
#~ "<br><br><br>\n"
#~ "\n"
#~ "### More Examples\n"
#~ "\n"
#~ " (rule \"copper keepout\"\n"
#~ " (constraint disallow track via zone)\n"
#~ " (condition \"A.intersectsArea('zone3')\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"BGA neckdown\"\n"
#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
#~ " (condition \"A.intersectsCourtyard('U3')\"))\n"
#~ "\n"
#~ "\n"
#~ " # prevent silk over tented vias\n"
#~ " (rule silk_over_via\n"
#~ " (constraint silk_clearance (min 0.2mm))\n"
#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"Distance between Vias of Different Nets\"\n"
#~ " (constraint hole_to_hole (min 0.254mm))\n"
#~ " (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B."
#~ "Net\"))\n"
#~ "\n"
#~ " (rule \"Clearance between Pads of Different Nets\"\n"
#~ " (constraint clearance (min 3.0mm))\n"
#~ " (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B."
#~ "Net\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"Via Hole to Track Clearance\"\n"
#~ " (constraint hole_clearance (min 0.254mm))\n"
#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
#~ "\n"
#~ " (rule \"Pad to Track Clearance\"\n"
#~ " (constraint clearance (min 0.2mm))\n"
#~ " (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"clearance-to-1mm-cutout\"\n"
#~ " (constraint clearance (min 0.8mm))\n"
#~ " (condition \"A.Layer == 'Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
#~ "\n"
#~ "\n"
#~ " (rule \"Max Drill Hole Size Mechanical\"\n"
#~ " (constraint hole_size (max 6.3mm))\n"
#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
#~ "\n"
#~ " (rule \"Max Drill Hole Size PTH\"\n"
#~ " (constraint hole_size (max 6.35mm))\n"
#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Specify an optimal gap for a particular diff-pair\n"
#~ " (rule \"dp clock gap\"\n"
#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n"
#~ " (condition \"A.inDiffPair('/CLK')\"))\n"
#~ "\n"
#~ " # Specify a larger clearance around any diff-pair\n"
#~ " (rule \"dp clearance\"\n"
#~ " (constraint clearance (min \"1.5mm\"))\n"
#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
#~ "\n"
#~ "\n"
#~ " # Don't use thermal reliefs on heatsink pads\n"
#~ " (rule heat_sink_pad\n"
#~ " (constraint zone_connection solid)\n"
#~ " (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n"
#~ "\n"
#~ " # Require all four thermal relief spokes to connect to parent zone\n"
#~ " (rule fully_spoked_pads\n"
#~ " (constraint min_resolved_spokes 4))\n"
#~ "\n"
#~ " # Set thermal relief gap & spoke width for all zones\n"
#~ " (rule defined_relief\n"
#~ " (constraint thermal_relief_gap (min 10mil))\n"
#~ " (constraint thermal_spoke_width (min 12mil)))\n"
#~ "\n"
#~ " # Override thermal relief gap & spoke width for GND and PWR zones\n"
#~ " (rule defined_relief_pwr\n"
#~ " (constraint thermal_relief_gap (min 10mil))\n"
#~ " (constraint thermal_spoke_width (min 12mil))\n"
#~ " (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Prevent solder wicking from SMD pads\n"
#~ " (rule holes_in_pads\n"
#~ " (constraint physical_hole_clearance (min 0.2mm))\n"
#~ " (condition \"B.Pad_Type == 'SMD'\"))\n"
#~ "\n"
#~ " # Disallow solder mask margin overrides\n"
#~ " (rule \"disallow solder mask margin overrides\"\n"
#~ " (constraint assertion \"A.Soldermask_Margin_Override == 0mm\")\n"
#~ " (condition \"A.Type == 'Pad'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Enforce a mechanical clearance between components and board edge\n"
#~ " (rule front_mechanical_board_edge_clearance\n"
#~ " (layer \"F.Courtyard\")\n"
#~ " (constraint physical_clearance (min 3mm))\n"
#~ " (condition \"B.Layer == 'Edge.Cuts'\"))\n"
#~ "\n"
#~ "\n"
#~ " # Check current-carrying capacity\n"
#~ " (rule high-current\n"
#~ " (constraint track_width (min 1.0mm))\n"
#~ " (constraint connection_width (min 0.8mm))\n"
#~ " (condition \"A.NetClass == 'Power'\"))"
#~ msgid "Filter other symbol fields by name:"
#~ msgstr "Filter other symbol fields by name:"

13
translation/pofiles/es.po
View File

@ -14,7 +14,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad Spanish Translation\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2022-12-03 01:48+0000\n"
"Last-Translator: VicSanRoPe <vicsanrope@protonmail.com>\n"
"Language-Team: Spanish <https://hosted.weblate.org/projects/kicad/master-"
@ -15550,8 +15550,7 @@ msgid "Invalid Ramp"
msgstr "Rampa inválida"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Comprobando cabecera..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31730,7 +31729,6 @@ msgid "Check rule syntax"
msgstr "Verificar reglas de sintaxis"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -32052,12 +32050,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Cláusulas de nivel superior\n"
"\n"

13
translation/pofiles/es_MX.po
View File

@ -14,7 +14,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad Spanish Translation\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-30 07:26+0000\n"
"Last-Translator: Ulices <dev.n47os@aleeas.com>\n"
"Language-Team: Spanish (Mexico) <https://hosted.weblate.org/projects/kicad/"
@ -15544,8 +15544,7 @@ msgid "Invalid Ramp"
msgstr "Rampa inválida"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Comprobando cabecera..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31724,7 +31723,6 @@ msgid "Check rule syntax"
msgstr "Verificar reglas de sintaxis"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -32046,12 +32044,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Cláusulas de nivel superior\n"
"\n"

11
translation/pofiles/et.po
View File

@ -3,7 +3,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-27 14:28+0000\n"
"Last-Translator: Ivan Chuba <xtrvweb@gmail.com>\n"
"Language-Team: Estonian <https://hosted.weblate.org/projects/kicad/master-"
@ -14571,7 +14571,7 @@ msgid "Invalid Ramp"
msgstr ""
#: eeschema/sim/kibis/ibis_parser.cpp:613
msgid "Checking Header... "
msgid "Checking Header..."
msgstr ""
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -30094,12 +30094,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

13
translation/pofiles/fi.po
View File

@ -16,7 +16,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 07:25+0000\n"
"Last-Translator: Toni Laiho <apelegeos@gmail.com>\n"
"Language-Team: Finnish <https://hosted.weblate.org/projects/kicad/master-"
@ -15449,8 +15449,7 @@ msgid "Invalid Ramp"
msgstr "Virheellinen Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Tarkistetaan Otsikko..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31488,7 +31487,6 @@ msgid "Check rule syntax"
msgstr "Tarkista säännön syntaksit"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31810,12 +31808,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Huipputason lausekkeet\n"
"\n"

13
translation/pofiles/fr.po
View File

@ -2,7 +2,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 10:31+0100\n"
"Last-Translator: \n"
"Language-Team: jp-charras\n"
@ -15602,8 +15602,7 @@ msgid "Invalid Ramp"
msgstr "Rampe invalide"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Vérification de l'Entête..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31814,6 +31813,7 @@ msgid "Check rule syntax"
msgstr "Vérification de la syntaxe de la règle"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -32135,12 +32135,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Top-level Clauses\n"
"\n"

11
translation/pofiles/hu.po
View File

@ -4,7 +4,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2022-04-25 17:47+0000\n"
"Last-Translator: Miklós Márton <martonmiklosqdev@gmail.com>\n"
"Language-Team: Hungarian <https://hosted.weblate.org/projects/kicad/master-"
@ -16023,7 +16023,7 @@ msgstr "Érvénytelen jel név"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Zóna kitöltések ellenőrzése...\n"
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -33336,12 +33336,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/id.po
View File

@ -7,7 +7,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2022-12-17 19:13+0000\n"
"Last-Translator: Neko Nekowazarashi <kodra@nekoweb.my.id>\n"
"Language-Team: Indonesian <https://hosted.weblate.org/projects/kicad/master-"
@ -15800,7 +15800,7 @@ msgstr "Nama berkas tidak valid: %s"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Memeriksa permasalahan simbol pustaka..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32800,12 +32800,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

13
translation/pofiles/it.po
View File

@ -109,7 +109,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-31 15:39+0100\n"
"Last-Translator: Marco Ciampa <ciampix@posteo.net>\n"
"Language-Team: Italian <https://hosted.weblate.org/projects/kicad/master-"
@ -15588,8 +15588,7 @@ msgid "Invalid Ramp"
msgstr "Rampa non valida"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Controllo intestazione..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31674,7 +31673,6 @@ msgid "Check rule syntax"
msgstr "Controlla la sintassi regole"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31996,12 +31994,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Proposizioni di primo livello\n"
"\n"

13
translation/pofiles/ja.po
View File

@ -9,7 +9,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-07 01:13+0000\n"
"Last-Translator: Tokita, Hiroshi <tokita.hiroshi@fujitsu.com>\n"
"Language-Team: Japanese <https://hosted.weblate.org/projects/kicad/master-"
@ -15390,8 +15390,7 @@ msgid "Invalid Ramp"
msgstr "不正な Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "ヘッダーをチェック中..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31371,7 +31370,6 @@ msgid "Check rule syntax"
msgstr "ルールの文法をチェック"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31693,12 +31691,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### トップレベルの句\n"
"\n"

13
translation/pofiles/ko.po
View File

@ -27,7 +27,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-04 10:00+0000\n"
"Last-Translator: 김랑기 <korearf@gmail.com>\n"
"Language-Team: Korean <https://hosted.weblate.org/projects/kicad/master-"
@ -15308,8 +15308,7 @@ msgid "Invalid Ramp"
msgstr "잘못된 Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "헤더 확인 중..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31197,7 +31196,6 @@ msgid "Check rule syntax"
msgstr "규칙 문법을 체크"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31519,12 +31517,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### 최상위 조항\n"
"\n"

11
translation/pofiles/lt.po
View File

@ -7,7 +7,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad 4.0\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-20 06:51+0000\n"
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
"Language-Team: Lithuanian <https://hosted.weblate.org/projects/kicad/master-"
@ -15818,7 +15818,7 @@ msgstr "Neteisinga"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Tikrinami kaiščiai ..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32791,12 +32791,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/lv.po
View File

@ -5,7 +5,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad 6.0\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-20 06:51+0000\n"
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
"Language-Team: Latvian <https://hosted.weblate.org/projects/kicad/master-"
@ -15228,7 +15228,7 @@ msgstr "Pagriešana"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Izveidot zonas"
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31471,12 +31471,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/nl.po
View File

@ -10,7 +10,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-01 03:03+0000\n"
"Last-Translator: Christiaan Nieuwlaat <krizzje@gmail.com>\n"
"Language-Team: Dutch <https://hosted.weblate.org/projects/kicad/master-"
@ -15589,7 +15589,7 @@ msgstr "Ongeldig"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Controleer pad's..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32331,12 +32331,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/no.po
View File

@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: 5.99\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-20 06:51+0000\n"
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
"Language-Team: Norwegian Bokmål <https://hosted.weblate.org/projects/kicad/"
@ -15840,7 +15840,7 @@ msgstr "Ugyldig"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Kontrollere pinner ..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32790,12 +32790,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

13
translation/pofiles/pl.po
View File

@ -10,7 +10,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 07:25+0000\n"
"Last-Translator: Mark Roszko <mark.roszko@gmail.com>\n"
"Language-Team: Polish <https://hosted.weblate.org/projects/kicad/master-"
@ -15512,8 +15512,7 @@ msgid "Invalid Ramp"
msgstr "Niepoprawny Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Sprawdzam nagłówek..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31628,7 +31627,6 @@ msgid "Check rule syntax"
msgstr "Sprawdź składnię reguł"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31950,12 +31948,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Klauzule najwyższego poziomu\n"
"\n"

12
translation/pofiles/pt.po
View File

@ -11,7 +11,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2022-10-24 14:09+0000\n"
"Last-Translator: ssantos <ssantos@web.de>\n"
"Language-Team: Portuguese <https://hosted.weblate.org/projects/kicad/master-"
@ -15493,8 +15493,7 @@ msgid "Invalid Ramp"
msgstr "Rampa inválida"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Verificando o cabeçalho..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32008,12 +32007,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Clausulas do primeiro nível\n"
"\n"

13
translation/pofiles/pt_br.po
View File

@ -10,7 +10,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-30 16:44+0000\n"
"Last-Translator: Wellington Terumi Uemura <wellingtonuemura@gmail.com>\n"
"Language-Team: Portuguese (Brazil) <https://hosted.weblate.org/projects/"
@ -15578,8 +15578,7 @@ msgid "Invalid Ramp"
msgstr "Rampa inválida"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Verificando o cabeçalho..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31734,7 +31733,6 @@ msgid "Check rule syntax"
msgstr "Verifique a sintaxe da regra"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -32056,12 +32054,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Clausulas do primeiro nível\n"
"\n"

11
translation/pofiles/ro.po
View File

@ -5,7 +5,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-20 06:51+0000\n"
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
"Language-Team: Romanian <https://hosted.weblate.org/projects/kicad/master-"
@ -15738,7 +15738,7 @@ msgstr "Nevalabil"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Se verifică etichetele..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32834,12 +32834,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Clauze de nivel superior\n"
"\n"

13
translation/pofiles/ru.po
View File

@ -13,7 +13,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-04 10:00+0000\n"
"Last-Translator: dsa-t <dudesuchamazing@gmail.com>\n"
"Language-Team: Russian <https://hosted.weblate.org/projects/kicad/master-"
@ -15418,8 +15418,7 @@ msgid "Invalid Ramp"
msgstr "Недопустимый Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Проверка заголовка..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31486,7 +31485,6 @@ msgid "Check rule syntax"
msgstr "Проверить синтаксис правил"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31808,12 +31806,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Определения верхнего уровня\n"
"\n"

11
translation/pofiles/sk.po
View File

@ -6,7 +6,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-25 00:33+0000\n"
"Last-Translator: Jakub Janek <shaman.janek@gmail.com>\n"
"Language-Team: Slovak <https://hosted.weblate.org/projects/kicad/master-"
@ -15733,7 +15733,7 @@ msgstr "Neplatný"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Kontrolujú sa kolíky ..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32640,12 +32640,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/sl.po
View File

@ -7,7 +7,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2022-12-07 22:47+0000\n"
"Last-Translator: Sašo Domadenik <saso.doma@gmail.com>\n"
"Language-Team: Slovenian <https://hosted.weblate.org/projects/kicad/master-"
@ -17601,7 +17601,7 @@ msgstr "Neveljavno"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Preverjanje zatičev ..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -36570,12 +36570,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

11
translation/pofiles/sr.po
View File

@ -4,7 +4,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-29 22:21+0000\n"
"Last-Translator: ___davidpr <david.pribic95@gmail.com>\n"
"Language-Team: Serbian <https://hosted.weblate.org/projects/kicad/master-"
@ -16008,7 +16008,7 @@ msgstr "Попуњавање зона"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Попуњавање зона"
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -33320,12 +33320,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

13
translation/pofiles/sv.po
View File

@ -9,7 +9,7 @@ msgid ""
msgstr ""
"Project-Id-Version: \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-30 07:26+0000\n"
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
"Language-Team: Swedish <https://hosted.weblate.org/projects/kicad/master-"
@ -15423,8 +15423,7 @@ msgid "Invalid Ramp"
msgstr "Ogiltig ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Kontrollerar header..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31469,7 +31468,6 @@ msgid "Check rule syntax"
msgstr "Kontrollera regelsyntax"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31791,12 +31789,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Toppnivåsatser\n"
"\n"

11
translation/pofiles/th.po
View File

@ -3,7 +3,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-28 22:14+0000\n"
"Last-Translator: boonchai k. <kicadthai@gmail.com>\n"
"Language-Team: Thai <https://hosted.weblate.org/projects/kicad/master-source/"
@ -15165,7 +15165,7 @@ msgstr "ไม่ถูกต้อง"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "กำลังตรวจสอบแพ็ด..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31490,12 +31490,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Top-level Clauses\n"
"\n"

11
translation/pofiles/tr.po
View File

@ -13,7 +13,7 @@ msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-20 06:51+0000\n"
"Last-Translator: Mustafa Selçuk ÇAVDAR <mselcuk@gmail.com>\n"
"Language-Team: Turkish <https://hosted.weblate.org/projects/kicad/master-"
@ -15264,7 +15264,7 @@ msgstr "Geçersiz"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Etiketler kontrol ediliyor..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -32237,12 +32237,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Üst Düzey Yan tümceler\n"
"\n"

13
translation/pofiles/uk.po
View File

@ -7,7 +7,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-01-30 07:26+0000\n"
"Last-Translator: Ivan Chuba <xtrvweb@gmail.com>\n"
"Language-Team: Ukrainian <https://hosted.weblate.org/projects/kicad/master-"
@ -15402,8 +15402,7 @@ msgid "Invalid Ramp"
msgstr "Некоректний Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Перевірка заголовку..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -31482,7 +31481,6 @@ msgid "Check rule syntax"
msgstr "Перевірити синтаксис правил"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31804,12 +31802,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Застереження верхнього рівня\n"
"\n"

11
translation/pofiles/vi.po
View File

@ -5,7 +5,7 @@ msgid ""
msgstr ""
"Project-Id-Version: Kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2022-11-26 09:53+0000\n"
"Last-Translator: Bế Trọng Nghĩa <benghia1st@gmail.com>\n"
"Language-Team: Vietnamese <https://hosted.weblate.org/projects/kicad/master-"
@ -16043,7 +16043,7 @@ msgstr "Tên tín hiệu không hợp lệ"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "Đang kiểm tra nhãn..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -33385,12 +33385,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
#: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75

13
translation/pofiles/zh_CN.po
View File

@ -24,7 +24,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 07:25+0000\n"
"Last-Translator: taotieren <admin@taotieren.com>\n"
"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
@ -15136,8 +15136,7 @@ msgid "Invalid Ramp"
msgstr "无效 Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "正在检查 Header..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -30850,7 +30849,6 @@ msgid "Check rule syntax"
msgstr "检查规则语法"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31172,12 +31170,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Top-level Clauses\n"
"### 顶层语句\n"

13
translation/pofiles/zh_TW.po
View File

@ -9,7 +9,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2023-02-10 14:35-0800\n"
"POT-Creation-Date: 2023-02-10 15:35-0800\n"
"PO-Revision-Date: 2023-02-06 07:25+0000\n"
"Last-Translator: taotieren <admin@taotieren.com>\n"
"Language-Team: Chinese (Traditional) <https://hosted.weblate.org/projects/"
@ -15120,8 +15120,7 @@ msgid "Invalid Ramp"
msgstr "無效 Ramp"
#: eeschema/sim/kibis/ibis_parser.cpp:613
#, fuzzy
msgid "Checking Header... "
msgid "Checking Header..."
msgstr "正在檢查 Header..."
#: eeschema/sim/kibis/ibis_parser.cpp:620
@ -30831,7 +30830,6 @@ msgid "Check rule syntax"
msgstr "檢查規則語法"
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
#, fuzzy
msgid ""
"### Top-level Clauses\n"
"\n"
@ -31153,12 +31151,7 @@ msgid ""
" (rule high-current\n"
" (constraint track_width (min 1.0mm))\n"
" (constraint connection_width (min 0.8mm))\n"
" (condition \"A.NetClass == 'Power'\"))\n"
"\n"
"### Documentation\n"
"\n"
"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)."
" (condition \"A.NetClass == 'Power'\"))"
msgstr ""
"### Top-level Clauses\n"
"### 頂層語句\n"