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Fix bug in IDF export (plus minor cleaning up of IDF/VRML export)

This commit is contained in:
unknown 2014-11-13 12:29:05 +01:00 committed by jean-pierre charras
parent d84567ae40
commit d54675b56b
3 changed files with 10 additions and 6 deletions
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3
pcbnew/exporters/export_idf.cpp
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@ -443,6 +443,9 @@ static void idf_export_module( BOARD* aPcb, MODULE* aModule,
comp->SetPosition( aModule->GetPosition().x * scale + dx, comp->SetPosition( aModule->GetPosition().x * scale + dx,
-aModule->GetPosition().y * scale + dy, -aModule->GetPosition().y * scale + dy,
rotz, IDF3::LYR_BOTTOM ); rotz, IDF3::LYR_BOTTOM );
comp->SetPlacement( IDF3::PS_ECAD );
} }
else else
{ {

3
utils/idftools/idf_parser.cpp
View File

@ -728,7 +728,8 @@ void IDF3_COMP_OUTLINE_DATA::writePlaceData( std::ofstream& aBoardFile,
if( aPlacement == PS_INVALID ) if( aPlacement == PS_INVALID )
{ {
ERROR_IDF << "placement invalid; defaulting to PLACED\n"; ERROR_IDF << "placement invalid (" << aRefDes << ":";
std::cerr << aPlacement << "); defaulting to PLACED\n";
aPlacement = PS_PLACED; aPlacement = PS_PLACED;
} }

2
utils/idftools/vrml_layer.cpp
View File

@ -30,7 +30,7 @@
// a closed loop as assumed for all other outlines. // a closed loop as assumed for all other outlines.
// 3. a scheme is needed to tell a castellated edge from a plain board edge // 3. a scheme is needed to tell a castellated edge from a plain board edge
#include <iostream>
#include <sstream> #include <sstream>
#include <string> #include <string>
#include <iomanip> #include <iomanip>