haskal
/
kicad
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix various compiler and Coverity warnings

This commit is contained in:
Ian McInerney 2020-11-11 00:18:35 +00:00
parent 11e6cac42b
commit d88eaaf477
7 changed files with 67 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
common/widgets/widget_hotkey_list.cpp
View File

@ -136,7 +136,32 @@ public:
}
void OnCharHook( wxKeyEvent& aEvent )
/**
* End the dialog whether modal or quasimodal
*/
void EndFlexible( int aRtnCode )
{
if( IsQuasiModal() )
EndQuasiModal( aRtnCode );
else
EndModal( aRtnCode );
}
static wxKeyEvent PromptForKey( wxWindow* aParent, const wxString& aName,
const wxString& aCurrentKey )
{
HK_PROMPT_DIALOG dialog( aParent, wxID_ANY, _( "Set Hotkey" ), aName, aCurrentKey );
if( dialog.ShowModal() == wxID_OK )
return dialog.m_event;
else
return wxKeyEvent();
}
protected:
void OnCharHook( wxKeyEvent& aEvent ) override
{
// On certain platforms, EVT_CHAR_HOOK is the only handler that receives
// certain "special" keys. However, it doesn't always receive "normal"
@ -184,30 +209,6 @@ public:
m_event = aEvent;
EndFlexible( wxID_OK );
}
/**
* End the dialog whether modal or quasimodal
*/
void EndFlexible( int aRtnCode )
{
if( IsQuasiModal() )
EndQuasiModal( aRtnCode );
else
EndModal( aRtnCode );
}
static wxKeyEvent PromptForKey( wxWindow* aParent, const wxString& aName,
const wxString& aCurrentKey )
{
HK_PROMPT_DIALOG dialog( aParent, wxID_ANY, _( "Set Hotkey" ), aName, aCurrentKey );
if( dialog.ShowModal() == wxID_OK )
return dialog.m_event;
else
return wxKeyEvent();
}
};

5
eeschema/schematic_settings.cpp
View File

@ -41,6 +41,7 @@ SCHEMATIC_SETTINGS::SCHEMATIC_SETTINGS( JSON_SETTINGS* aParent, const std::strin
m_TextOffsetRatio( 0.08 ),
m_PinSymbolSize( DEFAULT_TEXT_SIZE * IU_PER_MILS / 2 ),
m_JunctionSize( DEFAULT_JUNCTION_DIAM * IU_PER_MILS ),
m_JunctionSizeChoice( 3 ),
m_IntersheetsRefShow( false ),
m_IntersheetsRefFormatShort( false ),
m_IntersheetsRefPrefix( DEFAULT_IREF_PREFIX ),
@ -62,7 +63,7 @@ SCHEMATIC_SETTINGS::SCHEMATIC_SETTINGS( JSON_SETTINGS* aParent, const std::strin
int defaultJunctionSize =
appSettings ? appSettings->m_Drawing.default_junction_size : DEFAULT_JUNCTION_DIAM;
int defaultJunctionSizeChoice =
appSettings ? appSettings->m_Drawing.junction_size_choice : 3;
appSettings ? appSettings->m_Drawing.junction_size_choice : 3;
bool defaultIntersheetsRefShow =
appSettings ? appSettings->m_Drawing.intersheets_ref_show : false;
bool defaultIntersheetsRefFormatShort =
@ -114,7 +115,7 @@ SCHEMATIC_SETTINGS::SCHEMATIC_SETTINGS( JSON_SETTINGS* aParent, const std::strin
&m_JunctionSize,
Mils2iu( defaultJunctionSize ), Mils2iu( 5 ), Mils2iu( 1000 ), 1 / IU_PER_MILS ) );
// User choice for junction dot size ( e.g. none = 0, smallest = 1, small = 2, etc )
// User choice for junction dot size ( e.g. none = 0, smallest = 1, small = 2, etc )
m_params.emplace_back(new PARAM<int>("drawing.junction_size_choice",
&m_JunctionSizeChoice,
defaultJunctionSizeChoice) );

4
pcbnew/dialogs/dialog_select_net_from_list.cpp
View File

@ -1454,7 +1454,9 @@ std::unique_ptr<DIALOG_SELECT_NET_FROM_LIST::LIST_ITEM> DIALOG_SELECT_NET_FROM_L
void DIALOG_SELECT_NET_FROM_LIST::buildNetsList()
{
wxCHECK( m_brd, /* void */ );
// Only build the list of nets if there is a board present
if( !m_brd )
return;
m_in_build_nets_list = true;

58
pcbnew/drc/drc_engine.cpp
View File

@ -208,25 +208,25 @@ void DRC_ENGINE::loadImplicitRules()
{
wxString ncName = nc->GetName();
DRC_RULE* rule;
DRC_RULE* netclassRule;
wxString expr;
if( nc->GetClearance() || nc->GetTrackWidth() )
{
rule = new DRC_RULE;
rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
rule->m_Implicit = true;
netclassRule = new DRC_RULE;
netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
netclassRule->m_Implicit = true;
expr = wxString::Format( "A.NetClass == '%s'",
ncName );
rule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassClearanceRules.push_back( rule );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassClearanceRules.push_back( netclassRule );
if( nc->GetClearance() )
{
DRC_CONSTRAINT constraint( CLEARANCE_CONSTRAINT );
constraint.Value().SetMin( std::max( bds.m_MinClearance, nc->GetClearance() ) );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
if( nc->GetTrackWidth() )
@ -234,27 +234,27 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
constraint.Value().SetMin( bds.m_TrackMinWidth );
constraint.Value().SetOpt( nc->GetTrackWidth() );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
}
if( nc->GetDiffPairWidth() || nc->GetDiffPairGap() )
{
rule = new DRC_RULE;
rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
rule->m_Implicit = true;
netclassRule = new DRC_RULE;
netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
netclassRule->m_Implicit = true;
expr = wxString::Format( "A.NetClass == '%s' && A.isDiffPair()",
ncName );
rule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( rule );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
if( nc->GetDiffPairWidth() )
{
DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
constraint.Value().SetMin( bds.m_TrackMinWidth );
constraint.Value().SetOpt( nc->GetDiffPairWidth() );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
if( nc->GetDiffPairGap() )
@ -262,27 +262,27 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT constraint( DIFF_PAIR_GAP_CONSTRAINT );
constraint.Value().SetMin( std::max( bds.m_MinClearance, nc->GetClearance() ) );
constraint.Value().SetOpt( nc->GetDiffPairGap() );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
}
if( nc->GetViaDiameter() || nc->GetViaDrill() )
{
rule = new DRC_RULE;
rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
rule->m_Implicit = true;
netclassRule = new DRC_RULE;
netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
netclassRule->m_Implicit = true;
expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type != 'Micro'",
ncName );
rule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( rule );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
if( nc->GetViaDiameter() )
{
DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
constraint.Value().SetMin( bds.m_ViasMinSize );
constraint.Value().SetOpt( nc->GetViaDiameter() );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
if( nc->GetViaDrill() )
@ -290,27 +290,27 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
constraint.Value().SetMin( bds.m_MinThroughDrill );
constraint.Value().SetOpt( nc->GetViaDrill() );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
}
if( nc->GetuViaDiameter() || nc->GetuViaDrill() )
{
rule = new DRC_RULE;
rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
rule->m_Implicit = true;
netclassRule = new DRC_RULE;
netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
netclassRule->m_Implicit = true;
expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type == 'Micro'",
ncName );
rule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( rule );
netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
netclassItemSpecificRules.push_back( netclassRule );
if( nc->GetuViaDiameter() )
{
DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
constraint.Value().SetMin( bds.m_MicroViasMinSize );
constraint.Value().SetMin( nc->GetuViaDiameter() );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
if( nc->GetuViaDrill() )
@ -318,7 +318,7 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
constraint.Value().SetMin( bds.m_MicroViasMinDrill );
constraint.Value().SetOpt( nc->GetuViaDrill() );
rule->AddConstraint( constraint );
netclassRule->AddConstraint( constraint );
}
}
};

2
pcbnew/router/pns_kicad_iface.cpp
View File

@ -224,7 +224,7 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType,
DRC_CONSTRAINT hostConstraint;
// A track being routed may not have a BOARD_ITEM associated yet.
if( !parentA )
if( aItemA && !parentA )
{
switch( aItemA->Kind() )
{

4
pcbnew/undo_redo.cpp
View File

@ -503,7 +503,9 @@ void PCB_BASE_EDIT_FRAME::PutDataInPreviousState( PICKED_ITEMS_LIST* aList, bool
break;
case UNDO_REDO::UNGROUP:
group->AddItem( static_cast<BOARD_ITEM*>( eda_item ) );
if( group )
group->AddItem( static_cast<BOARD_ITEM*>( eda_item ) );
break;
case UNDO_REDO::MOVED:

4
pcbnew/zone_filler.cpp
View File

@ -683,9 +683,9 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
auto evalRulesForItems =
[&bds]( DRC_CONSTRAINT_TYPE_T aConstraint, const BOARD_ITEM* a, const BOARD_ITEM* b,
PCB_LAYER_ID aLayer ) -> int
PCB_LAYER_ID aEvalLayer ) -> int
{
DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aLayer );
DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aEvalLayer );
return c.Value().HasMin() ? c.Value().Min() : 0;
};