Fix various compiler and Coverity warnings
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parent
11e6cac42b
commit
d88eaaf477
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@ -136,7 +136,32 @@ public:
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}
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void OnCharHook( wxKeyEvent& aEvent )
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/**
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* End the dialog whether modal or quasimodal
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*/
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void EndFlexible( int aRtnCode )
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{
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if( IsQuasiModal() )
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EndQuasiModal( aRtnCode );
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else
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EndModal( aRtnCode );
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}
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static wxKeyEvent PromptForKey( wxWindow* aParent, const wxString& aName,
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const wxString& aCurrentKey )
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{
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HK_PROMPT_DIALOG dialog( aParent, wxID_ANY, _( "Set Hotkey" ), aName, aCurrentKey );
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if( dialog.ShowModal() == wxID_OK )
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return dialog.m_event;
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else
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return wxKeyEvent();
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}
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protected:
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void OnCharHook( wxKeyEvent& aEvent ) override
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{
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// On certain platforms, EVT_CHAR_HOOK is the only handler that receives
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// certain "special" keys. However, it doesn't always receive "normal"
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@ -184,30 +209,6 @@ public:
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m_event = aEvent;
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EndFlexible( wxID_OK );
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}
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/**
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* End the dialog whether modal or quasimodal
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*/
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void EndFlexible( int aRtnCode )
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{
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if( IsQuasiModal() )
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EndQuasiModal( aRtnCode );
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else
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EndModal( aRtnCode );
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}
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static wxKeyEvent PromptForKey( wxWindow* aParent, const wxString& aName,
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const wxString& aCurrentKey )
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{
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HK_PROMPT_DIALOG dialog( aParent, wxID_ANY, _( "Set Hotkey" ), aName, aCurrentKey );
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if( dialog.ShowModal() == wxID_OK )
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return dialog.m_event;
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else
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return wxKeyEvent();
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}
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};
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@ -41,6 +41,7 @@ SCHEMATIC_SETTINGS::SCHEMATIC_SETTINGS( JSON_SETTINGS* aParent, const std::strin
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m_TextOffsetRatio( 0.08 ),
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m_PinSymbolSize( DEFAULT_TEXT_SIZE * IU_PER_MILS / 2 ),
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m_JunctionSize( DEFAULT_JUNCTION_DIAM * IU_PER_MILS ),
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m_JunctionSizeChoice( 3 ),
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m_IntersheetsRefShow( false ),
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m_IntersheetsRefFormatShort( false ),
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m_IntersheetsRefPrefix( DEFAULT_IREF_PREFIX ),
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@ -1454,7 +1454,9 @@ std::unique_ptr<DIALOG_SELECT_NET_FROM_LIST::LIST_ITEM> DIALOG_SELECT_NET_FROM_L
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void DIALOG_SELECT_NET_FROM_LIST::buildNetsList()
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{
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wxCHECK( m_brd, /* void */ );
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// Only build the list of nets if there is a board present
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if( !m_brd )
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return;
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m_in_build_nets_list = true;
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@ -208,25 +208,25 @@ void DRC_ENGINE::loadImplicitRules()
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{
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wxString ncName = nc->GetName();
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DRC_RULE* rule;
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DRC_RULE* netclassRule;
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wxString expr;
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if( nc->GetClearance() || nc->GetTrackWidth() )
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{
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rule = new DRC_RULE;
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rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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rule->m_Implicit = true;
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netclassRule = new DRC_RULE;
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netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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netclassRule->m_Implicit = true;
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expr = wxString::Format( "A.NetClass == '%s'",
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ncName );
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rule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassClearanceRules.push_back( rule );
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netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassClearanceRules.push_back( netclassRule );
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if( nc->GetClearance() )
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{
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DRC_CONSTRAINT constraint( CLEARANCE_CONSTRAINT );
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constraint.Value().SetMin( std::max( bds.m_MinClearance, nc->GetClearance() ) );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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if( nc->GetTrackWidth() )
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@ -234,27 +234,27 @@ void DRC_ENGINE::loadImplicitRules()
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DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
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constraint.Value().SetMin( bds.m_TrackMinWidth );
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constraint.Value().SetOpt( nc->GetTrackWidth() );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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}
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if( nc->GetDiffPairWidth() || nc->GetDiffPairGap() )
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{
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rule = new DRC_RULE;
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rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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rule->m_Implicit = true;
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netclassRule = new DRC_RULE;
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netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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netclassRule->m_Implicit = true;
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expr = wxString::Format( "A.NetClass == '%s' && A.isDiffPair()",
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ncName );
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rule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassItemSpecificRules.push_back( rule );
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netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassItemSpecificRules.push_back( netclassRule );
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if( nc->GetDiffPairWidth() )
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{
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DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
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constraint.Value().SetMin( bds.m_TrackMinWidth );
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constraint.Value().SetOpt( nc->GetDiffPairWidth() );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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if( nc->GetDiffPairGap() )
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@ -262,27 +262,27 @@ void DRC_ENGINE::loadImplicitRules()
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DRC_CONSTRAINT constraint( DIFF_PAIR_GAP_CONSTRAINT );
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constraint.Value().SetMin( std::max( bds.m_MinClearance, nc->GetClearance() ) );
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constraint.Value().SetOpt( nc->GetDiffPairGap() );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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}
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if( nc->GetViaDiameter() || nc->GetViaDrill() )
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{
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rule = new DRC_RULE;
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rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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rule->m_Implicit = true;
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netclassRule = new DRC_RULE;
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netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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netclassRule->m_Implicit = true;
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expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type != 'Micro'",
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ncName );
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rule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassItemSpecificRules.push_back( rule );
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netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassItemSpecificRules.push_back( netclassRule );
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if( nc->GetViaDiameter() )
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{
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DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
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constraint.Value().SetMin( bds.m_ViasMinSize );
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constraint.Value().SetOpt( nc->GetViaDiameter() );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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if( nc->GetViaDrill() )
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@ -290,27 +290,27 @@ void DRC_ENGINE::loadImplicitRules()
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DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
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constraint.Value().SetMin( bds.m_MinThroughDrill );
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constraint.Value().SetOpt( nc->GetViaDrill() );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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}
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if( nc->GetuViaDiameter() || nc->GetuViaDrill() )
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{
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rule = new DRC_RULE;
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rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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rule->m_Implicit = true;
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netclassRule = new DRC_RULE;
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netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName );
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netclassRule->m_Implicit = true;
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expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type == 'Micro'",
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ncName );
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rule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassItemSpecificRules.push_back( rule );
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netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
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netclassItemSpecificRules.push_back( netclassRule );
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if( nc->GetuViaDiameter() )
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{
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DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
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constraint.Value().SetMin( bds.m_MicroViasMinSize );
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constraint.Value().SetMin( nc->GetuViaDiameter() );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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if( nc->GetuViaDrill() )
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@ -318,7 +318,7 @@ void DRC_ENGINE::loadImplicitRules()
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DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
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constraint.Value().SetMin( bds.m_MicroViasMinDrill );
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constraint.Value().SetOpt( nc->GetuViaDrill() );
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rule->AddConstraint( constraint );
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netclassRule->AddConstraint( constraint );
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}
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}
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};
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@ -224,7 +224,7 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType,
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DRC_CONSTRAINT hostConstraint;
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// A track being routed may not have a BOARD_ITEM associated yet.
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if( !parentA )
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if( aItemA && !parentA )
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{
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switch( aItemA->Kind() )
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{
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@ -503,7 +503,9 @@ void PCB_BASE_EDIT_FRAME::PutDataInPreviousState( PICKED_ITEMS_LIST* aList, bool
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break;
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case UNDO_REDO::UNGROUP:
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if( group )
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group->AddItem( static_cast<BOARD_ITEM*>( eda_item ) );
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break;
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case UNDO_REDO::MOVED:
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@ -683,9 +683,9 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
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auto evalRulesForItems =
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[&bds]( DRC_CONSTRAINT_TYPE_T aConstraint, const BOARD_ITEM* a, const BOARD_ITEM* b,
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PCB_LAYER_ID aLayer ) -> int
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PCB_LAYER_ID aEvalLayer ) -> int
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{
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DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aLayer );
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DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aEvalLayer );
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return c.Value().HasMin() ? c.Value().Min() : 0;
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};
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