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Allow close placement of stitching vias 

When placing a stitching via for a bypass capacitor, it is common to
place it close to the relevant pad.  If the via does not have the
correct net, this will violate DRC and be prevented.

Checking for zone-based net assignments allows the workflow to proceed
This commit is contained in:
Seth Hillbrand 2021-09-01 15:52:35 -07:00
parent f14e5b61b3
commit e03257b55f
1 changed files with 2 additions and 0 deletions
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2
pcbnew/tools/drawing_tool.cpp
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@ -2553,6 +2553,8 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
via->SetNetCode( track->GetNetCode() );
else if( pad )
via->SetNetCode( pad->GetNetCode() );
else
via->SetNetCode( findStitchedZoneNet( via ) );
if( !m_allowDRCViolations && checkDRCViolation( via ) )
{