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Pcbnew: fix some issues when using python scripting (remove outdated SEG_ZONE item, fix broken access to netclass, track width and via size lists, add missing access to zones) 

Update listPcb.py to show how to access zones.
This commit is contained in:
jean-pierre charras 2014-09-30 20:23:27 +02:00
parent 45a8e4da74
commit e617c5e6b1
6 changed files with 70 additions and 59 deletions
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38
pcbnew/scripting/board.i
View File

@ -35,22 +35,11 @@
def GetModules(self): return self.m_Modules
def GetDrawings(self): return self.m_Drawings
def GetTracks(self): return self.m_Track
def GetSegZones(self): return self.m_Zone
def GetFullRatsnest(self): return self.m_FullRatsnest
def GetLocalRatsnest(self): return self.m_LocalRatsnest
def GetNetClasses(self): return self.m_NetClasses
def GetCurrentNetClassName(self): return self.m_CurrentNetClassName
def GetViasDimensionsList(self): return self.m_ViasDimensionsList
def GetTrackWidthList(self): return self.m_TrackWidthList
def GetZones(self): return self.m_ZoneDescriptorList
def Save(self,filename,format = None):
if format is None:
str_filename = str(filename)
if str_filename.endswith(".brd"):
format = IO_MGR.LEGACY
if str_filename.endswith(".kicad_pcb"):
format = IO_MGR.KICAD
return SaveBoard(filename,self,format)
def Save(self,filename):
return SaveBoard(filename,self,IO_MGR.KICAD)
#
# add function, clears the thisown to avoid python from deleting
@ -70,14 +59,12 @@
%rename(Get) operator TRACK*;
%rename(Get) operator D_PAD*;
%rename(Get) operator MODULE*;
%rename(Get) operator SEGZONE*;
// we must translate C++ templates to scripting languages
%template(BOARD_ITEM_List) DLIST<BOARD_ITEM>;
%template(MODULE_List) DLIST<MODULE>;
%template(SEGZONE_List) DLIST<SEGZONE>;
%template(TRACK_List) DLIST<TRACK>;
%template(PAD_List) DLIST<D_PAD>;
@ -86,6 +73,25 @@
%template(VIA_DIMENSION_Vector) std::vector<VIA_DIMENSION>;
%template (RASTNET_Vector) std::vector<RATSNEST_ITEM>;
%extend BOARD
{
%pythoncode
{
def GetNetClasses(self):
return self.GetDesignSettings().m_NetClasses
def GetCurrentNetClassName(self):
return self.GetDesignSettings().m_CurrentNetClassName
def GetViasDimensionsList(self):
return self.GetDesignSettings().m_ViasDimensionsList
def GetTrackWidthList(self):
return self.GetDesignSettings().m_TrackWidthList
}
}
%extend DRAWSEGMENT
{
%pythoncode

28
pcbnew/scripting/board_item.i
View File

@ -37,18 +37,18 @@
%extend BOARD_ITEM
{
TEXTE_PCB* Cast_to_TEXTE_PCB() { return dynamic_cast<TEXTE_PCB*>(self); }
DIMENSION* Cast_to_DIMENSION() { return dynamic_cast<DIMENSION*>(self); }
MODULE* Cast_to_MODULE() { return dynamic_cast<MODULE*>(self); }
TEXTE_MODULE* Cast_to_TEXTE_MODULE() { return dynamic_cast<TEXTE_MODULE*>(self); }
DRAWSEGMENT* Cast_to_DRAWSEGMENT() { return dynamic_cast<DRAWSEGMENT*>(self); }
MARKER_PCB* Cast_to_MARKER_PCB() { return dynamic_cast<MARKER_PCB*>(self); }
BOARD* Cast_to_BOARD() { return dynamic_cast<BOARD*>(self); }
EDGE_MODULE* Cast_to_EDGE_MODULE() { return dynamic_cast<EDGE_MODULE*>(self); }
D_PAD* Cast_to_D_PAD() { return dynamic_cast<D_PAD*>(self); }
TRACK* Cast_to_TRACK() { return dynamic_cast<TRACK*>(self); }
SEGZONE* Cast_to_SEGZONE() { return dynamic_cast<SEGZONE*>(self); }
VIA* Cast_to_VIA() { return dynamic_cast<VIA*>(self); }
TEXTE_PCB* Cast_to_TEXTE_PCB() { return dynamic_cast<TEXTE_PCB*>(self); }
DIMENSION* Cast_to_DIMENSION() { return dynamic_cast<DIMENSION*>(self); }
MODULE* Cast_to_MODULE() { return dynamic_cast<MODULE*>(self); }
TEXTE_MODULE* Cast_to_TEXTE_MODULE() { return dynamic_cast<TEXTE_MODULE*>(self); }
DRAWSEGMENT* Cast_to_DRAWSEGMENT() { return dynamic_cast<DRAWSEGMENT*>(self); }
MARKER_PCB* Cast_to_MARKER_PCB() { return dynamic_cast<MARKER_PCB*>(self); }
BOARD* Cast_to_BOARD() { return dynamic_cast<BOARD*>(self); }
EDGE_MODULE* Cast_to_EDGE_MODULE() { return dynamic_cast<EDGE_MODULE*>(self); }
D_PAD* Cast_to_D_PAD() { return dynamic_cast<D_PAD*>(self); }
TRACK* Cast_to_TRACK() { return dynamic_cast<TRACK*>(self); }
ZONE_CONTAINER* Cast_to_ZONE_CONTAINER() { return dynamic_cast<ZONE_CONTAINER*>(self);}
VIA* Cast_to_VIA() { return dynamic_cast<VIA*>(self); }
%pythoncode
@ -73,12 +73,12 @@
return self.Cast_to_D_PAD()
elif ct=="MTEXT":
return self.Cast_to_TEXTE_MODULE()
elif ct=="ZONE":
return self.Cast_to_SEGZONE()
elif ct=="VIA":
return self.Cast_to_VIA()
elif ct=="TRACK":
return self.Cast_to_TRACK()
elif ct=="ZONE_CONTAINER":
return self.Cast_to_ZONE_CONTAINER()
else:
return None
}

47
pcbnew/scripting/examples/listPcb.py
View File

@ -6,34 +6,34 @@ filename=sys.argv[1]
pcb = LoadBoard(filename)
#ToUnits = ToMM
#FromUnits = FromMM
ToUnits=ToMils
FromUnits=FromMils
ToUnits = ToMM
FromUnits = FromMM
#ToUnits=ToMils
#FromUnits=FromMils
print "LISTING VIAS:"
for item in pcb.GetTracks():
if type(item) is SEGVIA:
if type(item) is VIA:
pos = item.GetPosition()
drill = item.GetDrillValue()
width = item.GetWidth()
print " * Via: %s - %f/%f "%(ToUnits(pos),ToUnits(drill),ToUnits(width))
elif type(item) is TRACK:
start = item.GetStart()
end = item.GetEnd()
width = item.GetWidth()
print " * Track: %s to %s, width %f" % (ToUnits(start),ToUnits(end),ToUnits(width))
else:
print "Unknown type %s" % type(item)
print ""
print "LISTING DRAWINGS:"
print "LIST DRAWINGS:"
for item in pcb.GetDrawings():
if type(item) is TEXTE_PCB:
@ -42,22 +42,25 @@ for item in pcb.GetDrawings():
print "* Drawing: %s"%item.GetShapeStr() # dir(item)
else:
print type(item)
print ""
print "LIST MODULES:"
for module in pcb.GetModules():
print "* Module: %s at %s"%(module.GetReference(),ToUnits(module.GetPosition()))
print ""
print ""
print "Ratsnest cnt:",len(pcb.GetFullRatsnest())
print "track w cnt:",len(pcb.GetTrackWidthList())
print "via s cnt:",len(pcb.GetViasDimensionsList())
print ""
print "LIST ZONES:"
for zone in pcb.GetSegZones():
print zone
print ""
print "RATSNEST:",len(pcb.GetFullRatsnest())
for idx in range(0, pcb.GetAreaCount()):
zone=pcb.GetArea(idx)
print "zone:", idx, "priority:", zone.GetPriority(), "netname", zone.GetNetname()
print ""
print "NetClasses:", pcb.GetNetClasses().GetCount()
print dir(pcb.GetNetClasses())

2
pcbnew/scripting/pcbnew.i
View File

@ -88,6 +88,7 @@
#include <class_board.h>
#include <class_module.h>
#include <class_track.h>
#include <class_zone.h>
#include <layers_id_colors_and_visibility.h>
#include <class_pad.h>
#include <pad_shapes.h>
@ -123,6 +124,7 @@
%include <class_board.h>
%include <class_module.h>
%include <class_track.h>
%include <class_zone.h>
%include <layers_id_colors_and_visibility.h>
%include <class_pad.h>
%include <pad_shapes.h>

2
pcbnew/scripting/units.i
View File

@ -27,7 +27,7 @@
* @brief unit conversion code
*/
// Unit conversion, between internal
// Unit conversion, between internal units and mm or mils
%pythoncode
{

12
pcbnew/tracepcb.cpp
View File

@ -255,14 +255,14 @@ void BOARD::DrawHighLight( EDA_DRAW_PANEL* am_canvas, wxDC* DC, int aNetCode )
else
draw_mode = GR_AND | GR_HIGHLIGHT;
// Redraw ZONE_CONTAINERS
BOARD::ZONE_CONTAINERS& zones = m_ZoneDescriptorList;
for( BOARD::ZONE_CONTAINERS::iterator zc = zones.begin(); zc!=zones.end(); ++zc )
// Redraw zones
for( int ii = 0; ii < GetAreaCount(); ii++ )
{
if( (*zc)->GetNetCode() == aNetCode )
ZONE_CONTAINER* zone = GetArea( ii );
if( zone->GetNetCode() == aNetCode )
{
(*zc)->Draw( am_canvas, DC, draw_mode );
zone->Draw( am_canvas, DC, draw_mode );
}
}