Board edges have no width.

Fixes https://gitlab.com/kicad/code/kicad/issues/5990
This commit is contained in:
Jeff Young 2020-10-14 11:06:04 +01:00
parent 54dc91a623
commit f220e83de6
2 changed files with 16 additions and 15 deletions

View File

@ -115,8 +115,8 @@ public:
m_ids.push_back( aItem->m_Uuid ); m_ids.push_back( aItem->m_Uuid );
} }
void SetItems( EDA_ITEM* aItem, EDA_ITEM* bItem = nullptr, EDA_ITEM* cItem = nullptr, void SetItems( const EDA_ITEM* aItem, const EDA_ITEM* bItem = nullptr,
EDA_ITEM* dItem = nullptr ) const EDA_ITEM* cItem = nullptr, const EDA_ITEM* dItem = nullptr )
{ {
m_ids.clear(); m_ids.clear();

View File

@ -90,13 +90,14 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
if( !reportPhase( _( "Checking board edge clearances..." ) ) ) if( !reportPhase( _( "Checking board edge clearances..." ) ) )
return false; return false;
std::vector<PCB_SHAPE*> boardOutline; std::vector<PCB_SHAPE> boardOutline;
std::vector<BOARD_ITEM*> boardItems; std::vector<BOARD_ITEM*> boardItems;
auto queryBoardOutlineItems = auto queryBoardOutlineItems =
[&]( BOARD_ITEM *item ) -> bool [&]( BOARD_ITEM *item ) -> bool
{ {
boardOutline.push_back( dyn_cast<PCB_SHAPE*>( item ) ); boardOutline.push_back( dyn_cast<PCB_SHAPE*>( item ) );
boardOutline.back().SetWidth( 0 );
return true; return true;
}; };
@ -116,20 +117,20 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
drc_dbg( 2, "outline: %d items, board: %d items\n", drc_dbg( 2, "outline: %d items, board: %d items\n",
(int) boardOutline.size(), (int) boardItems.size() ); (int) boardOutline.size(), (int) boardItems.size() );
for( PCB_SHAPE* outlineItem : boardOutline ) for( const PCB_SHAPE& outlineItem : boardOutline )
{ {
if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) ) if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) )
break; break;
const std::shared_ptr<SHAPE>& refShape = outlineItem->GetEffectiveShape(); const std::shared_ptr<SHAPE>& refShape = outlineItem.GetEffectiveShape();
for( BOARD_ITEM* boardItem : boardItems ) for( BOARD_ITEM* boardItem : boardItems )
{ {
if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) ) if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) )
break; break;
drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem->Type(), outlineItem, drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem.Type(), &outlineItem,
outlineItem->GetClass(), outlineItem->GetLayer() ); outlineItem.GetClass(), outlineItem.GetLayer() );
drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem, drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem,
boardItem->GetClass(), boardItem->GetLayer() ); boardItem->GetClass(), boardItem->GetLayer() );
@ -139,7 +140,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape(); const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE, auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,
outlineItem, boardItem ); &outlineItem, boardItem );
int minClearance = constraint.GetValue().Min(); int minClearance = constraint.GetValue().Min();
int actual; int actual;
@ -157,7 +158,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
MessageTextFromValue( userUnits(), actual ) ); MessageTextFromValue( userUnits(), actual ) );
drcItem->SetErrorMessage( m_msg ); drcItem->SetErrorMessage( m_msg );
drcItem->SetItems( outlineItem, boardItem ); drcItem->SetItems( &outlineItem, boardItem );
drcItem->SetViolatingRule( constraint.GetParentRule() ); drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, (wxPoint) pos ); reportViolation( drcItem, (wxPoint) pos );
@ -171,20 +172,20 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
boardItems.clear(); boardItems.clear();
forEachGeometryItem( {}, LSET( 2, F_SilkS, B_SilkS ), queryBoardGeometryItems ); forEachGeometryItem( {}, LSET( 2, F_SilkS, B_SilkS ), queryBoardGeometryItems );
for( PCB_SHAPE* outlineItem : boardOutline ) for( const PCB_SHAPE& outlineItem : boardOutline )
{ {
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) ) if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
break; break;
const std::shared_ptr<SHAPE>& refShape = outlineItem->GetEffectiveShape(); const std::shared_ptr<SHAPE>& refShape = outlineItem.GetEffectiveShape();
for( BOARD_ITEM* boardItem : boardItems ) for( BOARD_ITEM* boardItem : boardItems )
{ {
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) ) if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
break; break;
drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem->Type(), outlineItem, drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem.Type(), &outlineItem,
outlineItem->GetClass(), outlineItem->GetLayer() ); outlineItem.GetClass(), outlineItem.GetLayer() );
drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem, drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem,
boardItem->GetClass(), boardItem->GetLayer() ); boardItem->GetClass(), boardItem->GetLayer() );
@ -194,7 +195,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape(); const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE, auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
outlineItem, boardItem ); &outlineItem, boardItem );
int minClearance = constraint.GetValue().Min(); int minClearance = constraint.GetValue().Min();
int actual; int actual;
@ -216,7 +217,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
drcItem->SetErrorMessage( m_msg ); drcItem->SetErrorMessage( m_msg );
} }
drcItem->SetItems( outlineItem, boardItem ); drcItem->SetItems( &outlineItem, boardItem );
drcItem->SetViolatingRule( constraint.GetParentRule() ); drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, (wxPoint) pos ); reportViolation( drcItem, (wxPoint) pos );