Board edges have no width.
Fixes https://gitlab.com/kicad/code/kicad/issues/5990
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54dc91a623
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f220e83de6
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@ -115,8 +115,8 @@ public:
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m_ids.push_back( aItem->m_Uuid );
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}
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void SetItems( EDA_ITEM* aItem, EDA_ITEM* bItem = nullptr, EDA_ITEM* cItem = nullptr,
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EDA_ITEM* dItem = nullptr )
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void SetItems( const EDA_ITEM* aItem, const EDA_ITEM* bItem = nullptr,
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const EDA_ITEM* cItem = nullptr, const EDA_ITEM* dItem = nullptr )
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{
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m_ids.clear();
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@ -90,13 +90,14 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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if( !reportPhase( _( "Checking board edge clearances..." ) ) )
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return false;
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std::vector<PCB_SHAPE*> boardOutline;
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std::vector<PCB_SHAPE> boardOutline;
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std::vector<BOARD_ITEM*> boardItems;
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auto queryBoardOutlineItems =
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[&]( BOARD_ITEM *item ) -> bool
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{
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boardOutline.push_back( dyn_cast<PCB_SHAPE*>( item ) );
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boardOutline.back().SetWidth( 0 );
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return true;
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};
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@ -116,20 +117,20 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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drc_dbg( 2, "outline: %d items, board: %d items\n",
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(int) boardOutline.size(), (int) boardItems.size() );
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for( PCB_SHAPE* outlineItem : boardOutline )
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for( const PCB_SHAPE& outlineItem : boardOutline )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) )
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break;
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const std::shared_ptr<SHAPE>& refShape = outlineItem->GetEffectiveShape();
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const std::shared_ptr<SHAPE>& refShape = outlineItem.GetEffectiveShape();
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for( BOARD_ITEM* boardItem : boardItems )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) )
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break;
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drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem->Type(), outlineItem,
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outlineItem->GetClass(), outlineItem->GetLayer() );
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drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem.Type(), &outlineItem,
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outlineItem.GetClass(), outlineItem.GetLayer() );
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drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem,
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boardItem->GetClass(), boardItem->GetLayer() );
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@ -139,7 +140,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,
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outlineItem, boardItem );
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&outlineItem, boardItem );
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int minClearance = constraint.GetValue().Min();
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int actual;
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@ -157,7 +158,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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MessageTextFromValue( userUnits(), actual ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( outlineItem, boardItem );
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drcItem->SetItems( &outlineItem, boardItem );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, (wxPoint) pos );
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@ -171,20 +172,20 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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boardItems.clear();
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forEachGeometryItem( {}, LSET( 2, F_SilkS, B_SilkS ), queryBoardGeometryItems );
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for( PCB_SHAPE* outlineItem : boardOutline )
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for( const PCB_SHAPE& outlineItem : boardOutline )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
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break;
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const std::shared_ptr<SHAPE>& refShape = outlineItem->GetEffectiveShape();
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const std::shared_ptr<SHAPE>& refShape = outlineItem.GetEffectiveShape();
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for( BOARD_ITEM* boardItem : boardItems )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
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break;
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drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem->Type(), outlineItem,
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outlineItem->GetClass(), outlineItem->GetLayer() );
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drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem.Type(), &outlineItem,
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outlineItem.GetClass(), outlineItem.GetLayer() );
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drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem,
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boardItem->GetClass(), boardItem->GetLayer() );
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@ -194,7 +195,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
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outlineItem, boardItem );
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&outlineItem, boardItem );
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int minClearance = constraint.GetValue().Min();
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int actual;
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@ -216,7 +217,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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drcItem->SetErrorMessage( m_msg );
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}
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drcItem->SetItems( outlineItem, boardItem );
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drcItem->SetItems( &outlineItem, boardItem );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, (wxPoint) pos );
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