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Allow non-identical schematic/pcb nets 

The schematic net names are fully unique but if we have multiple pads
that are mapped to a NC pin, they need to have unique net names so that
they do not get connected to each other in the ratsnest.  This breaks
the schematic parity check as we have modified the netname for some
pads.  To work around this, we first maintain the zero-th net without
suffix and then add an additional check in DRC to ensure that we allow
unconnected nets as long as the share a common prefix with the schematic
netname.
This commit is contained in:
Seth Hillbrand 2024-04-15 17:40:04 -07:00
parent ea904c9fb1
commit f61d400d88
6 changed files with 1090 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
pcbnew/drc/drc_test_provider_schematic_parity.cpp
View File

@ -213,7 +213,10 @@ void DRC_TEST_PROVIDER_SCHEMATIC_PARITY::testNetlist( NETLIST& aNetlist )
drcItem->SetItems( pad );
reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER );
}
else if( pcb_netname != sch_net.GetNetName() )
else if( pcb_netname != sch_net.GetNetName()
&& !( pcb_netname.starts_with(
wxT( "unconnected-" ) )
&& pcb_netname.starts_with( sch_net.GetNetName() ) ) )
{
wxString msg;
msg.Printf( _( "Pad net (%s) doesn't match net given by schematic (%s)." ),

4
pcbnew/netlist_reader/board_netlist_updater.cpp
View File

@ -774,7 +774,9 @@ bool BOARD_NETLIST_UPDATER::updateComponentPadConnections( FOOTPRINT* aFootprint
if( pad->IsNoConnectPad() )
{
for( int jj = 0; !padNetnames.insert( netName ).second; jj++ )
netName = wxString::Format( wxS( "%s" ), net.GetNetName() );
for( int jj = 1; !padNetnames.insert( netName ).second; jj++ )
netName = wxString::Format( wxS( "%s_%d" ), net.GetNetName(), jj );
}

312
qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pcb Normal file
View File

@ -0,0 +1,312 @@
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(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(pad_to_mask_clearance 0)
(allow_soldermask_bridges_in_footprints no)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
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(net 1 "unconnected-(TP1-Pad1)")
(net 2 "unconnected-(TP1-Pad1)_0")
(footprint "TestPoint:TestPoint_Bridge_Pitch2.0mm_Drill0.7mm"
(layer "F.Cu")
(uuid "5680b68d-7137-4930-9dd5-5f4fafc5da8a")
(at 138.030698 95.032002)
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(tags "test point wire loop")
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(net 2 "unconnected-(TP1-Pad1)_0")
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(gr_text "There should be no schematic parity errors\nhere because NC pads share a common \nprefix with the test point"
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582
qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pro Normal file
View File

@ -0,0 +1,582 @@
{
"board": {
"3dviewports": [],
"design_settings": {
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"other_text_thickness": 0.15,
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},
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"bus_to_bus_conflict": "error",
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"different_unit_net": "error",
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"duplicate_sheet_names": "error",
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"global_label_dangling": "warning",
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"label_dangling": "error",
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"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
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"pinned_symbol_libs": []
},
"meta": {
"filename": "unconnected-netnames.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
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"clearance": 0.2,
"diff_pair_gap": 0.25,
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"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
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"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 3
},
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"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
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"name": "CSV",
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},
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{
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"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
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187
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3
qa/tests/pcbnew/drc/test_drc_regressions.cpp
View File

@ -62,7 +62,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR
"issue11814", // Bad cache hit in isInsideArea
"issue12609", // Arc collison edge case
"issue14412", // Solder mask bridge between pads in a net-tie pad group
"issue15280" // Very wide spokes mis-counted as being single spoke
"issue15280", // Very wide spokes mis-counted as being single spoke
"unconnected-netnames/unconnected-netnames", // Raised false schematic partity error
};
for( const wxString& relPath : tests )