kicad2step: fix a bug when the board has no hole.
kicad2step was trying to remove an empty hole list, generating a OCC error. Fixes #4242 https://gitlab.com/kicad/code/kicad/issues/x4242
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@ -312,7 +312,7 @@ bool KICADMODULE::ComposePCB( class PCBMODEL* aPCB, S3D_RESOLVER* resolver,
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double posX = m_position.x - aOrigin.x;
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double posX = m_position.x - aOrigin.x;
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double posY = m_position.y - aOrigin.y;
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double posY = m_position.y - aOrigin.y;
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for( auto i : m_curves )
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for( KICADCURVE* i : m_curves )
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{
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{
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if( i->m_layer != LAYER_EDGE || CURVE_NONE == i->m_form )
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if( i->m_layer != LAYER_EDGE || CURVE_NONE == i->m_form )
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continue;
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continue;
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@ -320,7 +320,8 @@ bool KICADPCB::parseSetup( SEXPR::SEXPR* data )
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if( !child->IsList() )
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if( !child->IsList() )
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{
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{
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ReportMessage( wxString::Format( "corrupt PCB file (line %d)\n", child->GetLineNumber() ) );
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ReportMessage( wxString::Format(
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"corrupt PCB file (line %d)\n", child->GetLineNumber() ) );
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return false;
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return false;
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}
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}
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@ -330,8 +331,9 @@ bool KICADPCB::parseSetup( SEXPR::SEXPR* data )
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{
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{
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if( child->GetNumberOfChildren() != 3 )
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if( child->GetNumberOfChildren() != 3 )
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{
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{
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ReportMessage( wxString::Format( "corrupt PCB file (line %d): grid_origin has %d children (expected: 3)\n",
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ReportMessage( wxString::Format(
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child->GetLineNumber(), child->GetNumberOfChildren() ) );
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"corrupt PCB file (line %d): grid_origin has %d children (expected: 3)\n",
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child->GetLineNumber(), child->GetNumberOfChildren() ) );
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return false;
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return false;
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}
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}
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@ -343,8 +345,9 @@ bool KICADPCB::parseSetup( SEXPR::SEXPR* data )
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{
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{
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if( child->GetNumberOfChildren() != 3 )
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if( child->GetNumberOfChildren() != 3 )
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{
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{
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ReportMessage( wxString::Format( "corrupt PCB file (line %d)m: aux_axis_origin has %d children (expected: 3)\n",
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ReportMessage( wxString::Format(
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child->GetLineNumber(), child->GetNumberOfChildren() ) );
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"corrupt PCB file (line %d)m: aux_axis_origin has %d children (expected: 3)\n",
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child->GetLineNumber(), child->GetNumberOfChildren() ) );
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return false;
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return false;
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}
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}
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@ -260,7 +260,6 @@ bool PCBMODEL::AddOutlineSegment( KICADCURVE* aCurve )
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ReportMessage( msg );
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ReportMessage( msg );
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return false;
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return false;
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}
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}
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}
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}
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else
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else
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{
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{
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@ -778,6 +777,7 @@ bool PCBMODEL::CreatePCB()
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}
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}
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}
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}
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#else // Much faster than first version: group all holes and cut only once
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#else // Much faster than first version: group all holes and cut only once
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if( m_cutouts.size() )
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{
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{
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BRepAlgoAPI_Cut Cut;
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BRepAlgoAPI_Cut Cut;
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TopTools_ListOfShape mainbrd;
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TopTools_ListOfShape mainbrd;
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@ -794,6 +794,7 @@ bool PCBMODEL::CreatePCB()
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board = Cut.Shape();
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board = Cut.Shape();
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}
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}
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#endif
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#endif
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// push the board to the data structure
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// push the board to the data structure
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ReportMessage( "\nGenerate board full shape\n" );
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ReportMessage( "\nGenerate board full shape\n" );
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m_pcb_label = m_assy->AddComponent( m_assy_label, board );
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m_pcb_label = m_assy->AddComponent( m_assy_label, board );
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